JP5278080B2 - Manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device capable of controlling the density of the dimension and distribution of a quantum dot separately, and reducing an influence of a potential barrier caused by a grain boundary. <P>SOLUTION: Semiconductor fine grains are distributed on a surface of a semiconductor substrate by supplying a plurality of semiconductor fine grains to the surface. Semiconductor fine grains are heated to a temperature in which semiconductor fine grains distributed on the surface of the semiconductor substrate are deformed. A semiconductor film grows on the semiconductor substrate so as to cover deformed semiconductor fine grains. <P>COPYRIGHT: (C)2011,JPO&amp;INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor element including a plurality of semiconductor fine particles.

  Using semiconductor quantum dots having a three-dimensional quantum confinement effect, optical semiconductor elements such as high-performance laser diodes and optical amplifiers are realized. In general, Stranski-Krastanov Growth mode (SK mode) is used to form an active layer containing semiconductor quantum dots. In the method using the SK mode, it is difficult to independently control the size of the quantum dots that are parameters for determining the emission wavelength and the distribution density of the quantum dots that are parameters for determining the gain of the semiconductor optical device. It is.

  By supplying semiconductor fine particles (nanocrystals) dispersed in an organic solvent onto the substrate together with the raw material of the semiconductor layer serving as a base, a quantum dot structure in which the semiconductor fine particles are dispersed in the semiconductor layer can be formed. In this quantum dot structure, the base semiconductor layer is polycrystalline, and the semiconductor fine particles and the semiconductor layer do not have an epitaxial relationship. By increasing the carrier density of the semiconductor layer, the potential barrier due to the grain boundary is reduced to such an extent that does not hinder carrier movement.

International Publication No. 2005/043656 International Publication No. 2005/071764

A. A. Guzelian et al., "Synthesis of Size-Selected, Surface-Passivated InP Nanocrystals", J. Phys. Chem., Vol.100, No.17 (1996), pp.7212-7219 BO Dabbousi et al., "(CdSe) ZnS Core-Shell Quantum Dots: Synthesis and Characterization of a Size Series of Highly Luminescent Nanocrystallites", J. Phys. Chem., Vol. 101, No. 46 (1997), pp. 9463-9475

  An object of the present invention is to provide a method for manufacturing a semiconductor device, in which the size and distribution density of quantum dots can be controlled independently, and the influence of potential barriers caused by grain boundaries can be reduced. .

A method of manufacturing a semiconductor device that solves the above problems is as follows.
Supplying a plurality of semiconductor fine particles to the surface of the semiconductor substrate to distribute the semiconductor fine particles on the surface;
Heating the semiconductor fine particles to a temperature at which the semiconductor fine particles distributed on the surface of the semiconductor substrate are independently deformed;
And a step of growing a semiconductor film on the semiconductor substrate so as to cover the deformed semiconductor fine particles.

  The size and distribution density of the semiconductor fine particles can be controlled independently. In addition, when solid phase epitaxial growth of semiconductor fine particles is performed during heating, potential barriers due to grain boundaries can be prevented.

FIG. 3 is a cross-sectional view of a semiconductor element in the middle of manufacturing of the manufacturing method according to Example 1. FIG. 4 is a cross-sectional view of a semiconductor element in a manufacturing intermediate stage of the manufacturing method according to Example 1, and a cross-sectional view of the manufactured semiconductor element. 1 is a schematic view of a semiconductor fine particle supply apparatus used in a manufacturing method according to Example 1. FIG. It is sectional drawing of the semiconductor element in the manufacture middle stage of the manufacturing method by Example 2, and sectional drawing of the manufactured semiconductor element. FIG. 6 is a cross-sectional view of a semiconductor element in a manufacturing stage of a manufacturing method according to Example 3, and a cross-sectional view of the manufactured semiconductor element. FIG. 10 is a cross-sectional view of a semiconductor element in the middle of manufacturing of a manufacturing method according to Example 4; FIG. 10 is a cross-sectional view of a semiconductor element in a manufacturing stage of the manufacturing method according to Example 4 and a cross-sectional view of the manufactured semiconductor element.

  Embodiments of the present invention will be described with reference to the drawings.

  With reference to FIGS. 1A to 1E and FIG. 2, a method for manufacturing a semiconductor device according to Example 1 will be described.

As shown in FIG. 1A, a GaAs buffer layer 10B is formed on a GaAs base substrate 10A by metal organic chemical vapor deposition (MOCVD). The GaAs base substrate 10 </ b> A and the GaAs buffer layer 10 </ b> B are simply referred to as “semiconductor substrate” 10. The growth conditions of the GaAs buffer layer 10B are, for example, as follows.
・ Ga raw material Triethylgallium (TEGa)
・ As raw material arsine (AsH ₃ )
-Substrate temperature 550 ° C-650 ° C
-Atmosphere Hydrogen atmosphere After forming the buffer layer 10B, the temperature of the semiconductor substrate 10 is set within a range of 350C to 500C. A colloidal solution in which a plurality of semiconductor fine particles 20 are dispersed in an organic solvent is used as a raw material, and the plurality of semiconductor fine particles 20 are supplied to the surface of the semiconductor substrate 10. Thereby, a plurality of semiconductor fine particles 20 are distributed on the surface of the semiconductor substrate 10.

  FIG. 2 shows a schematic view of an apparatus for supplying the semiconductor fine particles 20. A colloidal solution 31 in which the semiconductor fine particles 20 are dispersed in an organic solvent such as toluene is accommodated in the raw material container 30. Each of the semiconductor fine particles 20 is tri-n-octylphosphine (TOP), tri-n-octylphosphine oxide (TOPO), hexadecylamine (so that it is uniformly dispersed without aggregation in an organic solvent. It is coated with organic molecules 21 such as HDA). A stage 34 is stored in the chamber 33. The semiconductor substrate 10 is disposed on the stage 34. The stage 34 can heat the semiconductor substrate 10.

  When a carrier gas such as hydrogen gas is introduced into the raw material container 30, the colloidal solution 31 is transported into the vaporizer 32. A carrier gas such as hydrogen gas is introduced into the vaporizer 32 by a different route from the carrier gas introduced into the raw material container 30. The vaporizer 32 heats the colloidal solution to a temperature in the range of 100 ° C to 300 ° C. The organic solvent toluene or the like evaporates, and the semiconductor fine particles 20 covered with the organic molecules 21 are introduced into the chamber 33 together with the carrier gas. The semiconductor fine particles 20 introduced into the chamber 33 are supplied to the surface of the semiconductor substrate 10 and distributed discretely on the surface. The distribution density of the semiconductor fine particles 20 on the surface of the semiconductor substrate 10 can be controlled by the flow rate and supply time of the semiconductor fine particles 20.

  The semiconductor fine particles 20 not deposited on the surface of the semiconductor substrate 10 are discharged out of the chamber through the exhaust pipe 35 together with the carrier gas. A raw material for forming the semiconductor film is supplied into the chamber 33 via the pipe 36.

  FIG. 1B shows an enlarged cross-sectional view of the semiconductor fine particles 20 dispersed on the surface of the semiconductor substrate 10. The semiconductor fine particle 20 includes a substantially spherical core 20C and a shell 20S covering the core 20C. The core 20C is made of InAs, and the shell 20S is made of GaAs. The diameter of the core 20C is in the range of 3 nm to 10 nm, for example. However, the diameter of the core 20C is not widely distributed within this range, but is concentrated in the vicinity of a specific value within this range. That is, the semiconductor fine particles 20 having a specific size can be distributed on the surface of the semiconductor substrate 10.

In the step of supplying the semiconductor fine particles 20 to the surface of the semiconductor substrate 10, the semiconductor fine particles 20 are supplied to the surface of the semiconductor substrate 10 while maintaining the temperature of the semiconductor substrate 10 at 350 to 500 ° C. After a predetermined amount of the semiconductor fine particles 20 is supplied, the apparatus waits for 1 second to 1 minute in a state where only the carrier gas is supplied into the chamber 20. During standby, the organic molecules 21 that have covered the semiconductor fine particles 20 are decomposed and removed. In order to prevent the removed organic molecules from remaining on the surface of the semiconductor substrate 10, hydride AsH ₃ may be supplied into the chamber 33.

  FIG. 1C shows a cross-sectional view of the semiconductor fine particles 20 and the semiconductor substrate 10 after the organic molecules 21 are removed.

Processes up to the state shown in FIG. 1D will be described. While supplying AsH ₃ into the chamber 33, the temperature of the semiconductor substrate 10 is raised to a temperature within the range of 450 ° C. to 600 ° C. Maintain the elevated temperature for 1 to 5 minutes. Thereby, the semiconductor fine particles 20 are thermally deformed and become flat. During this thermal deformation, solid phase epitaxial growth occurs, and the semiconductor substrate 10 and the semiconductor fine particles 20 have an epitaxial relationship. The reason why AsH ₃ is supplied at the time of thermal deformation is to suppress the deviation of As from the semiconductor substrate 10 and the semiconductor fine particles 20. The degree of flatness can be controlled by adjusting the heat treatment temperature and the heat treatment time.

  As shown in FIG. 1E, a semiconductor layer 25 made of single crystal GaAs is epitaxially grown on the semiconductor substrate 10 by, for example, MOCVD so as to cover the deformed semiconductor fine particles 20. The semiconductor fine particles 20 and the semiconductor layer 25 have an epitaxial relationship.

  Through the steps so far, a semiconductor element in which a plurality of semiconductor fine particles 20 are distributed on the surface of the semiconductor substrate 10 is obtained. The core 20 </ b> C of the semiconductor fine particle 20 is formed of InAs, which has a narrower forbidden band than the GaAs semiconductor substrate 10 and the GaAs semiconductor layer 25. For this reason, the semiconductor fine particles 20 function as quantum dots that trap carriers.

  By changing the size of the semiconductor fine particles 20 to be dispersed in the colloidal solution, the size of the quantum dots can be changed. In the step of supplying the semiconductor fine particles 20 to the surface of the semiconductor substrate 10, the distribution density of the quantum dots can be changed by changing the supply amount, that is, the flow rate and the supply time. In this way, the size and distribution density of the quantum dots can be controlled independently.

  The crystals forming the semiconductor substrate 10 and the semiconductor layer 25 and the crystals forming the semiconductor fine particles 20 have an epitaxial relationship. That is, there is no grain boundary at the interface between the two. For this reason, carriers can be efficiently injected into the semiconductor fine particles 20 from the semiconductor substrate 10 and the semiconductor layer 25.

  In the first embodiment, the semiconductor fine particle 20 has a double structure in which the core 20C is covered with the shell 20S. However, only the core 20C that is not covered with the shell 20S may be used. However, when a part of the organic molecule 21 remains on the surface of the semiconductor fine particle 20, an interface state is generated at the interface between the semiconductor fine particle 20 and the organic molecule 21. If the core 20C is covered with the shell 20S, the core 20C is less affected by the interface state.

  In Example 1, GaAs is used for the semiconductor layer 25 in which the quantum dots are embedded and the surface layer portion (buffer layer) 10B of the semiconductor substrate 10, but other semiconductor materials may be used. The semiconductor material used for the semiconductor layer 25 and the buffer layer 10 </ b> B has a forbidden band wider than that of the semiconductor material used for the core 20 </ b> C of the semiconductor fine particles 20. Further, the material of the base substrate 10A need not be the same as the material of the buffer layer 10B and the semiconductor layer 25. For example, when a GaAs substrate is used as the base substrate 10A, AlGaAs or InGaAs may be used for the buffer layer 10B and the semiconductor layer 25. In the case where InGaAs is used for the buffer layer 10B and the semiconductor layer 25, the film thickness is preferably set in a range in which strain relaxation does not occur, that is, in a range not exceeding the critical film thickness. When an InP substrate is used as the base substrate 10A, InGaAsP, AlGaInAs, or the like may be used for the buffer layer 10B and the semiconductor layer 25. In addition to a III-V compound semiconductor, a II-VI compound semiconductor may be used.

  Examples of combinations of the material of the core 20C, the material of the shell 20S, and the material of the buffer layer 10B and the semiconductor layer 25 are shown in the following table.

半導体微粒子２０が有機溶媒中に分散されたコロイド状溶液は、例えばEvident Technologies Inc., Sigma-Aldrich, Nanoco Technologies Limited等から入手すすることができる。

A colloidal solution in which the semiconductor fine particles 20 are dispersed in an organic solvent can be obtained from, for example, Evident Technologies Inc., Sigma-Aldrich, Nanoco Technologies Limited.

  With reference to FIGS. 3A to 3D, description will be made on a method of manufacturing a semiconductor device (buried semiconductor laser device) according to the second embodiment.

An n-type InP lower cladding layer 41 is epitaxially grown on an n-type InP semiconductor substrate 40 having a (100) plane as a main surface. The thickness of the lower cladding layer 41 is, for example, 300 nm to 500 nm, and the n-type impurity concentration is, for example, 5 × 10 ¹⁷ cm ⁻³ . The lower clad layer 41 is formed by, for example, MOCVD. The film forming conditions are, for example, as follows.
Raw materials Phosphine (PH ₃ ), trimethylindium (TMIn), disilane (Si ₂ H ₆ )
・ Substrate temperature 600 ℃ ～ 650 ℃
・ Pressure 6.7 × 10 ³ Pa
An active layer 43 having a multiple quantum dot structure is formed on the lower cladding layer 41. The active layer 43 is formed by alternately stacking a barrier layer 43B having a thickness of 100 nm and a plurality of quantum dots 43D distributed on the surface thereof. The barrier layer 43B is made of InGaAsP. For example, by setting the In composition ratio to 0.85 and the P composition ratio to 0.67, an unstrained barrier layer 43B having a transition wavelength of 1.1 μm can be obtained. The film formation conditions of the barrier layer 43B are, for example, as follows.
Raw materials TMIn, TEGa, AsH ₃ , PH ₃
・ Substrate temperature 600 ℃ ～ 650 ℃
・ Pressure 6.7 × 10 ³ Pa
For the formation of the quantum dots 43D, semiconductor fine particles including an InAs core and an InP shell are used. Hereinafter, a method for forming the quantum dots 43D will be specifically described.

After forming the barrier layer 43B, the substrate temperature is lowered to a range of 350 ° C. to 450 ° C. After the substrate temperature is stabilized, semiconductor fine particles are distributed on the surface of the barrier layer 43B in the same manner as in the first embodiment. For example, if the concentration of the colloidal solution is 1 μmol / liter, the flow rate of the solution is 10 ccm, and the supply time is 6 seconds, 6 × 10 ¹³ semiconductor particles are introduced into the chamber. Assuming that the diameter of the substrate is 2 inches and the ratio of the semiconductor fine particles introduced into the chamber to reach the substrate surface is 10%, the distribution density of the quantum dots 43D is 3 × 10 ¹¹ cm ⁻² . When the diameter of the quantum dot is 7 nm, the emission wavelength is 1.55 μm.

  The active layer 43 is formed by repeating the formation of the barrier layer 43B and the formation of the quantum dots 43D a plurality of times. The number of repetitions is, for example, 10 times. The number of repetitions may be in the range of 5 to 10 times.

  A mask pattern 45 such as silicon oxide is formed on the active layer 43.

  As shown in FIG. 3B, the mesa 46 is formed by etching the surface layer portions of the active layer 43 and the lower cladding layer 41 using the mask pattern 45 as an etching mask. The mesa 46 extends in one direction on the surface of the semiconductor substrate 40.

  As shown in FIG. 3C, a p-type InP buried layer 48 is formed on both sides of the mesa 46 using the mask pattern 45 as a mask for selective growth. The buried layer 48 covers the upper surface of the lower cladding layer 41 and the side surface of the mesa 46. Further, an n-type InP current blocking layer 49 is formed on the buried layer 48. After forming the current blocking layer 49, the mask pattern 45 is removed.

As shown in FIG. 3D, a p-type InP upper cladding layer 50 is formed on the mesa 46 and the current blocking layer 49. Further, a p-type InGaAs contact layer 51 is formed thereon. The impurity concentration of the upper cladding layer 50 is 1 × 10 ¹⁸ cm ^−3, and the impurity concentration of the contact layer 51 is 1 × 10 ¹⁹ cm ⁻³ .

  An n-side electrode 53 is formed on the back surface of the semiconductor substrate 40, and a p-side electrode 54 is formed on the contact layer 51. Electrons and holes are supplied from the n-side electrode 53 and the p-side electrode 54 into the quantum dot 43D, respectively.

  Thereafter, the semiconductor substrate 40 is cleaved, and an antireflection film is formed on the cleaved surface. An optical resonator is defined by the pair of cleavage planes, and a waveguide structure including the quantum dots 43D and the barrier layer 43B is defined in the optical resonator.

  The dispersion of the size of the quantum dots 43D is smaller than the dispersion of the sizes of the quantum dots formed using the SK mode. For this reason, the spread of the spectrum of the emission wavelength can be narrowed. Since the distribution density of the quantum dots 43D can be set independently of the size of the quantum dots 43D, a desired gain can be obtained independently of the emission wavelength.

  In Example 1, the quantum dots 43D and the surrounding barrier layer 43B have an epitaxial relationship. Since the potential barrier due to the grain boundary is not formed, it is possible to suppress a decrease in the efficiency of current injection into the quantum dots 43D.

  With reference to FIGS. 4A to 4C, a method of manufacturing a semiconductor device (ridge-type semiconductor laser device) according to Example 3 will be described.

As shown in FIG. 4A, an n-type AlGaAs lower cladding layer 61 is formed on an n-type GaAs semiconductor substrate 60 by MOCVD. Trimethylaluminum (TMAl), TEGa, AsH ₃ , and Si ₂ H ₆ are used as raw materials. The Al composition ratio of the lower cladding layer 61 is, for example, 0.4. An active layer 63 having a multiple quantum dot structure is formed on the lower cladding layer 61. The active layer 63 is formed by alternately laminating a GaAs barrier layer 63B and a plurality of quantum dots 63D distributed on the surface thereof. The barrier layer 63B is formed by MOCVD. The quantum dots 63D are formed in the same manner as in Example 1 using semiconductor fine particles including an InAs core and a GaAs shell.

    The active layer 63 is formed by repeating the formation of the barrier layer 63B and the formation of the quantum dots 63D a plurality of times. The number of repetitions is, for example, 10 times. The number of repetitions may be within the range of 5 to 10 times.

  A p-type AlGaAs upper cladding layer 65 and a p-type GaAs contact layer 66 are formed on the active layer 63. A mask pattern 67 such as silicon oxide is formed on the contact layer 66.

  As shown in FIG. 4B, the contact layer 66 and the upper cladding layer 65 are etched using the mask pattern 67 as an etching mask. The etching is stopped before reaching the bottom surface of the upper cladding layer 65. Thereby, the ridge 70 including the upper clad layer 65 and the contact layer 66 is formed. After the ridge 70 is formed, the mask pattern 67 is removed.

  As shown in FIG. 4C, a protective film 71 that covers the upper surface of the upper cladding layer 65 and the surface of the ridge 70 is formed. The protective film 71 is provided with an opening for exposing the contact layer 66. A p-side electrode 73 is formed on the contact layer 66 in the opening. An n-side electrode 74 is formed on the back surface of the semiconductor substrate 60.

  The semiconductor substrate 60 is cleaved, and an antireflection film is formed on the cleaved surface. An optical resonator is defined by the pair of cleavage planes. A waveguide structure including quantum dots 63D and a barrier layer 63B is defined in the optical resonator.

  In the third embodiment, as in the second embodiment, the spectrum of the emission wavelength can be narrowed, and the gain can be set independently of the emission wavelength.

  With reference to FIGS. 5A to 5G, a method of manufacturing a semiconductor device (vertical cavity surface emitting laser device) according to Example 4 will be described. On a silicon semiconductor substrate 80, a distributed Bragg reflection (DBR) mirror 81 in which silicon oxide films and polycrystalline silicon films are alternately stacked is formed. For example, in order to set the reflectance at a wavelength of 1.3 μm to 99%, the thickness of the polycrystalline silicon film is 96 nm, the thickness of the silicon oxide film is 225 nm, and the number of repetitions is 4 or more. It is also possible to configure the DBR mirror using other dielectric materials. A single crystal silicon substrate 85 is bonded to the surface of the DBR mirror 81.

  As shown in FIG. 5B, the single crystal silicon substrate 85 is polished to be thinned. Thereby, a semiconductor layer 85a of single crystal silicon is formed.

As shown in FIG. 5C, an n-type layer 86 of n-type SiGeC is formed on the semiconductor layer 85a by MOCVD. For example, Si ₂ H ₆ , germane (GeH ₄ ), and monomethylsilane (SiH ₃ CH ₃ ) are used as raw materials. The growth temperature of the n-type layer 86 is 650 ° C., for example. The n-type layer 86 is doped with As as an n-type impurity, and its concentration is 1 × 10 ¹⁸ cm ⁻³ .

  An active layer 87 is formed on the n-type layer 86. The active layer 87 is formed by alternately stacking a SiGeC barrier layer 87B having a thickness of 50 nm and a plurality of quantum dots 87D distributed on the surface thereof. The quantum dots 87 are formed by a method similar to the method according to the first embodiment, using, for example, semiconductor fine particles including an InSb core and an InAs shell. The number of repetitions of the formation of the barrier layer 87B and the formation of the quantum dots 87D is, for example, 7 times. The number of repetitions may be in the range of 3 to 7 times.

A p-type layer 88 of p-type SiGeC is formed on the active layer 87 by MOCVD. The p-type layer 88 is doped with B as a p-type impurity, and its concentration is 1 × 10 ¹⁸ cm ⁻³ .

  As shown in FIG. 5D, a mesa 90 is formed by etching the surface layer portions of the p-type layer 88, the active layer 87, and the n-type layer 86 using an etching mask.

  As shown in FIG. 5E, an insulating film 92 such as silicon oxide is deposited on the n-type layer 86 and the mesa 90. The surface of the insulating film 90 is planarized until the p-type layer 88 is exposed.

As shown in FIG. 5F, a p-type layer 93 of polycrystalline p-type Si is formed by MOCVD on the mesa 90 and the planarized insulating film 92. The p-type layer 93 is doped with B as a p-type impurity, and the impurity concentration thereof is, for example, 1 × 10 ¹⁹ cm ⁻³ . The thickness of the p-type layer 93 is, for example, 100 nm. A DBR mirror 95 is formed on the p-type layer 93. The DBR mirror 95 has the same multilayer structure as the lower DBR mirror 81.

  As shown in FIG. 5G, the upper DBR mirror 95 is patterned. Further, the p-type layer 93 and the insulating film 92 are patterned so that the p-type layer 93 and the insulating film 92 include the upper DBR mirror 95 in plan view. A p-side electrode 96 is formed on the exposed surface of the p-type layer 93. An n-side electrode 97 is formed on the exposed surface of the n-type layer 86.

  In the fourth embodiment, as in the second embodiment, the spectrum of the emission wavelength can be narrowed, and the gain can be set independently of the emission wavelength.

  In the above Examples 2 to 4, the method for forming quantum dots according to Example 1 was applied to the manufacture of a semiconductor laser device. This quantum dot forming method can also be applied to the manufacture of semiconductor optical devices other than semiconductor laser devices, such as semiconductor optical amplifiers.

  In a polarization-independent semiconductor optical amplifier having the same amplification characteristic with respect to TE polarized light and TM polarized light, the shape of the quantum dots is preferably close to a sphere. In the thermal deformation process shown in FIG. 1D, a quantum dot close to a sphere can be formed by setting the heating temperature low and the heating time short. On the contrary, in the semiconductor laser element, it is preferable to increase the flatness of the quantum dots in order to relatively increase the gain of one polarized light, for example, TE polarized light. In the method according to the first embodiment, it is possible to control the flatness of the quantum dot shape.

  Although the present invention has been described with reference to the embodiments, the present invention is not limited thereto. It will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

10 Semiconductor substrate 10A Base substrate 10B Buffer layer (surface layer part)
20 Semiconductor fine particle 20C Core 20S Shell 21 Organic molecule 25 Semiconductor layer 30 Raw material container 31 Colloidal solution 32 Vaporizer 33 Chamber 34 Stage 35 Exhaust pipe 36 Pipe 40 Semiconductor substrate 41 Lower clad layer 43 Active layer 43B Barrier layer 43D Quantum dot 45 Mask Pattern 46 Mesa 48 Buried layer 49 Current blocking layer 50 Upper cladding layer 51 Contact layer 53 N-side electrode 54 P-side electrode 60 Semiconductor substrate 61 Lower cladding layer 63 Active layer 63B Barrier layer 63D Quantum dot 65 Upper cladding layer 66 Contact layer 67 Mask pattern 70 Ridge 71 Insulating film 73 P-side electrode 74 N-side electrode 80 Semiconductor substrate 81 DBR mirror 85 Silicon substrate 85a Single crystal silicon layer 86 N-type layer 87 Active layer 87B Barrier layer 87D Quantum dot 88 P-type layer 90 Mesa 9 Insulating film 93 p-type layer 95 DBR mirror 96 p-side electrode 97 n-side electrode

Claims (5)

Supplying a plurality of semiconductor fine particles to the surface of the semiconductor substrate to distribute the semiconductor fine particles on the surface;
Heating the semiconductor fine particles to a temperature at which the semiconductor fine particles distributed on the surface of the semiconductor substrate are independently deformed;
And a step of growing a semiconductor film on the semiconductor substrate so as to cover the deformed semiconductor fine particles. The step of dispersing the semiconductor fine particles,
2. The semiconductor device according to claim 1, further comprising: vaporizing a colloidal solution in which the semiconductor fine particles coated with organic molecules are colloidally dispersed in an organic solvent, and supplying the semiconductor fine particles to the surface of the semiconductor substrate. Production method.   The method of manufacturing a semiconductor element according to claim 1, wherein in the heating step, the deformed semiconductor fine particles and the surface layer portion of the semiconductor substrate are heated so as to have an epitaxial relationship.   4. The method of manufacturing a semiconductor element according to claim 1, wherein in the step of growing the semiconductor film, the semiconductor film is grown so that the semiconductor film and the semiconductor substrate have an epitaxial relationship. 5.   5. The method of manufacturing a semiconductor element according to claim 1, wherein in the step of growing the semiconductor film, the semiconductor film is grown so that the semiconductor film and the semiconductor fine particles have an epitaxial relationship.

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