JP5280097B2 - Switching regulator - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a switching regulator which is hard to be affected by switching noise. <P>SOLUTION: The switching regulator includes a comparator 12 generating a comparison signal Sa of feedback voltage Vfb and reference voltage Vref, an oscillator 14 generating a clock signal Sb, a latch circuit 15 generating a PWM signal Sc based on the comparison signal Sa and a clock signal Sb, and an output transistor 11 which is switching-controlled based on the PWM signal Sc (gate signal Sd) and in which switch voltage Vsw is pulled out from one end. The regulator includes mask circuits (17 and 18) smoothing switch voltage Vsw, generating desired output voltage Vo from input voltage Vi and pulling down feedback voltage Vfb to a prescribed voltage level until a mask period Tm elapses after the output transistor 11 is turned on. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

  The present invention relates to a switching regulator that generates a desired output voltage from an input voltage.

  FIG. 3 is a circuit diagram showing a conventional example of a switching regulator. The switching regulator of this conventional example compares a predetermined reference voltage Vref and a feedback voltage Vfb corresponding to the output voltage Vo, and compares the comparison signal Sa (more precisely, a logical sum signal of the comparison signal Sa and the mask signal Sm). Sa ′) and a predetermined clock signal Sb are used to generate a pulse width modulation signal Sc having a desired duty (hereinafter referred to as a PWM [Pulse Width Modulation] signal Sc), and then the gate signal of the output transistor 101 Sd is generated.

  In the conventional switching regulator, the output transistor 101 is turned on at the rising edge of the clock signal Sb and turned off at the falling edge of the logical sum signal Sa ′ (comparison signal Sa after masking processing). Therefore, a rectangular wave switch voltage Vsw corresponding to the ON / OFF state is drawn from the source of the output transistor 101 to which the input voltage Vi is applied to the drain, and the desired output voltage is smoothed. Vo is generated.

As an example of related art (particularly switching noise removal technique) related to the above, Patent Document 1 can be cited.
JP 2005-295754 A

  Certainly, with the conventional switching regulator shown in FIG. 3, it is possible to generate a desired output voltage Vo from the input voltage Vi with a very simple configuration.

  By the way, the conventional switching regulator performs a switching noise (particularly, an output transistor) superimposed on the feedback voltage Vfb by performing a masking process (OR operation with the mask signal Sm) on the comparison signal Sa output from the comparator 102. In this configuration, malfunction due to switching noise generated when the switch 101 is turned on is prevented.

  FIG. 4 is a timing chart showing a conventional noise removal operation. In order from the top, the switch voltage Vsw, the feedback voltage Vfb, the mask signal Sm, the comparison signal Sa, and the logical sum signal Sa ′ (comparison signal after masking processing). Sa) is depicted.

  As shown in FIG. 4, the mask signal Sm is kept at a high level over a predetermined mask period Tm from the time when the output transistor 101 is turned on, and is kept at a low level during the remaining period. On the other hand, the comparison signal Sa is at a low level when the feedback voltage Vfb is higher than the reference voltage Vref, and is at a high level when it is low. The logical sum signal Sa 'is set to a high level when at least one of the comparison signal Sa and the mask signal Sm is at a high level, and is set to a low level when both are at a low level.

  Therefore, during the mask period Tm, the logical sum signal Sa ′ is maintained at a high level without depending on the logical level of the comparison signal Sa. Ideally, the influence of switching noise superimposed on the feedback voltage Vfb is exerted. It is possible to prevent malfunction caused by this.

  However, in the conventional switching regulator, the masking process does not function effectively due to the output delay inevitably generated in the comparator 102, and there is a possibility that the malfunction due to the switching noise cannot be prevented. The reason will be described below.

  In the conventional switching regulator, the timing at which the logic level of the comparison signal Sa is inverted is delayed by a delay time d from the timing at which the level relationship between the feedback voltage Vfb and the reference voltage Vref is inverted. That is, the comparison signal Sa is set to the low level after a delay time d after the feedback voltage Vfb becomes higher than the reference voltage Vref, and after the delay time d after the feedback voltage Vfb becomes lower than the reference voltage Vref. High level. For example, when the switching noise generated when the output transistor 101 is turned on is superimposed on the feedback voltage Vfb and the feedback voltage Vfb becomes higher than the reference voltage Vref, the comparison signal Sa becomes a low level after a delay time d. .

  In this case, the comparison signal Sa masked by the mask signal Sm is not the comparison signal Sa based on the level relationship between the feedback voltage Vfb and the reference voltage Vref inputted in real time at that time, but the delay signal d before. The comparison signal Sa is based on the level relationship between the feedback voltage Vfb and the reference voltage Vref that have been input to. Therefore, in the above conventional switching regulator, the mask period Tm includes the delay time d of the comparator 102, and the period during which the comparison signal Sa is substantially masked is shortened.

  Of course, as indicated by the symbol (a) in FIG. 4, even when switching noise is superimposed on the feedback voltage Vfb, no noise pulse is generated in the comparison signal Sa unless the feedback voltage Vfb exceeds the reference voltage Vref. Therefore, no particular problem occurs.

  Further, as indicated by reference numeral (b) in FIG. 4, even when switching noise is superimposed on the feedback voltage Vfb and the feedback voltage Vfb exceeds the reference voltage Vref, the feedback voltage Vfb exceeds the reference voltage Vref. When the period of time is sufficiently short, the comparison signal Sa returns to the high level by the end of the mask period Tm, so that the noise pulse generated in the comparison signal Sa is appropriately masked by the mask signal Sm. No particular problem occurs.

  However, as indicated by reference numeral (c) in FIG. 4, when the switching noise is superimposed on the feedback voltage Vfb and the feedback voltage Vfb exceeds the reference voltage Vref for a long period of time, the comparator 102 The problem due to the delay time d occurs. That is, in the code (c) in FIG. 4, since the feedback voltage Vfb has not yet fallen below the reference voltage Vref at the time point that is delayed by the delay time d of the comparator 102 from the end point of the mask period Tm, By the time, the comparison signal Sa cannot be returned to the high level, and remains at the low level. Therefore, at the end of the mask period Tm, both the comparison signal Sa and the mask signal Sm are at the low level, and the logical sum signal Sa ′ falls to the low level, so that the output voltage Vo has not reached the desired voltage level. Nevertheless, the output transistor 101 was turned off unintentionally.

  If the switching regulator is a switching regulator that once inputs a feedback voltage to an error amplifier to generate an error voltage, and inputs the error voltage to a comparator to generate a PWM signal, the conventional technique of Patent Document 1 is adopted. It is possible to eliminate the influence of switching noise by applying an appropriate filter within a range where the average voltage level does not fluctuate. However, as shown in FIG. 3, in the switching regulator that generates the PWM signal by directly inputting the feedback voltage to the comparator, the instantaneous voltage level of the feedback voltage is important in the feedback control of the output voltage. When the feedback voltage is filtered using a circuit or the like, the feedback control of the output voltage Vo may be hindered.

  In view of the above problems, an object of the present invention is to provide a switching regulator that is not easily affected by switching noise.

  In order to achieve the above object, a switching regulator according to the present invention includes a comparator that generates a comparison signal between a feedback voltage corresponding to an output voltage and a predetermined reference voltage, an oscillator that generates a clock signal of a predetermined frequency, A latch circuit that generates a pulse width modulation signal having a desired duty based on the comparison signal and the clock signal, an output transistor that is switching-controlled based on the pulse width modulation signal, and that draws a rectangular wave switch voltage from one end thereof, And a switching regulator that generates a desired output voltage from an input voltage by smoothing the switch voltage, and from when the output transistor is turned on until a predetermined mask period elapses. And a mask circuit for pulling down the feedback voltage to a predetermined voltage level. And it is configured as (first configuration) that.

  In the switching regulator having the first configuration, the mask circuit includes a switch connected between the input terminal of the comparator and a predetermined potential terminal, and ON / OFF of the switch in synchronization with the clock signal. A mask control circuit that performs control may be configured (second configuration).

  In the switching regulator having the second configuration, the mask circuit may be configured to have a first resistor on a pull-down path through the switch (third configuration).

  In the switching regulator having the third configuration, the mask circuit may be configured to have a second resistor on the feedback path to the comparator (fourth configuration).

  In the switching regulator having any one of the first to fourth configurations, the mask control circuit includes a time constant circuit or a timer circuit as a means for setting the mask period (fifth (fifth). (Configuration).

  According to the present invention, it is possible to provide a switching regulator that is not easily affected by switching noise.

  FIG. 1 is a block diagram showing an embodiment of a switching regulator according to the present invention. As shown in FIG. 1, the switching regulator of the present embodiment includes a switching regulator IC 10, a diode (Schottky diode) D1, an inductor L1, a capacitor C1, and resistors R1 and R2 attached to the switching regulator IC 10. Become.

  The switching regulator IC 10 includes a P-channel MOS field effect transistor (output transistor) 11, a comparator 12, a DC voltage source 13, an oscillator 14, a latch circuit (RS flip-flop) 15, a pre-driver 16, an N-channel This is a semiconductor device formed by integrating a type MOS field effect transistor (switch) 17, a mask control circuit 18, a resistor 19x, and a resistor 19y.

  The source of the output transistor 11 is connected to the application terminal for the input voltage Vi. The drain of the output transistor 11 is connected to the cathode of the diode D1 and one end of the inductor L1. The anode of the diode D1 is connected to the ground terminal. The other end of the inductor L1 is connected to a load (not shown) as an extraction terminal for the output voltage Vo, and is also connected to the ground terminal through a path via the capacitor C1 and a path via the resistors R1 and R2. Yes.

  The non-inverting input terminal (+) of the comparator 12 is connected to the positive terminal (application terminal for the reference voltage Vref) of the DC voltage source 13. The negative terminal of the DC voltage source 13 is connected to the ground terminal. The inverting input terminal (−) of the comparator 12 is connected to one end of each of the resistor 19x and the resistor 19y (applied end of the feedback voltage Vfb). The other end of the resistor 19x is connected to the drain of the transistor 17. The source of the transistor 17 is connected to the ground terminal. The other end of the resistor 19y is connected to a connection node between the resistor R1 and the resistor R2.

  The reset terminal (R) of the latch circuit 15 is connected to the output terminal of the comparator 12. The set end (S) of the latch circuit 15 is connected to the output end of the oscillator 14. The output terminal (Q) of the latch circuit 15 is connected to the gate of the output transistor 11 via the pre-driver 16.

  The mask control circuit 18 is means for generating a mask signal Sm in synchronization with the clock signal Sb generated by the oscillator 14 and performing on / off control of the transistor 17 using this.

  Of the above components, the transistor 17, the mask control circuit 18, the resistor 19x, and the resistor 19y have a predetermined feedback voltage Vfb from when the output transistor 11 is turned on until a predetermined mask period Tm elapses. A mask circuit is formed to pull down to the voltage level of, which will be described in detail later.

  Next, a basic operation (generation operation of the output voltage Vo) of the switching regulator configured as described above will be described.

  When the desired output voltage Vo is generated from the input voltage Vi, the comparator 12 generates a comparison signal Sa between the feedback voltage Vfb corresponding to the output voltage Vo and a predetermined reference voltage Vref. More specifically, in the comparator 12, the comparison signal Sa is set to the high level when the feedback voltage Vfb is lower than the reference voltage Vref, and is set to the low level when it is high.

  On the other hand, the oscillator 14 generates a clock signal Sb having a predetermined frequency f (for example, 100 to 200 [kHz]) in order to determine the switching frequency of the output transistor 11.

  In the latch circuit 15, a PWM signal Sc having a desired duty is generated based on the comparison signal Sa and the clock signal Sb. More specifically, in the latch circuit 15, the PWM signal Sc is set to the high level at the rising edge of the clock signal Sb, and the PWM signal Sc is set to the low level at the falling edge of the comparison signal Sa. That is, in the latch circuit 15, when the PWM signal Sc is changed to the high level according to the clock signal Sb, the PWM signal Sc is maintained at the high level until the feedback voltage Vfb reaches the reference voltage Vref. When Vfb reaches the reference voltage Vref, the PWM signal Sc transitions to a low level. Accordingly, as the output voltage Vo is lower than the target value, the on-duty of the output transistor 11 increases, and as the target value is approached, the on-duty of the output transistor 11 decreases.

  In the pre-driver 16, the drive capability of the PWM signal Sc is increased, and the gate signal Sd of the output transistor 11 is generated.

  The output transistor 11 is switching-controlled based on the gate signal Sd, and a rectangular wave switch voltage Vsw is drawn from the drain thereof. The switch voltage Vsw is smoothed by a smoothing circuit including a diode D1, an inductor L1, and a capacitor C1, and a desired output voltage Vo is generated. The output voltage Vo is divided by a voltage dividing circuit composed of resistors R1 and R2, and the feedback voltage Vfb described above is generated.

  With such feedback control, the switching regulator of this embodiment generates a desired output voltage Vo from the input voltage Vi with a very simple configuration.

  Next, the noise removal operation of the switching regulator configured as described above will be described with reference to FIG. FIG. 2 is a timing chart showing the noise removal operation of the present invention, in which the switch voltage Vsw, the feedback voltage Vfb, the mask signal Sm, and the comparison signal Sa are depicted in order from the top.

  As shown in FIG. 2, the mask signal Sm is kept at a high level for a predetermined mask period Tm from the time when the output transistor 11 is turned on, and is maintained at a low level for the remaining period. On the other hand, the transistor 17 is turned on when the mask signal Sm is at a high level, and is turned off when the mask signal Sm is at a low level. That is, the feedback voltage Vfb applied to the inverting input terminal (−) of the comparator 12 is pulled down to a predetermined voltage level from when the output transistor 11 is turned on until a predetermined mask period Tm elapses.

  Therefore, the switching noise superimposed on the feedback voltage Vfb during the mask period does not affect the comparison operation (generation operation of the comparison signal Sa) in the comparator 12, and the comparison signal Sa is always maintained at the high level. Therefore, it is possible to prevent malfunction caused by switching noise.

  For example, in addition to the case indicated by reference numerals (a) and (b) in FIG. 2, the case indicated by reference numeral (c) in FIG. 2, that is, switching noise is superimposed on the feedback voltage Vfb, and the feedback voltage Even when Vfb exceeds the reference voltage Vref for a long period of time, the switching regulator according to the present invention can appropriately switch the switching noise without being affected by the output delay unavoidably generated by the comparator 12. It becomes possible to eliminate the influence.

  Thus, unlike the conventional configuration in which masking processing is performed on the comparison signal Sa output from the comparator 12, the configuration of the present invention in which masking processing is performed on the feedback voltage Vfb input to the comparator 12, Since the mask period Tm does not include the delay time d of the comparator 12, it is possible to eliminate the influence of switching noise without unnecessarily extending the mask period Tm. It becomes possible to improve the property.

  In the switching regulator having the above configuration, if the input voltage Vi is relatively large and large switching noise is likely to be generated when the output transistor 11 is turned on, the mask period Tm should be set sufficiently with priority given to improving the mask capability. It is desirable to set it long (for example, a mask period Tm of about 200 [ns] with respect to a minimum pulse width of 300 [ns] of the PWM signal Sc). On the other hand, if the input voltage Vi is relatively small and large switching noise is unlikely to occur when the output transistor 11 is on, it is desirable to set the mask period Tm short, giving priority to improving output accuracy at low duty. .

  At this time, the mask control circuit 18 may be configured to have a time constant circuit or a timer circuit that is activated by using the rising edge of the clock signal Sb as a trigger as means for setting the mask period Tm.

  In the switching regulator of this embodiment, the mask circuit is formed by inserting a resistor 19x on a pull-down path through the transistor 17. With such a configuration, it is possible to arbitrarily and easily set the voltage level of the feedback voltage Vfb during pull-down by adjusting the resistance value of the resistor 19x. In view of only the purpose of masking switching noise, the feedback voltage Vfb may be pulled down to the ground level. However, in this case, a return occurs after the pull-down is canceled, and feedback control of the output voltage Vo is performed. There is also a risk of trouble. For this reason, the voltage level of the feedback voltage Vfb at the time of pull-down should be set appropriately in consideration of the return delay.

  In the switching regulator of this embodiment, the mask circuit is formed by inserting a resistor 19y on the feedback path to the comparator 12. With such a configuration, the voltage level of the feedback voltage Vfb at the time of pull-down is less likely to fluctuate depending on the resistance values of the resistors R1 and R2, and the adjustment becomes easy. When the resistance values of the resistors R1 and R2 are several [kΩ] to several tens [kΩ], the resistance value of the resistor 19y may be set to about 10 [kΩ].

  In the above embodiment, the case where the present invention is applied to the step-down switching regulator has been described as an example. However, the application target of the present invention is not limited to this, and the step-up switching is not limited thereto. The regulator can also be widely applied.

  The configuration of the present invention can be variously modified within the scope of the present invention in addition to the above embodiment.

  The present invention is a useful technique for improving the stability and accuracy of output voltage in all applications using a switching regulator such as an ink jet printer.

These are block diagrams which show one Embodiment of the switching regulator which concerns on this invention. These are timing charts showing the noise removal operation of the present invention. These are block diagrams which show one prior art example of a switching regulator. These are timing charts showing a conventional noise removal operation.

Explanation of symbols

10 Switching regulator IC
11 P-channel MOS field effect transistor (output transistor)
12 Comparator 13 DC Voltage Source 14 Oscillator 15 Latch Circuit (RS Flip-Flop)
16 Pre-driver 17 N-channel MOS field effect transistor (switch)
18 Mask control circuit 19x, 19y Resistance D1 Diode (Schottky diode)
L1 Inductor C1 Capacitance R1, R2 Resistance

Claims (7)

A comparator that generates a comparison signal between a feedback voltage corresponding to the output voltage and a predetermined reference voltage, an oscillator that generates a clock signal of a predetermined frequency, and a pulse width modulation signal having a desired duty based on the comparison signal and the clock signal And a latch circuit that is switching-controlled based on the pulse width modulation signal, and an output transistor from which a rectangular wave-shaped switch voltage is drawn from one end thereof, and smoothing the switch voltage, A switching regulator that generates a desired output voltage from an input voltage,
A switching regulator comprising a mask circuit for pulling down the feedback voltage to a predetermined voltage level from when the output transistor is turned on until a predetermined mask period elapses.   The mask circuit includes a switch connected between an input terminal of the comparator and a predetermined potential terminal, and a mask control circuit that performs on / off control of the switch in synchronization with the clock signal. The switching regulator according to claim 1, comprising:   3. The switching regulator according to claim 2, wherein the mask circuit has a first resistor on a pull-down path through the switch.   4. The switching regulator according to claim 3, wherein the mask circuit includes a second resistor on a feedback path to the comparator. The switching regulator according to any one of claims 2 to 4, wherein the mask control circuit includes a time constant circuit or a timer circuit as means for setting the mask period.   An electric device having the switching regulator according to any one of claims 1 to 5.   An ink jet printer having the switching regulator according to claim 1.

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