JP5287261B2 - DC-DC converter - Google Patents

Description

  The present invention relates to a DC-DC converter that supplies a DC voltage with a predetermined magnitude to a load, and more particularly to a DC-DC converter having an overcurrent protection function in a pulse width modulation (PWM) control system.

  2. Description of the Related Art Conventionally, in notebook personal computers, mobile phones, and other portable electronic devices, a battery voltage is stepped down to a specified voltage by a DC-DC converter including a step-down switching power supply circuit and then supplied to an electronic circuit. The DC-DC converter responds to an overcurrent immediately when it is determined to be overcurrent by a pulse-by-pulse overcurrent protection system that monitors the inductor current every switching cycle. Restrictions can be made. For this reason, overcurrent protection circuits are used in a wide range of applications for the purpose of preventing overcurrent due to a load short circuit or the like.

  In the overcurrent protection circuit of the DC-DC converter, in order to monitor the inductor current, a method of detecting the inductor current by inserting a detection resistor in series with the inductor is adopted. However, since this detection method increases extra power loss due to the detection resistor, a method of detecting the inductor current via the conduction voltage of the output stage switch is preferred except for applications that require high accuracy.

  In order to monitor and limit the inductor current, there are a method in which peak current is detected to limit the current and a method in which bottom current is detected to limit the current. First, a method for detecting the peak current will be described.

FIG. 9 is a diagram illustrating an example of a conventional DC-DC converter that performs overcurrent protection based on the peak value of the inductor current.
This type of DC-DC converter is a switching semiconductor element (hereinafter referred to as a main switch) S1 composed of a P-channel field effect transistor (FET) having a source terminal connected to an input power source Vin such as a battery. And a synchronous rectification switch S2 made of an N-channel FET whose source terminal is grounded. The main switch S1 and the synchronous rectification switch S2 are configured to connect the drain terminals to each other and supply a PWM signal from the control circuit 1 through the driver circuits 2 and 3 as switching control signals to the respective gate terminals. Has been. In addition, a charging / smoothing output capacitor Cout and a load R are connected to a connection point between the main switch S1 and the synchronous rectification switch S2 via an inductor L with the other ends grounded.

  The inductor L and the output capacitor Cout constitute a filter circuit that supplies a smooth output voltage to the load R. In order to detect the output voltage Vout with respect to the load R, the output voltage Vout is supplied to the control circuit 1 as a negative feedback signal. In the control circuit 1, while monitoring the output voltage Vout, the main switch S1 and the synchronous rectification switch S2 are alternately turned on and off via the driver circuits 2 and 3 so that the output voltage Vout becomes a constant value. The switching terminal voltage Vsw is controlled.

The overcurrent detection circuit 4 is composed of, for example, a current transformer or a sense resistor and an amplifier. The overcurrent detection circuit 4 detects a current flowing through the main switch S1, that is, an inductor current IL flowing from the main switch S1 into the inductor _L, and uses this as a predetermined reference. Overcurrent is detected by comparing with the value. In this overcurrent detection circuit 4, when an overcurrent is detected, overcurrent limitation is performed so that the control circuit 1 controls the main switch S <b> 1 to a cut-off state.

  While the normal switching operation is being performed, the control circuit 1 changes the pulse width of the pulse signal for conducting / cutting off the main switch S1 and the synchronous rectification switch S2 according to the change of the output voltage Vout. The feedback control is performed so that the output voltage Vout becomes constant. Thereby, even when the supply current (output current) Iout to the load R is a heavy load, the energy stored in the inductor L according to the load R while the main switch S1 is in the cut-off state is synchronized with a low on-resistance. Since it is discharged through the rectifying switch S2, efficient synchronous rectification can be performed.

In the overcurrent detection circuit 4, when the peak value of the inductor current IL flowing through the inductor _L exceeds a predetermined value, the inductor current _IL is limited by cutting off the main switch S1 in preference to the PWM signal of the control circuit 1. Like to do.

FIG. 10 shows how the inductor current value changes depending on whether the output voltage Vout is large or small and the overcurrent protection function of the conventional DC-DC converter is operating. 4A shows a case where the output voltage Vout is large, and FIG. 4B shows a case where the output voltage Vout is small. The vertical axis shows the inductor current _IL and the horizontal axis shows time.

When the current (= I _L ) flowing through the main switch S1 on the input power source Vin side exceeds the specified value Ipmax, the DC-DC converter outputs a detection signal from the overcurrent detection circuit 4 and passes through the control circuit 1 to The main switch S1 is kept in the cutoff control state until the switching cycle. Thus, over-current limit function of limiting the peak current value Ip of the inductor current I _L equal to or less than the specified value Ipmax is achieved.

However, after a current exceeding the specified value Ipmax is detected by the actual overcurrent detection circuit 4, a certain delay time Td is required until the main switch S1 is switched off. Therefore, even if an overcurrent state is detected at the moment when the main switch S1 shifts to the conduction control state by the drive signal from the control circuit 1, the main switch S1 is actually cut off via the overcurrent detection circuit 4. In the meantime, the inductor current I _L continuously increases.

That is, when the inductor current I _L exceeds the specified value Ipmax, the decrease rate of the inductor current I _L is proportional to the output voltage Vout (dI _L / dt = Vout / L), and as shown in FIG. , if the output voltage is low Vout, as compared with a case high, a long time is required to decrease the inductor current I _L. Conversely, the increase rate of the inductor current I _L increases as the output voltage Vout decreases (dI _L / dt = (Vin−Vout) / L). Therefore, if the output voltage is low Vout, as shown in FIG. 10 (b), after the inductor current I _L has exceeded the prescribed value Ipmax also, the inductor current I _L by the delay time Td continues to rise with a large gradient. Then, the inductor current I _L that has increased up to that time cannot be reduced within the time in which the main switch S1 is controlled to be cut off, and the inductor current I _L starts to rise again in the next switching cycle.

Therefore, under the condition that the output voltage Vout is small and the operating frequency of the control circuit 1 is high, the current increase ((Vin−Vout) / L) during this period is the inductor current I _L until the main switch S1 becomes conductive next. There is a possibility that the limit of the inductor current I _L becomes ineffective, exceeding the decrease (Vout / L). Therefore, when the output voltage Vout is extremely lowered or an overcurrent state is continuously detected, an additional measure for stopping the DC-DC converter itself may be required.

Further, the peak current limit described above, performs the detection of the inductor current I _L by the current flowing through the main switch S1, after the conduction of the main switch S1 is a hard switching operation of the switching terminal voltage Vsw rises rapidly. For this reason, particularly when an output stage switching semiconductor element is externally attached, large noise is mixed. In order to avoid such an inconvenience, it is necessary to provide a blanking time for prohibiting the response of the overcurrent protection function and lengthen this blanking time.

Next, a bottom current limiting method for limiting the current on the synchronous rectifying switch S2 side will be described.
FIG. 11 is a diagram illustrating an example of a conventional DC-DC converter that performs overcurrent protection based on a bottom value of an inductor current.

Unlike the peak current limiting method, the bottom current limiting method extends the shut-off period of the main switch S1 in preference to the PWM signal of the control circuit 1 until the bottom value of the inductor current I _L falls below a predetermined value, and the inductor current I _L is limited. In other words, bottom current limit is because a method of waiting for a decrease in inductor current I _L, the inductor current I _L during the delay time in the overcurrent detection of the overcurrent detecting circuit 5 continues to decrease. For this reason, there is no possibility that the restriction of the inductor current I _L will not be effective even under the condition that the output voltage Vout of the DC-DC converter is low and the operating frequency of the PWM signal is high.

Further, the bottom current limiting scheme as shown in FIG. 11, the overcurrent detection circuit 5 detects the overcurrent state of the inductor current I _L on the basis of the current flowing through the synchronous rectification switch S2. When the synchronous rectification switch S2 is turned on, the inductor current I _L flows through the parallel diode, so that the switching terminal voltage Vsw is already lowered to perform a soft switching operation. Therefore, there is an advantage that noise for current detection is small.

From the above, it seems that bottom current limitation is easier to use for step-down switching power supply circuits. However, when selecting a method for limiting the inductor current I _L , compatibility with the output voltage control method of the DC-DC converter must be taken into consideration.

  For example, in pulse frequency modulation (PFM) control with a fixed ON time, the output voltage Vout is obtained by varying the operating frequency while fixing the ON time of the main switch S1 (hereinafter simply referred to as “ON time”). Is controlling. In the bottom current limitation, when an overcurrent is detected, the control circuit operation is interrupted to extend the off time of the main switch S1 (hereinafter simply referred to as “off time”). At this time, the on time remains fixed. Therefore, the compatibility between the PFM control with the fixed on-time and the bottom current limit is good (see, for example, Patent Document 1).

JP 2008-236859 A (paragraph numbers [0021] to [0029] and FIGS. 1 and 2)

  On the other hand, in the control method of the DC-DC converter, PWM control that operates at a fixed switching frequency is often employed. In the PWM control circuit, the on-time is varied by changing the duty ratio and the output voltage Vout is controlled under a constant frequency. Therefore, in the bottom current limit method, when the overcurrent is detected, the off time is extended to limit the inductor current. Therefore, the on time is extended to prevent the output voltage Vout from being lowered due to the current limit, and the current limit operation is disturbed. In the first place, compatibility is not good. However, since the bottom current limiting method has the above-described excellent properties, a current control circuit applicable to a DC-DC converter having a PWM control circuit has been desired.

FIG. 12 is a diagram illustrating an example of operation waveforms of a DC-DC converter with no limitation on on-time. Again, the vertical axis represents the inductor current I _L and the horizontal axis represents time.
I1 is the average current value of the inductor current I _L during the normal operation. Further, at the time of overcurrent detection, the overcurrent detection circuit 5 as bottom current of the inductor current I _L is the set value Iblim, off-time of the main switch S1 is extended by Textd. Since the output voltage Vout decreases only by increasing the off time, the control circuit increases the on time of the main switch S1 in order to prevent this. For this reason, the average current value of the inductor current I _L increases to the current I2 consumed by the load when the output voltage Vout is maintained at a desired value, and no current limitation is applied (the average of the inductor current I _L Value and peak value become large).

  The present invention has been made in view of these points, and an object of the present invention is to provide a DC-DC converter capable of appropriately limiting current when detecting overcurrent when PWM control and bottom current limitation are simultaneously applied. And

  In the present invention, in order to solve the above problem, a main switch (S1) connected to the high potential side of the input power supply and a synchronous rectification switch (series) connected in series with the main switch on the low potential side of the input power supply. S2), a filter circuit including an inductor and a smoothing capacitor connected to a connection point between the main switch and the synchronous rectification switch and supplying a smoothed output voltage to the load circuit, and pulse width modulation of the main switch and the synchronous rectification switch. There is provided a DC-DC converter comprising a control circuit (10) that is alternately turned on and off by (PWM) control. The control circuit has priority over the pulse width modulation control in the control circuit while the inductor current flowing through the inductor during the conduction control of the synchronous rectification switch exceeds the first set value (Iblim). An extension circuit (21) for extending the cut-off time and a duty ratio limiting circuit (30) for setting a predetermined upper limit (Ton-max) for the conduction time of the main switch (S1). The conduction time is limited.

  Furthermore, in the DC-DC converter of the present invention, the duty ratio limiting circuit (30) has a voltage limiting circuit that changes the upper limit value (Ton-max) in accordance with the extension period (Textd) of the main switch cutoff time. If the extension period of the main switch cutoff time is longer than the second set value (Tdb) set here, the upper limit value (Ton-max) is reduced, and if the extension period does not occur By changing the upper limit value (Ton-max) to increase, the peak value and average value of the inductor current at the time of overcurrent detection are reliably reduced.

  According to the present invention, it is possible to realize a DC-DC converter having an overcurrent protection function that is less affected by switching noise and that can reliably limit a current even when a short circuit occurs.

It is a circuit diagram which shows the DC-DC converter which concerns on embodiment. FIG. 2 is a circuit diagram illustrating an example of a delay circuit in the DC-DC converter of FIG. 1. It is a timing diagram which shows the operation | movement waveform of a delay circuit. FIG. 10 is a timing diagram illustrating operation waveforms of a third delay circuit. It is a circuit diagram which shows an example of the voltage limiting circuit in the DC-DC converter of FIG. FIG. 6 is a timing chart showing signal waveforms related to the operation of the duty ratio limiting circuit. It is a figure which shows an example of the operation waveform of a DC-DC converter when the maximum value (Ton-max) of on-time is provided and the value is fixed. It is a figure which shows an example of the operation waveform of the DC-DC converter which made variable the maximum value (Ton-max) of ON time. It is a figure which shows an example of the conventional DC-DC converter which performs overcurrent protection based on the peak value of an inductor current. It is a figure which shows how an inductor electric current value changes with the case where the overcurrent protection function of the conventional DC-DC converter is operating with the case where the output voltage Vout is large and the case where it is small. It is a figure which shows an example of the conventional DC-DC converter which performs overcurrent protection based on the bottom value of an inductor current. It is a figure which shows an example of the operation | movement waveform of a DC-DC converter with no restriction | limiting in ON time.

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram illustrating a DC-DC converter according to an embodiment.
The main switch S1 and the synchronous rectification switch S2 are connected in series between the input power source Vin and the ground to constitute an output stage. The source terminal of the main switch S1 is connected to the high potential side of the input power source Vin, its drain terminal is connected to the drain terminal of the synchronous rectification switch S2, and the source terminal of the synchronous rectification switch S2 is grounded.

  The inductor L and the output capacitor Cout constitute a filter circuit, which is connected to the connection point between the main switch S1 and the synchronous rectifier switch S2 and supplies a smooth output voltage to the load R. The output voltage Vout for the load R is supplied as a negative feedback signal Vd to the integrated circuit 10 constituting the PWM control circuit via a voltage detection circuit in which the dividing resistors R1 and R2 are connected in series.

  The integrated circuit 10 includes an error amplifier circuit 11 that outputs an error voltage Vea obtained by amplifying a difference voltage between the negative feedback signal Vd and the first reference voltage Vref, and a PWM comparator 12 that compares the error voltage Vea with the sawtooth voltage Vsaw. ing. The output terminal of the PWM comparator 12 is connected to a dead time (DT: Dead Time) generation circuit 14 via an AND circuit 13, and generates an on / off control signal to the main switch S1 and the synchronous rectification switch S2. That is, the PWM comparator 12 is connected to the gate terminal of the main switch S1 through the level shifter 15 and the driver circuit 16, and further connected to the gate terminal of the synchronous rectification switch S2 through the driver circuit 17 having a signal inversion function. . In the present embodiment, the main switch S1 is an N-channel FET, but it may be a P-channel FET as in the conventional DC-DC converter of FIG. In that case, the level shifter 15 becomes unnecessary, and the output of the DT generation circuit 14 is directly input to the driver circuit 16.

The integrated circuit 10 further includes an overcurrent detector 18, an oscillation circuit 20, and a duty ratio limiting circuit 30, and the overcurrent detection circuit 18 includes a drain terminal of the synchronous rectification switch S 2 and It is connected to input a voltage signal from the source terminal. In the overcurrent detection circuit 18, the drain of synchronous rectifier switch S2 - the current flowing from the source voltage to the synchronous rectifier switch S2, i.e. the magnitude of the inductor current I _L is detected, the bottom current set value Iblim which is set therein by comparison with, it is determined the overcurrent state of the inductor current I _L. More specifically, synchronous drain of the rectifier switch S2 - by comparing the bottom reference voltage corresponding to a source voltage and the bottom current set value Iblim, it is determined the overcurrent state of the inductor current I _L. An overcurrent determination signal Voc that is an output signal of the overcurrent detection circuit 18 is a signal that is H (High) if it is an overcurrent, and is L (Low) if it is not, and is an oscillation circuit via the inverter circuit IV1. 20 is output. Note that the overcurrent determination signal Voc is set at the H level while the synchronous rectification switch S2 is cut off.

  The oscillation circuit 20 includes an extension circuit 21, a first delay circuit 22, a comparator 23, and the like, and a sawtooth voltage Vsaw that is a voltage between terminals of the oscillation capacitor Cosc is output to the inverting input terminal of the PWM comparator 12. . The extension circuit 21 includes a P-channel FET (hereinafter referred to as a transistor) Mp1 and two N-channel transistors Mn1 and Mn2 connected in series between the power supply VDD and the ground, and an inverter circuit IV2. The gate terminal of Mn2 is connected to the output terminal of the inverter circuit IV1. The gate terminals of the transistors Mp1 and Mn1 are both connected to the output terminal of the inverter circuit IV2, and their drain terminals are connected to each other. The first clock signal Vck is output to the inverting input terminal of the AND circuit 13 and the duty ratio limiting circuit 30 from the connection point between the transistors Mp1 and Mn1.

  In addition to the oscillation capacitor Cosc, the oscillation circuit 20 includes an oscillation constant current source Iosc, a discharge switch Mosc composed of an N-channel transistor, an oscillation reference voltage Vosc, and the like. One end of the oscillation capacitor Cosc is grounded and the other end is connected to the oscillation constant current source Iosc, and the sawtooth voltage Vsaw is supplied to the inverting input terminal of the PWM comparator 12 from the connection point. The oscillation constant current source Iosc connected to the power supply VDD is further connected to the drain terminal of the discharge switch Mosc. The discharge switch Mosc has its source terminal grounded together with the other end of the oscillation capacitor Cosc, its gate terminal connected to the connection point of the transistors Mp1 and Mn1 of the extension circuit 21, and is controlled to be turned on / off by the first clock signal Vck. The

  The comparator 23 is supplied with the oscillation reference voltage Vosc at its inverting input terminal. The non-inverting input terminal of the comparator 23 is connected to the oscillation constant current source Iosc together with the oscillation capacitor Cosc. Further, the comparator 23 is connected to the input side of the first delay circuit 22, and a delay output having a predetermined falling delay time Tda with respect to the output signal is supplied to the extension circuit 21 and the duty ratio limiting circuit 30. Is output as the clock signal Vckr.

  The duty ratio limiting circuit 30 includes a second delay circuit 31, a third delay circuit 32, an AND circuit 33, a charge pump circuit 34, a first voltage limiter 35, and a second voltage limiter 35. The voltage limiting circuit 36 is used. The duty ratio limiting circuit 30 clamps the output voltage Vea of the error amplifying circuit 11 below an appropriate clamp voltage Vcl based on the two clock signals Vck and Vckr input from the oscillation circuit 20.

  In the second delay circuit 31, a signal Vckr1 (second delay output) having a predetermined falling delay time Tdb is generated with respect to the second clock signal Vckr input thereto, and is charged via the inverter circuit IV3. It is output to the pump circuit 34. The third delay circuit 32 receives the first clock signal Vck via the inverter circuit IV4. The third delay circuit 32 is a circuit that generates and outputs a signal having a predetermined falling delay time Tdc with respect to the input signal. The AND circuit 33 is supplied with the output of the third delay circuit 32 as one input signal and the first clock signal Vck as the other input signal. The output signal Vck1 of the AND circuit 33 is output to the charge pump circuit 34.

  The charge pump circuit 34 includes two P-channel transistors Mp2 and Mp3, two N-channel transistors Mn3 and Mn4, a charging current source Iu, and a discharging current source Id. The charge pump circuit 34 is a circuit that increases or decreases the charge of the capacitor Cm, that is, the voltage Vcl across the capacitor Cm, according to the signal Vckr1 and the signal Vck1.

  Here, the transistors Mp2 and Mp3 are connected in series, and the source terminal of the transistor Mp2 is connected to the charging current source Iu. Similarly, the transistors Mn3 and Mn4 are connected in series with each other, and the source terminal of the transistor Mn4 is connected to the discharge current source Id. The gate terminals of the transistors Mp2 and Mn4 are connected to the AND circuit 33, and the gate terminals of the transistors Mp3 and Mn3 are connected to the inverter circuit IV3.

  The four transistors Mp2, Mp3, Mn3, and Mn4 form a series circuit between the power supply VDD and the ground by connecting the drain terminals of the transistors Mp3 and Mn3 to each other. The charge pump current Icp from the connection point of the transistors Mp3 and Mn3 (the charge current from the charge current source Iu or the discharge current sunk by the discharge current source Id. In the latter case, the direction of the current Icp is 1 is configured to charge and discharge the capacitor Cm constituting the memory capacity and to supply the clamp voltage Vcl of the first voltage limiting circuit 35. The first voltage limiting circuit 35 limits the output voltage Vea of the error amplifying circuit 11 to a clamp voltage Vcl that is a charging voltage of the capacitor Cm, and further, the second voltage limiting circuit 36 reduces the charging voltage of the capacitor Cm. By limiting, the maximum voltage value of the clamp voltage Vcl is limited to Vclmax or less.

Details of the configuration and operation of the voltage limiting circuits 35 and 36 will be described later with reference to FIG.
Next, the oscillation circuit 20 and the three delay circuits 22, 31 and 32 constituting the duty ratio limiting circuit 30 will be described.

FIG. 2 is a circuit diagram showing an example of a delay circuit in the DC-DC converter of FIG. 1, and FIG. 3 is a timing diagram showing operation waveforms of the delay circuit.
Each of the delay circuits 22, 31, and 32 (hereinafter abbreviated as 31 and 32) includes an N-channel transistor Mnr as a reset switch, a constant current source IB1 that determines a delay time, a capacitor Cdly, and a threshold voltage Vth. It has an inverter circuit IV5. The input signal Va is supplied to the gate terminal of the transistor Mnr, and the constant current source IB1 supplies a charging current for the capacitor Cdly. The capacitor Cdly is discharged when the transistor Mnr is turned on. The inverter circuit IV5 inverts the output signal Vc from H to L when the node voltage Vb exceeds the threshold voltage Vth.

  As shown in FIG. 3A, the transistor Mnr is turned off at the timing when the input signal Va falls, and the capacitor Cdly is gradually charged. Then, as shown in FIG. 5B, the voltage at the connection point between the constant current source IB1 and the capacitor Cdly increases. When the charging voltage Vb of the capacitor Cdly exceeds the threshold voltage Vth, the output signal Vc becomes L. Thereafter, when the input signal Va rises again, the transistor Mnr becomes conductive, the charging voltage Vb of the capacitor Cdly becomes 0, and the output signal Vc also returns to H without delay (FIG. 3C).

FIG. 4 is a timing chart showing operation waveforms of the third delay circuit 32.
FIG. 3A shows the first clock signal Vck output from the oscillation circuit 20. This clock signal Vck is inverted by the inverter circuit IV4 and is supplied as an input signal of the third delay circuit 32. Assuming that the fall delay time set in the delay circuit 32 is Tdc shown in FIG. 3C, the output signal falls from the delay circuit 32 with a delay of Tdc from the fall of the input signal of the delay circuit 32. Since the output signal and the clock signal Vck shown in FIG. 5A are input to the AND circuit 33, the AND circuit output Vck1 that becomes H only for the falling delay time Tdc is supplied from the AND circuit 33 to the charge pump circuit 34. Is done.

Next, the first and second voltage limiting circuits 35 and 36 will be described.
FIG. 5 is a circuit diagram showing an example of a voltage limiting circuit in the DC-DC converter of FIG.

  Here, a first voltage limiting circuit 35 configured by two P-channel transistors Mp11 and Mp12, four N-channel transistors Mn11 to Mn14, and a constant current source IB2 is shown. A constant amplifier IB2 and transistors Mp11, Mp12, Mn11, Mn12 constitute a differential amplifier, and the error voltage Vea of the error amplifier circuit 11 at the subsequent stage is clamped by the integrated voltage of the capacitor Cm input as the clamp voltage Vcl It is.

  Here, when the clamp voltage Vcl is equal to the error voltage Vea, equal current flows through the transistors Mn11 and Mn12, but no current flows through the transistor Mn13. Even when the clamp voltage Vcl is larger than the error voltage Vea, a larger amount of current is caused to flow to the transistor Mn12 than to the transistor Mn11, so that no current flows to the transistor Mn13. When the clamp voltage Vcl becomes smaller than the error voltage Vea, the differential amplifier tries to pass more current to the transistor Mn11 than the transistor Mn12. However, the transistor Mn11 and the transistor Mn12 constituting the current mirror have their current values. Therefore, the excess current of the transistor Mn11 with respect to the current of the transistor Mn12 flows to the transistor Mn13. When a current flows through the transistor Mn13, since the transistors Mn13 and Mn14 constitute a current mirror, a current amplified by a mirror ratio (which is determined to be larger) flows through the transistor Mn14. Thus, the error voltage Vea drops by the product of the current flowing through the transistor Mn14 and the output impedance of the error amplifier circuit 11, and the error voltage Vea is limited by the clamp voltage Vcl.

Note that the configuration of the voltage limiting circuit is not limited to that described above, and may be configured by another circuit system.
Next, the operation of the duty ratio limiting circuit 30 when overcurrent is detected will be described.

FIG. 6 is a timing diagram showing signal waveforms related to the operation of the duty ratio limiting circuit.
First, the case where the overcurrent of the inductor current I _L is not detected by the overcurrent detection circuit 18 will be described.

  At this time, since the overcurrent determination signal Voc is L, the transistor Mn2 of the extension circuit 21 is turned on via the inverter circuit IV1. In the oscillation circuit 20, if the second clock signal Vckr is L and the transistor Mn1 is kept on and the transistor Mp1 is kept off by the inverter circuit IV2 receiving this signal, the first clock signal Vck becomes L, and the discharge switch Mosc is turned off. Thus, the oscillation capacitor Cosc is charged with a predetermined current from the oscillation constant current source Iosc. When the comparator 23 determines that the charging voltage of the capacitor Cosc has reached the oscillation reference voltage Vosc, the output of the comparator 23 becomes H. Since this change is a rise, the second clock signal Vckr becomes H without delay without being delayed by the first delay circuit 22. The signal Vckr that has become H inverts the transistor Mn1 to the off state and the transistor Mp1 to the on state via the inverter circuit IV2, whereby the first clock signal Vck becomes H. When the first clock signal Vck becomes H, the discharge switch Mosc becomes conductive, and when the discharge switch Mosc becomes conductive, the charge of the capacitor Cosc is discharged. In this case, the output of the comparator 23 becomes L immediately after the discharge switch Mosc is turned on, but since this change falls, the first delay circuit 22 delays the fall delay time Tda and transmits it to the inverter circuit IV2. In response to this, the first clock signal Vck becomes L. With the above operation, the period during which the first clock signal Vck is H continues for the delay time Tda. By repeating such a charge / discharge operation, a sawtooth voltage Vsaw as shown in FIG. 6B is generated.

Next, a case where the overcurrent state is continuously detected by the overcurrent detection circuit 18 during the conduction period of the discharge switch Mosc in which the first clock signal Vck is H will be described.
At this time, since the overcurrent determination signal Voc remains H even after the delay time Tda ends, the H period of the first clock signal Vck is extended, thereby extending the ON state of the discharge switch Mosc. . If the overcurrent determination signal Voc is H, the transistor Mn2 to which the inverted signal is supplied via the inverter circuit IV2 is turned off. On the other hand, when the first clock signal Vck becomes H, the charge of the capacitor Cosc is discharged and the output of the comparator 23 falls to L. As described above, this fall is delayed by the delay time Tda by the delay circuit 22. And transmitted to the inverter IV2. Even if the delay time Tda ends and the second clock signal Vckr becomes L and the transistor Mn1 is turned on and the transistor Mp1 is turned off, the transistor Mn2 is turned off, so that the first clock signal Vck is turned on. Is not inverted to L, and the immediately preceding value H is maintained by the extended parasitic capacitance. Therefore, until the transistor Mn2 is turned on after the overcurrent state is canceled, the first clock signal Vck is held at H and supplied to the duty ratio limiting circuit 30 as shown in FIG.

  The PWM comparator 12 compares the sawtooth voltage Vsaw with the output voltage Vea of the error amplifier circuit 11 and outputs a pulse signal to the AND circuit 13 with a duty ratio corresponding to the output voltage Vea. Further, the output voltage Vea of the error amplifying circuit 11 is clamped to a clamp voltage Vcl or less by the first voltage limiting circuit 35 of the duty ratio limiting circuit 30. Based on this, during normal operation, the main switch S1 and the synchronous rectification switch S2 are complementarily switched with a predetermined dead time. However, when overcurrent is detected, the period during which the first clock signal Vck is H is extended as described above, and the output of the AND circuit 13 becomes L during the extension period. Therefore, during this period, the main switch S1 is turned off and the synchronous rectification switch S2 is kept on in the manner of interrupting the switching operation by the PWM comparator 12.

  As described above, during the normal operation, the time when the first clock signal Vck becomes H does not increase (that is, the OFF time of the main switch S1) does not occur, and the second delay circuit 31 is sufficient for the charge pump circuit 34. The capacitor Cm is charged with the current of the charging current source Iu only during the falling delay time Tdb set to a small value to increase the clamp voltage Vcl. On the other hand, when an overcurrent is detected, the H level period of the first clock signal Vck is extended to the falling delay time Tda or more as shown as the extension period Textd in FIG. Therefore, in the charge pump circuit 34, the capacitor Cm is discharged by the discharge current source Id during the extension period Textd, and the clamp voltage Vcl is lowered. Note that during the period in which both the signal Vck1 and the signal Vckr1 are H, the transistors Mp3 and Mn3 are simultaneously turned off, so that the charge pump current Icp does not flow. As a result, when the overcurrent is detected, the maximum value of the on-time of the main switch S1 determined by the output voltage Vea of the error amplifier circuit 11 can be reduced by reducing the clamp voltage Vcl.

Next, a method for limiting the inductor current by limiting the on-time when an overcurrent is detected will be described.
FIG. 7 is a timing chart showing an example of an operation waveform of the DC-DC converter when the maximum value Ton-max of the on-time of the main switch S1 is provided and the value is fixed.

In this case, the average current Iolim at the time of overcurrent detection is
Iolim = Iblim + Ton-max (Vin−Vout) / 2L
Can be limited. Here, Iblim is a bottom current set value set in the overcurrent detection circuit 18, and L is an inductance of the inductor L.

  Generally, when determining the maximum on-time value Ton-max, it is necessary not to affect the normal operation of the DC-DC converter. In the setting of the maximum on-time value Ton-max, a sufficiently large value is set in consideration of the on-time ratio D (= Vin / Vout) necessary for obtaining the output voltage Vout from the input power source Vin during normal operation. There is a need to. This is because the increment sufficient to compensate for the loss in the switches S1 and S2 and the inductor L of the DC-DC converter, the margin at the time of transient response, the detection error of the input power supply voltage (Vin) and the output voltage Vout, the calculation error, etc. is there. At this time, losses in external components other than the switches S1 and S2 and the inductor L also occur.

  Further, when the output voltage Vout is fed back to the control circuit configured as the integrated circuit 10 via an external voltage dividing resistor for voltage setting, or the power supply VDD of the integrated circuit 10 is supplied separately from the input power supply Vin. For example, the input power supply voltage (Vin) and the output voltage Vout cannot be detected unless a new terminal is provided. Therefore, it is necessary to set the maximum on-time value Ton-max in consideration of the maximum condition of the assumed use range.

  In the bottom current limitation of the DC-DC converter of the present invention, paying attention to the fact that the off-time extension period Textd occurs in the overcurrent state, the maximum on-time is set by the off-time extension signal set in the control circuit. The magnitude of the value Ton-max is adjusted. Therefore, it is not necessary to detect the magnitude of the input power supply voltage (Vin) or the output voltage Vout.

  The third delay circuit 32 of the duty ratio limiting circuit 30 sets the discharge time of the memory capacity (capacitor Cm) to fall of the third delay circuit 32 when the extension period of the H level of the first clock signal Vck is long. It is provided to limit the amount of change in the clamp voltage Vcl by limiting it to a delay time Tdc (strictly speaking, Tdc−Tda−Tdb) or less. In some cases, a second voltage limiting circuit that limits the clamp voltage Vcl to the clamp voltage Vdmax or less in order to reduce the time required for the clamp voltage Vcl to drop to a predetermined value after the overcurrent state occurs. 36 is provided. However, the clamp voltage Vdmax needs to be set so as not to affect the assumed normal operation.

FIG. 8 is a diagram illustrating an example of operation waveforms of the DC-DC converter in which the maximum value (Ton-max) of the on-time of the main switch S1 is variable.
When the off-time is extended due to an overcurrent state, the on-time maximum value Ton-max is reduced in the next cycle, and finally the on-time until the off-time extension period Textd becomes substantially zero. Make it smaller. However, a minute time for detecting that the overcurrent state has been eliminated remains. That is, as described above, the maximum value Ton-max is not adjusted (decreased) when the extension period Textd overlaps with the falling delay time Tdb of the second delay circuit 31, so that the overlapping time remains. become.

As a result, the frequency of the PWM signal is substantially the same as the normal operating frequency (1 / Tsw). In this case, the average current Iolim at the time of overcurrent detection is
Iolim = Iblim + Tsw · Vin (Vin−Vout) / 2Vout · L
Limited by.

  When the overcurrent state is canceled and the extension period Textd becomes 0, the capacitor Cm is charged at the falling delay time Tdb of the second delay circuit 31, and the clamp voltage Vcl of the first voltage limiting circuit 35 is set. Enlarge. As a result, the maximum on-time value Ton-max is increased, and eventually the normal state in which the on-time ratio D is controlled by the error voltage Vea from the error amplifier circuit 11 is restored.

  As described above, according to the DC-DC converter of the present invention, the extension period of the cutoff time of the main switch S1 can be appropriately controlled, so that it is not necessary to calculate the required on-time ratio D and set the limit, and the overcurrent limit There is no need to worry about the effect on the normal operation.

DESCRIPTION OF SYMBOLS 10 Integrated circuit 11 Error amplifier circuit 12 PWM comparator 13, 33 AND circuit 14 DT (dead time) generation circuit 15 Level shifter 16, 17 Driver circuit 18 Overcurrent detection circuit 20 Oscillation circuit 21 Extension circuit 22 First delay circuit 23 Comparator 30 Duty ratio limiting circuit 31 Second delay circuit 32 Third delay circuit 34 Charge pump circuit 35 First voltage limiting circuit 36 Second voltage limiting circuit Cm Memory capacity Cosc Oscillation capacitor Cout Output capacitor D On-time ratio L Inductor or its inductance I1, I2 Average current (value)
Iblim bottom current setting value Icp charge pump current Id discharge current source I _L inductor current Iolim average current (value) when overcurrent is detected
Iosc constant current source for oscillation Iout supply current (output current)
Iu Current source for charging IV1 to IV4 Inverter circuit Mosc Discharge switch R1, R2 Split resistor R Load or its load resistance value S1 Main switch S2 Synchronous rectifier switch Ton-max Maximum value of on-time of main switch S1 Tsw Operation cycle Tda , Tdb, Tdc Fall delay time Textd Extension period Vcl Clamp voltage Vck First clock signal Vck1 AND circuit output Vckr Second clock signal Vckr1 Second delay output Vd Negative feedback signal Vdmax Clamp voltage Vea Error voltage Vin Input power supply Vout Output voltage Voc Overcurrent determination signal Vosc Oscillation reference voltage Vref First reference voltage Vsaw sawtooth voltage Vsw Switching terminal voltage

Claims (3)

A main switch connected to the high potential side of the input power supply;
A synchronous rectification switch connected in series with the main switch on the low potential side of the input power supply;
A filter circuit including an inductor and a smoothing capacitor connected to a connection point between the main switch and the synchronous rectification switch, and supplying a smoothed output voltage to a load circuit;
A control circuit that alternately turns on and off the main switch and the synchronous rectification switch by pulse width modulation (PWM) control;
With
The control circuit sets the cutoff time of the main switch in preference to the pulse width modulation control in the control circuit while the inductor current flowing through the inductor during the conduction control of the synchronous rectification switch exceeds the first set value. has an extension circuit for extending and a duty ratio limiting circuit for setting the predetermined upper limit value (Ton-max) for the conduction time of the main switch,
The duty ratio limiting circuit includes a voltage limiting circuit that changes the upper limit value (Ton-max) in accordance with an extension period (Textd) of the shutoff time of the main switch, and the extension period is a second set value ( The DC-DC converter characterized in that the upper limit value (Ton-max) is decreased when longer than Tdb) and the upper limit value (Ton-max) is increased when the extension period does not occur. .   The control circuit includes an overcurrent detection circuit that detects whether an inductor current flowing through the inductor exceeds the first set value by comparing a voltage drop at the synchronous rectification switch with a bottom reference voltage. The DC-DC converter according to claim 1.   2. The DC-DC converter according to claim 1, wherein the control circuit includes a dead time generation circuit that sets a dead time for performing cutoff control of the main switch and the synchronous rectification switch at the same time.

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