JP5287624B2 - Image processing circuit and image encoding apparatus - Google Patents

Description

  The present invention relates to an image processing circuit and an image encoding device that perform motion compensation of moving image data.

  An image encoding technique for compressing and encoding data based on a difference value between and within frames of moving image data is used in various fields. A frame is a single still image constituting moving image data. One frame is divided into a plurality of macroblocks. All processing is executed in units of macroblocks.

  By reducing the data size of the moving image data by compressing and encoding the image, high-quality moving image data can be stored in a longer time on a storage medium having a limited storage capacity. An image encoding device having a function of moving image compression is also mounted on a portable device such as a handy camera. As an image encoding technique for compressing and encoding a data size based on a difference value between frames and within a frame, H.264 is used. H.264 and MPEG (Moving Picture Experts Group).

  H. H.264 performs inter-frame prediction processing, which is compression processing based on a difference value between frames, in order to realize high-precision compression coding. In the inter-frame prediction process, a motion vector, which is the amount of movement of the macro block, is detected by comparing the luminance of each macro block between frames. In order to improve the accuracy in the inter-frame prediction process when detecting the motion vector, the motion detection of the encoding target image is performed by using the fractional luminance reference image virtually obtained by interpolation from the integer precision luminance reference image. Done.

  Based on the motion vector detected by the motion detection, interpolation pixels of luminance and color difference are generated from the reference image frame by interpolation processing. Generating interpolated pixels of luminance and color difference from a plurality of luminance or color difference reference pixels in the reference image frame is called motion compensation processing. The color difference interpolation calculation will be described below.

  Color difference interpolation pixels are generated from four reference pixels close to the detected motion vector coordinates. Assuming that the reference pixels for obtaining the interpolation pixel are A, B, C, and D, the color difference data of the interpolation pixel is {(8−dx) × (8−dy) × A + dx × (8−dy) × B + (8 -Dx) * dy * C + dx * dy * D + 32} >> 6. Here, ‘>>’ indicates a bit shift operation to the right. Dx and dy are coefficients called weighting coefficients. Interpolated pixel operations involve many multiplications. Since the circuit scale of the multiplication unit for performing multiplication is large, the circuit scale of the arithmetic circuit for calculating the interpolation pixel increases as the number of multiplications increases.

  The following patent documents and non-patent documents disclose techniques related to an image encoding device.

Japanese Patent Laid-Open No. 04-035385 Japanese Patent Laid-Open No. 06-204888

Junya Tsunono et al. H.264 / AVC textbook, Impress Corporation, 2006

  An object of an embodiment of the present invention is to provide an image processing circuit having a small mounting area by reviewing an arithmetic expression for interpolation calculation and reducing an operation that increases a circuit scale.

  In order to solve the above problem, an image processing circuit includes: a first constant calculated from pixel values of a plurality of pixels in a row direction among a plurality of pixels arranged in a matrix surrounding the interpolation pixel; and the interpolation pixel A first calculation unit for obtaining a second constant calculated from the pixel values of the plurality of pixels on the column direction surrounding the interpolation pixel and a third constant calculated from the pixel values of the plurality of pixels surrounding the interpolation pixel; A third weighting is calculated by calculating a first weighting coefficient determined from the position of the interpolation pixel for the plurality of pixels in the row direction and a second weighting coefficient determined from the position of the interpolation pixel for the plurality of pixels in the column direction. A second calculation unit for obtaining a coefficient; a third calculation unit for calculating a pixel value change amount per first weighting coefficient according to the first constant; and a second calculation unit per second weighting coefficient according to the second constant. A fourth calculation unit for calculating the pixel value change amount of And calculating the pixel value of the interpolated pixel based on the calculation results of the third, fourth, and fifth calculation units, and the fifth calculation unit that calculates the pixel value change amount per the third weighting coefficient. A sixth arithmetic unit.

  According to the embodiment, it is possible to provide an image processing circuit with a small mounting area by reducing the computation that increases the circuit scale.

It is a block diagram of an image coding apparatus. It is an image figure of a reference pixel and an interpolation pixel. It is a detailed block diagram of a motion compensation part. It is a block diagram of the multiplication part in a pixel calculating part. It is a comparison table of the number of gates by a prior art and the number of gates by a present Example.

  Hereinafter, this embodiment will be described. In addition, the combination of the structure in each embodiment is also contained in embodiment of this invention.

  FIG. 1 is a block diagram showing an example of the configuration of an image encoding device 1 according to the present embodiment. The image encoding device 1 compresses and encodes the input moving image data. The image encoding device 1 includes a subtractor 5, a DCT conversion unit 3, a quantization unit 10, an inverse quantization unit 17, an inverse DCT conversion unit 7, an adder 18, an intra-frame prediction unit 11, an inter-frame prediction unit 12, a variable length. An encoding unit 13 is included. Here, DCT is a Discrete Cosine Transform, which is a process of converting a discrete signal into a frequency domain signal.

  The intra-frame prediction unit 11 generates a prediction image from the pixels 16 of the encoded adjacent block used for prediction calculation of the prediction target block, and the difference value between the generated prediction image and the input image 2 of the block before the prediction image generation is Intraframe prediction processing for obtaining the smallest prediction mode is performed. The intra-frame prediction unit 11 determines a prediction mode in which the most accurate image prediction is possible by selecting a prediction mode having the smallest difference value.

  The inter-frame prediction unit 12 generates a predicted image from the front, rear, or both of the prediction target blocks, and performs an inter-frame prediction process for obtaining a difference between the generated predicted image and the original input image 2. The inter-frame prediction unit 12 receives the input image 2 and the reference image 82 and generates a predicted image block.

  The inter-frame prediction unit 12 includes a motion detection circuit 20 and an image processing circuit 21. The motion detection circuit 20 calculates a motion vector 22 from the luminance data of the input image 2 and the reference image 82. The motion detection circuit 20 outputs weighting coefficients dx and dy to the image processing circuit 21 based on the calculated motion vector 22. Details of the weighting coefficients dx and dy will be described later.

  The image processing circuit 21 obtains pixel values of interpolation pixels from pixel values of a plurality of pixels arranged in a matrix by interpolation calculation. Based on the calculated motion vector 22 and the reference image 82, the image processing circuit 21 calculates a prediction pixel having luminance data and color difference data, which are interpolation pixels subjected to interpolation calculation, and outputs the prediction pixel to the determination unit 6. The image processing circuit 21 receives the motion vector 22 from the motion detection circuit 20 as weighting coefficients dx and dy. The image processing circuit 21 functions as a motion compensation unit that performs motion compensation from the motion vector 22.

  The determination unit 6 outputs an image with a small prediction error as the prediction image 8 among the prediction pixels output by the inter-frame prediction unit 12 and the intra-frame prediction unit 11.

  The differentiator 5 calculates the difference between the input image 2 and the prediction image 8 that is the prediction result, and outputs the difference value as a prediction error 80. Here, the predicted image 8 is an image generated based on the macroblock of the adjacent frame or the adjacent macroblock of the same frame in the inter-frame prediction process or the intra-frame prediction process. The image encoding device 1 encodes and outputs the difference between the predicted image 8 generated by each prediction process and the input image 2 before the prediction process. The smaller the difference, the higher the image compression rate.

  The DCT transform unit 3 transforms the prediction error 80 into the frequency domain by discrete cosine transform. The quantization unit 10 performs a process of rounding a result obtained by dividing the converted DCT coefficient value by the quantization step to an integer value.

  The variable length encoding unit 13 expresses information with high appearance frequency with a short code among DCT coefficient values rounded to an integer value, and expresses information with low appearance frequency with a long code, so that the number of output bits as a whole Is performed, and encoded data 19 is output.

  The inverse quantization unit 17 inversely quantizes the prediction error quantized by the quantization unit 10. The inversely quantized prediction error is inversely transformed by the inverse DCT transform unit 7 and becomes a prediction error 81 before being transformed into a DCT coefficient value.

  The adding unit 18 adds the prediction image 8 generated by the intra-frame prediction unit 11 or the inter-frame prediction unit 12 and the prediction error 81, and outputs an image 16. The image 16 is input to the filter unit 9. The filter unit 9 is also called a deblocking filter, and reduces block distortion of the image 16. The filter unit 9 outputs the image after the block distortion processing as a restored image 15. The restored image 15 is used as a reference image 82 for inter-frame prediction processing by the inter-frame prediction unit 12.

  When the input image 2 is input, the inter-frame prediction unit 12 executes an inter-frame prediction process, and the intra-frame prediction unit 11 executes an intra-frame prediction process. The determination unit 6 outputs the predicted image 8 having the smallest difference value from the input image 2 among the inter-frame prediction processing result and the intra-frame prediction processing result.

The difference unit 5 calculates the difference between the generated predicted image 8 and the input image 2 and outputs a prediction error 80 to the DCT conversion unit 3. The prediction error 80 is converted by the DCT conversion unit 3 and quantized by the quantization unit 10. The quantized predicted image 8 is encoded by the variable length encoding unit 13 and output as encoded data 19.
The quantization unit 10 outputs the quantized prediction error to the variable length coding unit 13 and also outputs it to the inverse quantization unit 17. The prediction error inversely quantized by the inverse quantization unit 17 is converted from the frequency domain to the time domain by the inverse DCT transform unit 7. The adder 18 adds the prediction error converted to the time domain and the predicted image 8 output from the determination unit 6 to decode and generate the image 16 before the prediction process.

  With the above operation, the image encoding device 1 can compress the moving image by the inter-frame prediction process and the intra-frame prediction process.

  FIG. 2 is an image diagram of the reference pixels A, B, C, D, E, and F and the interpolation pixels 30 and 31. Reference pixels A, B, C, D, E, and F are part of the color difference pixels of the reference image frame. In this embodiment, the interpolation pixels 30 and 31 are color difference data. The interpolation pixel 30 is generated by linearly interpolating adjacent reference pixels A, B, C, and D with 1/8 pixel accuracy and weighting. The interpolation pixel 31 is generated by linearly interpolating adjacent reference pixels B, D, E, and F with 1/8 pixel accuracy. H. In the H.264 standard, reference pixels A, B, C, D, E, and F are integer color difference pixel signals. The 1/8 pixel accuracy indicates that the interpolation pixels 30 and 31 can be interpolated with a distance obtained by dividing the reference pixels A and B and the reference pixels A and C into eight as a minimum unit. In this embodiment, the number of divisions between reference pixels is 8. However, if the number of divisions is a multiplier of 2, the image processing circuit can achieve a mounting area reduction effect equivalent to that of the present invention. Since the calculation method of the interpolation pixel 30 and the interpolation pixel 31 is the same, only the calculation method of the interpolation pixel 30 will be described below, and the description of the interpolation pixel 31 will be omitted.

  In FIG. 2, the coordinates of the interpolation pixel 30 are defined with reference to the reference pixel A. The interpolation pixel 30 is located at a distance of dx in the direction of the reference pixel B and dy in the direction of the reference pixel C with respect to the reference pixel A. Here, dx and dy are integers from 0 to 7 and are called weighting coefficients. The weighting coefficients dx and dy are output from the motion detection circuit 20 to the image processing circuit 21 based on the motion vector calculated by the motion detection circuit 20.

  The position of the interpolation pixel based on dx and dy is a position virtually set for weighting the reference pixel, and is different from the position where the interpolation pixel is displayed on the actual screen. The weighting coefficient dx in the row direction is determined from the positional relationship between the reference pixels A and B and the interpolation pixel 30 in the row direction. The weighting coefficient dy in the column direction is determined from the positional relationship between the reference pixels A and C and the interpolation pixel 30 in the column direction.

  In the condition of FIG. 2, the color difference data of the interpolation pixel 30 is: interpolation pixel 30 = {(8−dx) × (8−dy) × A + dx × (8−dy) × B + (8−dx) × dy × C + dx × It is calculated as dy × D + 32} >> 6. Here, ‘>>’ indicates a right bit shift operation, and ‘>> 6’ indicates a 6 bit right shift operation.

  When the arithmetic expression of the interpolation pixel 30 is reconsidered so that the number of multiplications becomes smaller, the interpolation pixel 30 = {64 × A−8 × dx × (AB) −8 × dy × (AC) + dx × dy × (A + D-B-C) +32} >> 6. As a result, multiplications other than the multiplication part of ‘dx × dy’ and ‘(A + D−B−C)’ can be performed by the multiplication unit and the shift operation unit. In addition, the number of multiplications with the weighting coefficients dx, dy and the reference pixels A, B, C, D matches 8 times before the equation is modified, whereas the number of multiplications is 4 after the equation is modified. . A multiplier that performs multiplication has a large circuit scale. By modifying the formula, the number of multiplications between the weighting coefficients dx and dy can be reduced, and an image processing circuit with a smaller mounting area can be realized.

  Although the present embodiment uses the reference pixel A as a reference, the interpolation pixel 30 can be obtained by the same calculation using the reference pixels B, C, and D as a reference.

  FIG. 3 is a detailed block diagram of the image processing circuit 21. The image processing circuit 21 includes a multiplication unit 41 and two pixel calculation units 54 and 55. In this embodiment, although there are two pixel calculation units, a plurality of equivalent circuits may be prepared so that a plurality of interpolation pixels can be calculated simultaneously.

  The multiplication unit 41 functions as a calculation unit that generates a new weighting coefficient “dx × dy” based on the weighting coefficients dx and dy received from the motion detection circuit 20. The multiplier 41 multiplies the weighting coefficient dx and the weighting coefficient dy and outputs a weighting coefficient 'dx × dy'. The weighting coefficients dx and dy are integers.

  The pixel calculation unit 54 inputs the reference pixels A, B, C, and D, the weighting coefficients dx, dy, and “dx × dy”, and outputs the interpolation pixel 30. The pixel calculation unit 55 inputs the reference pixels B, D, E, and F, the weighting coefficients dx, dy, and “dx × dy”, and outputs the interpolation pixel 31. Each pixel calculation unit 54, 55 has calculation units 93, 94, 95. Since the pixel calculation units 54 and 55 have the same configuration, only the pixel calculation unit 54 will be described in detail below, and description of the pixel calculation unit 55 will be omitted.

  The calculation unit 93 obtains the number by which the weighting coefficient dx is multiplied, the number by which the weighting coefficient dy is multiplied, and the number by which the weighting coefficient ‘dx × dy’ is multiplied by subtraction from the pixel value of the reference pixel. The calculation unit 93 includes subtraction units 42, 43, 44 and 45.

  The subtracting unit 42 subtracts the reference pixel B in the row direction of the reference pixel A from the reference pixel A, and outputs a constant ‘A−B’. The subtracting unit 43 subtracts the reference pixel C in the column direction of the reference pixel A from the reference pixel A, and outputs a constant ‘A−C’. The subtracting unit 44 subtracts the reference pixel D in the row direction of the reference pixel C from the reference pixel C, and outputs a constant 'C-D'. The subtracting unit 45 subtracts the constant “C−D” from the constant “A−B”, thereby obtaining the constant “A + D−B−C” from the reference pixels A, B, C, and D used for the interpolation calculation of the interpolation pixel 30. Calculate. Since each of the reference pixels A, B, C, and D has an integer value, the addition / subtraction result also has an integer value.

  The arithmetic unit 94 multiplies the weighting coefficient dx and the constant “A−B”, multiplies the weighting coefficient dy and the constant “A−C”, and multiplies the weighting coefficient “dx × dy” and the constant “A + DBC”. To do. The calculation unit 94 includes multiplication units 41, 46, 47 and 48.

  The multiplication unit 46 functions as a calculation unit that calculates the pixel change amount per weighting coefficient dx according to the constant “A−B”. The multiplier 46 multiplies the weighting coefficient dx and the constant “A−B” and outputs “dx × (A−B)”. The multiplication unit 47 functions as a calculation unit that calculates a pixel change amount per weighting coefficient dy according to the constant “A−C”. The multiplication unit 47 multiplies the weighting coefficient dy and the constant “A−C” and outputs “dy × (A−C)”. The multiplication unit 46 functions as a calculation unit that calculates a pixel change amount per weighting coefficient “dx × dy” according to the constant “A + D−B−C”. The multiplier 48 multiplies the weighting coefficient ‘dx × dy’ and the constant ‘A + D−B−C’ and outputs ‘dx × dy × (A + D−B−C)’.

  The calculation unit 95 calculates the interpolation pixel 30 based on the calculation result of the calculation unit 94. The calculation unit 95 includes shift calculation units 49, 50, 51, 53 and an addition / subtraction unit 52.

  The shift calculation unit 49 shifts the reference pixel A 6 bits to the left, and outputs “64 × A” as the shift calculation result. The shift calculation unit 50 shifts ‘dx × (A−B)’ to the left by 3 bits, and outputs ‘8 × dx × (A−B)’, which is a shift calculation result. The shift calculation unit 51 shifts ‘dy × (A−C)’ to the left by 3 bits, and outputs ‘8 × dy × (A−C)’ as the shift calculation result.

  The addition / subtraction unit 52 subtracts the addition result of the output of the shift calculation unit 50 and the output of the shift calculation unit 51 from the addition result of the output of the shift calculation unit 49, the output of the multiplication unit 48, and the constant '32', and the addition / subtraction As a result, “64 × A−8 × dx × (A−B) −8 × dy × (A−C) + dx × dy × (A + D−B−C) +32” is output.

  The shift calculation unit 53 shifts the output of the addition / subtraction unit 52 to the right by 6 bits, and the result of the shift calculation is' {64 × A−8 × dx × (AB) −8 × dy × (AC) + dx × dy × (A + D−B−C) +32} >> 6 ′ is output as the interpolation pixel 30.

  As described above, the interpolation pixel 30 can be calculated with fewer multiplication units by configuring the circuit with the modified arithmetic expression. Furthermore, the mounting area of the image processing circuit can be further reduced by using a multiplier described later.

  The weighting coefficients dx and dy are integers from 0 to 7. Therefore, the multiplication unit that performs multiplication with the weighting coefficients dx and dy can be realized by a combination of an adder and a shift calculator without using a multiplier having a large circuit scale. In the motion compensation calculation of the color difference data, the interpolation pixel is positioned with respect to the reference pixel with the length obtained by dividing the interval between the reference pixels by “8” which is a multiplier of 2 as a minimum unit. Therefore, the weighting coefficient is a multiplier of 2 in the interpolation pixel weighting calculation. Multiplication with a multiplier of 2 can be realized by a shift operation unit that performs a bit shift operation.

  FIG. 4 is a detailed block diagram of the multiplication unit 46. 4A shows a block diagram of the multiplication unit 46, and FIG. 4B shows a control table 71 in the control unit 60 of the multiplication unit 46.

  The multiplication unit 46 includes a control unit 60, shift circuits 96 and 97, and an addition / subtraction unit 67. The shift circuits 96 and 97 divide the integer ‘dx’ into two 2 multipliers, and bit-shift the other integer ‘A−B’ according to the exponents of the two divided 2 multipliers.

  The control unit 60 sets the number of shifts of the shift circuits 96 and 97 according to the respective exponents after dividing the integer 'dx' into two 2's multipliers, and performs addition / subtraction to combine the shift circuit 96 and 97 shift operation results. The unit 67 is controlled. The control unit 60 stores a control table 71 shown in FIG. The control unit 60 outputs control signals 68, 69, and 70 to the multiplexers 64 and 66 and the addition / subtraction unit 67 according to the integer value of the input signal ‘dx’.

  The shift circuit 96 includes shift calculation units 61, 62, 63 and a multiplexer 64. The shift circuit 97 includes a shift calculation unit 65 and a multiplexer 66.

  ‘A−B’ input to the multiplication unit 46 is input to the multiplexers 64 and 66 and the shift calculation units 61, 62, 63 and 65. The shift calculation units 61 and 65 shift the input 'A-B' to the left by 1 bit and output it. The shift operation unit 62 shifts the inputted 'A-B' by 2 bits to the left and outputs it. The shift calculation unit 63 shifts the inputted 'A-B' to the left by 3 bits and outputs it.

  The multiplexer 64 selects and outputs one input signal according to the value of the control signal 68 among the signals input to the input terminals 0 to 4. The control signal 68 is, for example, a 3-bit signal that can designate any of the five input terminals. The multiplexer 66 selects and outputs one input signal according to the value of the control signal 69 among the signals input from the input terminals 0 to 2. The control signal 69 is, for example, a 2-bit signal that can designate any of the three input terminals.

  In order to make the number of bit shifts variable, in this embodiment, the outputs of a plurality of shift operation units are selected by switching with a multiplexer, but it can also be realized by a shift operation unit that makes the number of bit shifts variable by a control signal. .

  The addition / subtraction unit 67 adds / subtracts the plurality of shifted reference pixels output from the plurality of multiplexers 64 and 66 according to the multiplication value of the weighting coefficient ‘dx’ and the reference pixel. The adder / subtractor 67 adds or subtracts the values output from the multiplexers 64 and 66 according to the value of the control signal 70, and outputs the result.

  4B is a control table 71 stored in the control unit 60. FIG. In the control table 71, a column 72 is a value of “dx” input to the multiplication unit 46.

  A column 73 is a value of the control signal 68 output from the control unit 60 according to the value of “dx”. The multiplexer 64 selects and outputs a signal input from the input terminal corresponding to the value of the control signal 68.

  A column 74 is a value of the control signal 69 output from the control unit 60 in accordance with the value of “dx”. The multiplexer 66 selects and outputs a signal input from the input terminal corresponding to the value of the control signal 69.

  A column 75 is a value of the control signal 70 output from the control unit 60 according to the value of “dx”. The adder / subtractor 67 adds the output value of the multiplexer 66 to the output value of the multiplexer 64 when the control signal is “0”, and subtracts the output value of the multiplexer 66 from the output value of the multiplexer 64 when the control signal is “1”. To do.

  A column 76 is a value output from the adder / subtractor 67 according to the value of “dx”. The value output from the adder / subtractor 67 corresponds to the multiplied value of ‘dx’ and ‘A−B’ input to the multiplier 46.

  For example, when ‘dx’ is ‘0’, the control unit 60 outputs ‘0’ as the control signal 68, outputs ‘0’ as the control signal 69, and outputs ‘0’ as the control signal 70. As a result, the multiplexer 64 outputs the input value “0” at the input terminal 0, the multiplexer 66 outputs the input value “0” at the input terminal 0, and the adder / subtractor 67 adds the output values from the multiplexers 64 and 66. '0' is output.

  When ‘dx’ is ‘1’, the control unit 60 outputs ‘1’ as the control signal 68, outputs ‘0’ as the control signal 69, and outputs ‘0’ as the control signal 70. As a result, the multiplexer 64 outputs the input value “A−B” of the input terminal 1, the multiplexer 66 outputs the input value “0” of the input terminal 0, and the adder / subtractor 67 adds the output values from the multiplexers 64 and 66. The result “A-B” is output.

  When ‘dx’ is ‘2’, the control unit 60 outputs ‘2’ as the control signal 68, outputs ‘0’ as the control signal 69, and outputs ‘0’ as the control signal 70. As a result, the multiplexer 64 outputs the input value “(A−B) << 1” of the input terminal 2, the multiplexer 66 outputs the input value “0” of the input terminal 0, and the adder / subtractor 67 receives from the multiplexers 64 and 66. '(AB) << 1' is output as a result of adding the output values of.

  When ‘dx’ is ‘3’, the control unit 60 outputs ‘2’ as the control signal 68, outputs ‘1’ as the control signal 69, and outputs ‘0’ as the control signal 70. As a result, the multiplexer 64 outputs the input value “(A−B) << 1” of the input terminal 2, the multiplexer 66 outputs the input value “A−B” of the input terminal 1, and the adder / subtractor 67 includes the multiplexer 64, '((A−B) << 1) + (A−B)', which is the result of adding the output values from 66, is output.

  When ‘dx’ is ‘4’, the control unit 60 outputs ‘3’ as the control signal 68, outputs ‘0’ as the control signal 69, and outputs ‘0’ as the control signal 70. As a result, the multiplexer 64 outputs the input value “(A−B) << 2” of the input terminal 3, the multiplexer 66 outputs the input value “0” of the input terminal 0, and the adder / subtractor 67 receives from the multiplexers 64 and 66. '(AB) << 2' is output as a result of adding the output values of.

  When ‘dx’ is ‘5’, the control unit 60 outputs ‘3’ as the control signal 68, outputs ‘1’ as the control signal 69, and outputs ‘0’ as the control signal 70. As a result, the multiplexer 64 outputs the input value “(A−B) << 2” of the input terminal 3, the multiplexer 66 outputs the input value “A−B” of the input terminal 1, and the adder / subtractor 67 includes the multiplexer 64, '((A−B) << 2) + (A−B)', which is the result of adding the output values from 66, is output.

  When ‘dx’ is ‘6’, the control unit 60 outputs ‘3’ as the control signal 68, ‘2’ as the control signal 69, and ‘0’ as the control signal 70. Thereby, the multiplexer 64 outputs the input value '(AB) << 2' of the input terminal 3, the multiplexer 66 outputs the input value '(AB) << 1' of the input terminal 2, and the addition / subtraction unit 67 outputs “((A−B) << 2) + ((A−B) << 1)”, which is the result of adding the output values from the multiplexers 64 and 66.

  When ‘dx’ is ‘7’, the control unit 60 outputs ‘4’ as the control signal 68, outputs ‘1’ as the control signal 69, and outputs ‘1’ as the control signal 70. As a result, the multiplexer 64 outputs the input value “(A−B) << 3” of the input terminal 4, the multiplexer 66 outputs the input value “A−B” of the input terminal 1, and the adder / subtractor 67 '((A−B) << 3) − (A−B)', which is a result of subtracting the output value of the multiplexer 66 from the output, is output.

  As described above, the multiplication unit 46 can be implemented by a combination of the shift calculation unit and the addition / subtraction unit.

  Similarly to the multiplication unit 46, the multiplication unit 41 can be replaced with a combination of addition / subtraction and shift operation as shown in FIG. More specifically, dx × dy can be calculated by replacing “A-B” in FIG. 4 with “dy”.

  FIG. 5 is a comparison table of the number of gates according to the prior art and the number of gates according to the present embodiment. When the mounting area of one gate is the same, the mounting area increases as the number of gates increases. In FIG. 5, row 90 is a comparison of the number of gates per multiplication unit, and row 91 is a comparison of the number of gates in the image processing circuit.

  As shown in FIG. 5, the multiplication of the 8-bit pixel is realized by the multiplication unit according to this embodiment, whereby the number of gates can be reduced by 64% compared to the case of using the conventional 8-bit multiplier. Also, the mounting area of the entire image processing circuit can be reduced by 35%.

DESCRIPTION OF SYMBOLS 1 Image coding apparatus 2 Input image 11 Intra-frame prediction part 12 Inter-frame prediction part 20 Motion detection circuit 21 Image processing circuit 22 Motion vector 30 Interpolation pixel 41, 46, 47, 48 Multiplication part 49, 50, 51, 53 Shift calculation Units 61, 62, 63, 65 Shift calculation unit 60 Control unit 64, 66 Multiplexer 67 Addition / subtraction unit

Claims (3)

A first constant calculated from pixel values of a plurality of pixels in the row direction among a plurality of pixels arranged in a matrix surrounding the interpolation pixel, and a plurality of pixels in the column direction surrounding the interpolation pixel A first calculation unit for obtaining a second constant calculated from a value and a third constant calculated from pixel values of the plurality of pixels surrounding the interpolation pixel;
A third weighting is calculated by calculating a first weighting coefficient determined from the position of the interpolation pixel for the plurality of pixels in the row direction and a second weighting coefficient determined from the position of the interpolation pixel for the plurality of pixels in the column direction. A second calculation unit for obtaining a coefficient;
A third calculation unit for calculating a pixel value change amount per the first weighting coefficient according to the first constant;
A fourth calculation unit for calculating a pixel value change amount per the second weighting coefficient according to the second constant;
A fifth calculation unit for calculating a pixel value change amount per the third weighting coefficient according to the third constant;
An image processing circuit comprising: a sixth calculation unit that calculates a pixel value of the interpolation pixel based on calculation results of the third, fourth, and fifth calculation units. The second, the third, or the fourth operation unit calculates any two of the first weighting coefficient, the second weighting coefficient, the first constant, and the second constant that are integer values. As an input value,
A first shift circuit and a second shift circuit for dividing one of the input values into a multiplier of 2 and bit-shifting the other input value according to an index of each of the two multipliers;
A control unit configured to set the number of shifts of the first shift circuit and the second shift circuit according to the exponent and to combine the shift operation results of the first shift circuit and the second shift circuit. The image processing circuit described. A first constant calculated from pixel values of a plurality of pixels in the row direction among a plurality of pixels arranged in a matrix surrounding the interpolation pixel, and a plurality of pixels in the column direction surrounding the interpolation pixel A first calculation unit for obtaining a second constant calculated from a value and a third constant calculated from pixel values of the plurality of pixels surrounding the interpolation pixel;
A first weighting coefficient determined from the position of the interpolation pixel with respect to the plurality of pixels in the row direction and a second weighting coefficient determined from the position of the interpolation pixel with respect to the plurality of pixels in the column direction are calculated and a third A second calculation unit for obtaining a weighting coefficient;
A third calculation unit for calculating a pixel value change amount per the first weighting coefficient according to the first constant;
A fourth calculation unit for calculating a pixel value change amount per the second weighting coefficient according to the second constant;
A fifth calculation unit for calculating a pixel value change amount per the third weighting coefficient according to the third constant;
A sixth calculation unit that calculates the pixel value of the interpolation pixel based on the calculation results of the third, fourth, and fifth calculation units;
A differentiator for calculating a difference value between the interpolated pixel and the original input pixel;
A discrete cosine transform unit for performing a discrete cosine transform on the difference value;
An image coding apparatus comprising: a variable-length coding unit that performs variable-length coding on the difference value subjected to the discrete cosine transform.

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