JP5295240B2 - Linear voltage regulator and method for regulating voltage using linear voltage regulator - Google Patents

Description

  The present application relates to a linear voltage regulator.

  Voltage regulators have been used to control the voltage applied to the device. The problem with voltage regulators is that they could not effectively remove both high and low frequency noise from the voltage source. In addition, the voltage regulator uses at least two relatively expensive comparator chips that use a relatively large amount of power.

  Accordingly, the inventors of the present application recognize the need for an improved voltage regulator that minimizes or eliminates the above problems or both.

  In accordance with an exemplary embodiment, a linear voltage regulator is provided. The linear voltage regulator is configured to receive a first voltage from a voltage source and remove a frequency component of the first voltage within a first frequency range to obtain an output voltage at the primary output node. A first circuit is included. The linear voltage regulator further includes a second circuit having first and second inverters electrically coupled to the primary output node of the first circuit. The second circuit is configured to receive the output voltage and remove a frequency component of the output voltage within the second frequency range. The second frequency range is greater than the first frequency range.

  According to another exemplary embodiment, a linear voltage regulator is provided. The linear voltage regulator includes a first inverter having a first input terminal and a first output terminal. The first input terminal is electrically coupled to the first output terminal. The first input terminal is further electrically coupled to a capacitor that is further coupled to electrical ground. The first inverter is further electrically coupled to the primary output node such that the first voltage on the first output terminal is less than the output voltage of the primary output node. The linear voltage regulator further includes a second inverter having a second input terminal and a second output terminal. The second input terminal is electrically coupled to the first output terminal of the first inverter. The second inverter is further electrically coupled to the primary output node and receives a first voltage from the first inverter. The linear voltage regulator further includes a p-channel field effect transistor (P-FET transistor) having a gate terminal, a drain terminal, and a source terminal. The source terminal is electrically coupled to the voltage source. The drain terminal is coupled to the primary output node. When the output voltage of the primary output node increases, the first voltage on the first output terminal of the first inverter becomes less than the output voltage on the primary output node, thereby causing the second output terminal The gate terminal is in direct or indirect electrical communication with the second output terminal of the second inverter so as to induce the second inverter to output a high logic voltage above. The P-FET transistor reduces the output voltage on the primary output node in response to a high logic voltage.

2 is a connection diagram of an electrical system having a linear voltage regulator according to an exemplary embodiment. FIG. FIG. 2 is a connection diagram of a comparator circuit used in the linear voltage regulator of FIG. 1. FIG. 2 is a connection diagram of a plurality of inverters used in the linear voltage regulator of FIG. 1. It is the schematic of the voltage signal output by the voltage source in the electric system of FIG. FIG. 2 is a schematic diagram of a voltage signal output on a primary output node of the linear voltage regulator of FIG. 1. FIG. 3 is a schematic diagram of a voltage signal output on a node in the comparator circuit of FIG. 2. FIG. 2 is a schematic diagram of a voltage signal output on a P-FET transistor used in the linear voltage regulator of FIG. 1. 3 is a flow diagram of a method for adjusting voltage using the linear voltage regulator of FIG. 1 according to another exemplary embodiment. 3 is a flow diagram of a method for adjusting voltage using the linear voltage regulator of FIG. 1 according to another exemplary embodiment.

  Referring to FIG. 1, an electrical system 10 having a linear voltage regulator 14 according to an exemplary embodiment is shown. The electrical system further includes a voltage source 12 and a load 18. The advantage of the linear voltage regulator 14 is that it can output a voltage with minimal voltage deviation for the voltage sensitive load device.

  The voltage source 12 is provided to output a voltage that may deviate from a desired voltage level. Voltage source 12 is electrically coupled to linear voltage regulator 14.

  The linear voltage regulator 14 is provided to receive a voltage from the voltage source 12 and output a voltage having a minimum voltage deviation from a desired voltage level. The linear voltage regulator 14 includes a circuit 20 and a circuit 22.

  The circuit 20 is provided to remove the frequency component of the voltage received from the voltage source 12 within the first frequency range and to obtain an output voltage at the primary voltage node 36 with reduced voltage deviation. In one exemplary embodiment, the circuit 20 is configured to remove frequency components of the voltage received from the voltage source 12 in the frequency range of 0-10 megahertz. Of course, in alternative embodiments of the circuit 20, the circuit 20 can remove frequency components in other frequency ranges. The circuit 20 includes a voltage reference device 30, an operational amplifier 32, and a P-FET transistor 34. The operational amplifier 32 has an inverting input terminal “−”, a non-inverting input terminal “+”, and an output terminal. The P-FET transistor has a gate terminal (G1), a source terminal (S1), and a drain terminal (D1). The voltage reference device 30 is electrically connected to the inverting input terminal “−” of the operational amplifier 32. The voltage reference device 30 is configured to output a desired reference voltage level. The output terminal of the operational amplifier 32 is electrically coupled to the gate terminal (G1) of the P-FET transistor 34. The non-inverting terminal “+” of the operational amplifier 32 is electrically coupled to the drain terminal (D 1) of the P-FET transistor 34 and further coupled to the primary output node 36.

  When the output voltage of voltage source 12 decreases during operation of circuit 20, the voltage received by non-inverting terminal "+" of operational amplifier 32 has a lower logic voltage compared to a higher logic voltage on inverting terminal "-". Thereby inducing the operational amplifier 32 to output a low logic voltage. In response to a low logic voltage on the gate terminal (G1) of the P-FET transistor 34, the P-FET transistor 34 increases the current flowing from the source terminal (S1) to the drain terminal (D1), thereby causing the primary The output voltage on output node 36 increases. Instead, as the output voltage of voltage source 12 increases, the voltage received by non-inverting terminal “+” of operational amplifier 32 has a higher logic voltage compared to the lower logic voltage on inverting terminal “−”, thereby. The operational amplifier 32 is induced to output a high logic voltage. In response to a high logic voltage on the gate terminal (G1) of the P-FET transistor 34, the P-FET transistor 34 reduces the current flowing from the source terminal (S1) to the drain terminal (D1), thereby causing the primary The output voltage on output node 36 decreases.

  The circuit 22 is provided to remove the frequency component of the voltage received from the voltage source 12 within the second frequency range and to obtain an output voltage with a reduced voltage deviation at the primary voltage node 36. In one exemplary embodiment, the circuit 22 is configured to remove the frequency component of the voltage received from the voltage source 12 within the frequency range of 10 megahertz to 6 gigahertz. Of course, in alternative embodiments of the circuit 22, the circuit 22 can remove frequency components in other frequency ranges. The circuit 22 includes comparator circuits 62 and 50, inverters 52, 54, 56, 58 and 60, and a P-FET transistor 62.

  Referring to FIGS. 1 and 2, the comparator circuit 50 is provided to detect a voltage deviation on the primary output node 36. Comparator circuit 50 includes inverters 80 and 82 and a capacitor 84.

  Inverter 80 includes a P-FET transistor 90, an FET transistor 92, an input terminal 94, and an output terminal 96. The P-FET transistor 90 includes a gate terminal (G3), a source terminal (S3), and a drain terminal (D3). The FET transistor 92 includes a gate terminal (G4), a source terminal (S4), and a drain terminal (D4). P-FET transistor 90 is electrically coupled to FET transistor 92. In particular, the gate terminals (G3) and (G4) are electrically coupled together at the input terminal 94. Source terminal (S 3) is electrically coupled to primary output node 36. The drain terminal (D3) is electrically coupled to the source terminal (S4) at the output terminal 96. Output terminal 96 is electrically coupled to input terminal 94. Terminal (D4) is electrically coupled to electrical ground. Capacitor 84 is electrically coupled between input terminal 94 and electrical ground. During operation, the voltage on output terminal 96 is less than the output voltage at primary output node 36. In particular, the voltage on output terminal 96 is approximately half that of primary output node 36.

  Inverter 82 includes a P-FET transistor 100, an FET transistor 102, an input terminal 104, and an output terminal 106. The P-FET transistor 100 includes a gate terminal (G5), a source terminal (S5), and a drain terminal (D5). The FET transistor 102 includes a gate terminal (G6), a source terminal (S6), and a drain terminal (D6). P-FET transistor 100 is electrically coupled to FET transistor 102. In particular, the gate terminals (G5) and (G6) are electrically coupled together at the input terminal 104. Input terminal 104 is electrically coupled to output terminal 96. Source terminal (S5) is electrically coupled to primary output node. The drain terminal (D5) is electrically coupled to the source terminal (S6) at the output terminal 106. Output terminal 106 is electrically coupled to input terminal 114. Terminal (D6) is electrically coupled to electrical ground.

  If the output voltage at the primary output node 36 increases during the operation of the comparator circuit 50, the voltage on the output terminal 96 of the inverter 80 will be less than the output voltage on the primary output node 36, thereby causing the output on the output terminal 106 to Inverter 82 is induced to output a high logic voltage. This high logic voltage is then used to induce P-FET transistor 62 to reduce the output voltage on primary output node 36 in response to the high logic voltage. Instead, as the output voltage at primary output node 36 decreases, the voltage on output terminal 96 of inverter 80 becomes greater than the output voltage on primary output node 36, thereby lowering the logic voltage on output terminal 106. Inverter 82 is induced to output. This low logic voltage is then used to induce P-FET transistor 62 to increase the output voltage on primary output node 36 in response to the low logic voltage.

  1 and 3, the chain of inverters 52, 54, 56, 58, 60 amplifies the output voltage from the comparator circuit 50 received by the gate terminal (G2) of the P-FET transistor 62. Is provided.

  Inverter 52 includes a P-FET transistor 110, an FET transistor 112, an input terminal 114, and an output terminal 116. The P-FET transistor 110 includes a gate terminal (G7), a source terminal (S7), and a drain terminal (D7). The FET transistor 112 includes a gate terminal (G8), a source terminal (S8), and a drain terminal (D8). P-FET transistor 110 is electrically coupled to FET transistor 112. In particular, the gate terminals (G7) and (G8) are electrically coupled together at the input terminal 114. The source terminal (S7) is electrically coupled to the primary output node 36. The drain terminal (D7) is electrically coupled to the source terminal (S8) at the output terminal 116. Output terminal 116 is electrically coupled to input terminal 124. Terminal (D8) is electrically coupled to electrical ground. During operation, inverter 52 receives the output voltage from comparator circuit 50 at input terminal 114 and outputs the inverted and amplified output voltage at output terminal 116.

  Inverter 54 includes a P-FET transistor 120, an FET transistor 122, an input terminal 124, and an output terminal 126. The P-FET transistor 120 includes a gate terminal (G9), a source terminal (S9), and a drain terminal (D9). The FET transistor 122 includes a gate terminal (G10), a source terminal (S10), and a drain terminal (D10). P-FET transistor 120 is electrically coupled to FET transistor 122. In particular, the gate terminals (G9) and (G10) are electrically coupled together at the input terminal 124. The source terminal (S9) is electrically coupled to the primary output node 36. The drain terminal (D9) is electrically coupled to the source terminal (S10) at the output terminal 126. Output terminal 126 is electrically coupled to input terminal 134. Terminal (D10) is electrically coupled to electrical ground. During operation, inverter 54 receives the output voltage from inverter 52 at input terminal 124 and outputs an inverted and amplified output voltage at output terminal 126.

  Inverter 56 includes a P-FET transistor 130, an FET transistor 132, an input terminal 134, and an output terminal 136. The P-FET transistor 130 includes a gate terminal (G11), a source terminal (S11), and a drain terminal (D11). The FET transistor 132 includes a gate terminal (G12), a source terminal (S12), and a drain terminal (D12). P-FET transistor 130 is electrically coupled to FET transistor 132. In particular, the gate terminals (G11) and (G12) are electrically coupled together at the input terminal 134. The source terminal (S11) is electrically coupled to the primary output node 36. The drain terminal (D11) is electrically coupled to the source terminal (S12) at the output terminal 136. Output terminal 136 is electrically coupled to input terminal 144. Terminal (D12) is electrically coupled to electrical ground. During operation, inverter 56 receives an output voltage from inverter 54 at input terminal 134 and outputs an inverted and amplified output voltage at output terminal 136.

  Inverter 58 includes a P-FET transistor 140, an FET transistor 142, an input terminal 144, and an output terminal 146. The P-FET transistor 140 includes a gate terminal (G13), a source terminal (S13), and a drain terminal (D13). The FET transistor 142 includes a gate terminal (G14), a source terminal (S14), and a drain terminal (D14). P-FET transistor 140 is electrically coupled to FET transistor 142. In particular, the gate terminals (G13) and (G14) are electrically coupled together at the input terminal 144. The source terminal (S13) is electrically coupled to the primary output node 36. The drain terminal (D13) is electrically coupled to the source terminal (S14) at the output terminal 146. Output terminal 146 is electrically coupled to input terminal 154. Terminal (D14) is electrically coupled to electrical ground. During operation, inverter 58 receives an output voltage from inverter 56 at input terminal 144 and outputs an inverted and amplified output voltage at output terminal 146.

  Inverter 60 includes a P-FET transistor 150, an FET transistor 152, an input terminal 154, and an output terminal 156. The P-FET transistor 150 includes a gate terminal (G15), a source terminal (S15), and a drain terminal (D15). The FET transistor 152 includes a gate terminal (G16), a source terminal (S16), and a drain terminal (D16). P-FET transistor 150 is electrically coupled to FET transistor 152. In particular, the gate terminals (G15) and (G16) are electrically coupled together at the input terminal 154. Source terminal (S15) is electrically coupled to primary output node. The drain terminal (D15) is electrically coupled to the source terminal (S16) at the output terminal 156. Output terminal 156 is electrically coupled to the gate terminal (G 2) of P-FET transistor 62. Terminal (D16) is electrically coupled to electrical ground. During operation, inverter 60 receives an output voltage from inverter 58 at input terminal 154 and outputs an inverted and amplified output voltage at output terminal 156.

  In an alternative embodiment, linear voltage regulator 14 can be constructed by removing inverters 52, 54, 56, 58, 60, and inverter 82 is electrically coupled directly to P-FET transistor 62. Please note that. Further, in other alternative embodiments, the number of inverters in the inverter chain for amplifying the voltage from the comparator circuit 50 is greater than the number of inverters shown in the inverter chain of FIG. May be less.

  Referring to FIG. 1, a P-FET transistor 62 is provided to remove voltage deviation at the primary output node 36. In particular, the P-FET transistor 62 is provided to remove the frequency component of the output voltage within the second frequency range. The P-FET transistor 62 includes a gate terminal (G2), a source terminal (S2), and a drain terminal (D2). Gate terminal (G 2) is electrically coupled to output terminal 156 of inverter 60. Source terminal (S 2) is electrically coupled to voltage source 12. Drain terminal (D 2) is electrically coupled to primary output node 36. Resistor 18 is electrically coupled between primary output node 36 and electrical ground. The resistor 18 corresponds to a load that receives an output voltage from the linear voltage regulator 14. In operation, when the P-FET transistor 62 receives a high logic voltage from the inverter 60 at the gate terminal (G2), in response to the high logic voltage, the P-FET transistor 62 reduces the current flowing therethrough and the primary. Reduce the output voltage on output node 36. Instead, when the P-FET transistor 62 receives a low logic voltage from the inverter 60 at the gate terminal (G2), in response to the low logic voltage, the P-FET transistor 62 increases the current flowing therethrough and the primary. Increase the output voltage on output node 36.

  An exemplary schematic diagram of the signal generated by the linear voltage regulator 14 will be briefly described with reference to FIGS. Referring to FIG. 4, the voltage curve 170 corresponds to an exemplary output voltage generated by the voltage source 12. As shown, the voltage curve 170 has a vibration shape over time. Referring to FIG. 5, voltage curve 180 corresponds to the output voltage generated by linear voltage regulator 14 at primary output node 36. As shown, voltage curve 180 is relatively constant over time as desired. Referring to FIG. 6, the voltage curve 190 corresponds to the output voltage at the output terminal 96 of the comparator 50. Referring to FIG. 7, the voltage curve 200 corresponds to the voltage received at the gate terminal (G 2) of the P-FET transistor 62 to control the operation of the P-FET transistor 62.

  A flowchart of a method for adjusting the voltage using the linear voltage regulator 14 will be described with reference to FIGS.

  In step 220, the circuit 20 of the linear voltage regulator 14 receives a first voltage from the voltage source 12. Circuit 20 has a primary output node 36.

  In step 222, the circuit 20 removes the frequency component of the first voltage within the first frequency range to obtain an output voltage at the primary output node 36.

  At step 224, the circuit 22 of the linear voltage regulator 14 causes the inverter 80 to be directly or indirectly electrically coupled to the primary output node 36 so as to remove the frequency component of the output voltage within the second frequency range. , 82. The second frequency range is greater than the first frequency range. Step 224 is implemented using steps 230-240.

  In step 230, inverter 80 outputs a second voltage on output terminal 96 that is less than the output voltage on primary output node 36 when the output voltage on primary output node 36 increases.

  In step 232, inverter 82 outputs a high logic voltage on output terminal 106 in response to the second voltage being less than the output voltage.

  At step 234, P-FET transistor 62 reduces the output voltage on primary output node 36 in response to a high logic voltage.

  In step 236, inverter 80 outputs a second voltage on output terminal 96 that is greater than the output voltage on primary output node 36 when the output voltage on primary output node 36 decreases.

  In step 238, inverter 82 outputs a low logic voltage on output terminal 106 in response to the second voltage being greater than the output voltage.

  At step 240, P-FET transistor 62 increases the output voltage on primary output node 36 in response to the low logic voltage. After step 240, the method returns to step 220.

  This linear voltage regulator provides substantial advantages over other regulators. In particular, the linear voltage regulator provides the technical effect of using a plurality of inverters to remove high frequency components of the voltage.

  Although the invention has been described with reference to an exemplary embodiment, those skilled in the art can make various modifications without departing from the scope of the invention, and equivalent elements instead of the elements. Will understand that can be used. In addition, many modifications may be made to the teachings of the invention to adapt to a particular situation without departing from its scope. Accordingly, the invention is not limited to the disclosed embodiments for carrying out the invention, but the invention is intended to include all embodiments falling within the scope of the intended claims. Moreover, the use of terms such as first, second, etc. does not indicate the order of importance; rather, terms such as first, second, etc. are used to distinguish one element from another. .

Claims (9)

A first circuit configured to receive a first voltage from a voltage source, remove a frequency component of the first voltage within a first frequency range, and obtain an output voltage at a primary output node;
A second circuit having first and second inverters electrically coupled to the primary output node of the first circuit, the second circuit receiving the output voltage, and the output within a second frequency range A second circuit configured to remove frequency components of the voltage, wherein the frequency in the second frequency range is higher than the frequency in the first frequency range;
Only including,
The first inverter has a first input terminal and a first output terminal, the first input terminal is electrically coupled to the first output terminal, and the first input terminal is electrically connected. The first inverter such that a second voltage on the first output terminal is less than the output voltage of the primary output node, further electrically coupled to a capacitor further coupled to a common ground. Is further electrically coupled to the primary output node;
The second inverter has a second input terminal and a second output terminal, and the second input terminal is electrically coupled to the first output terminal of the first inverter; Two inverters are further electrically coupled to the primary output node;
Said second circuit further comprises a P-FET transistor having a gate terminal, a drain terminal and a source terminal, said source terminal is electrically coupled to the voltage source, the drain terminal is the primary output node When electrically coupled and the output voltage of the primary output node increases, the second voltage on the first output terminal of the first inverter becomes the output on the primary output node. The second output of the second inverter so that the gate terminal induces the second inverter to output a higher logic voltage on the second output terminal. terminal and is directly or indirectly in electrical communication, the P-FET transistor to reduce the output voltage on the primary output node in response to the logic high voltage, linear voltage Seiki. When the output voltage of the primary output node decreases, the second voltage on the first output terminal of the first inverter becomes greater than the output voltage on the primary output node; To induce the second inverter to output a low logic voltage on the second output terminal, and the P-FET transistor is responsive to the low logic voltage to output the output on the primary output node. increasing the voltage, linear voltage regulator of claim 1. Further comprising at least third and fourth inverter electrically coupled in series between the second output terminal of the second inverter and said gate terminal of said P-FET transistor, according to claim 1, wherein Linear voltage regulator.   The linear voltage regulator of claim 1, wherein the first frequency range is 0 to 10 megahertz.   The linear voltage regulator of claim 1, wherein the second frequency range is 10 megahertz to 6 gigahertz. A method for regulating a voltage using a linear voltage regulator, wherein the linear voltage regulator is electrically coupled to a first circuit having a primary output node and to the primary output node. And a second circuit having first and second inverters,
Receiving a first voltage from a voltage source in the first circuit;
Removing a frequency component of the first voltage within a first frequency range using the first circuit to obtain an output voltage at the primary output node;
Removing the frequency component of the output voltage within a second frequency range using the first and second inverters of the second circuit, wherein the second frequency range is the first frequency range; A step larger than the frequency range;
Only including,
The second circuit further includes a P-FET transistor, the first inverter has a first input terminal and a first output terminal, and the first input terminal is connected to the first output terminal. Electrically coupled, the first input terminal is further electrically coupled to a capacitor further coupled to electrical ground, and the first inverter is further electrically coupled to the primary output node; The second inverter has a second input terminal and a second output terminal, and the second input terminal is electrically coupled to the first output terminal of the first inverter; Two inverters are further electrically coupled to the primary output node, the P-FET transistor has a gate terminal, a drain terminal, and a source terminal, and the source terminal is electrically coupled to the voltage source; The drain A child is electrically coupled to the primary output node, and the gate terminal is in direct or indirect electrical communication with the second output terminal of the second inverter, using the second circuit And removing the frequency component of the output voltage within the second frequency range,
Outputting a second voltage lower than the output voltage on the primary output node on the first output terminal of the first inverter when the output voltage of the primary output node increases; ,
Outputting a high logic voltage from the second inverter on the second output terminal in response to the second voltage being less than the output voltage;
Using the P-FET transistor to reduce the output voltage on the primary output node in response to the high logic voltage;
Including the method . Removing the frequency component of the output voltage within the second frequency range using the second circuit;
Outputting the second voltage greater than the output voltage on the primary output node on the first output terminal of the first inverter when the output voltage of the primary output node decreases. When,
Outputting a low logic voltage from the second inverter on the second output terminal in response to the second voltage being greater than the output voltage;
Using the P-FET transistor to increase the output voltage on the primary output node in response to the low logic voltage;
The method of claim 6 further comprising: The method of claim 6 , wherein the first frequency range is 0 to 10 megahertz. The method of claim 6 , wherein the second frequency range is from 10 megahertz to 6 gigahertz.

Images