JP5300514B2 - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve such a problem that in a heterojunction field-effect transistor formed of a nitride semiconductor, forming a cap layer of 50 nm or larger on a barrier layer without reducing a two-dimensional electron gas concentration requires silicon doping at a high concentration of about 1&times;10<SP>19</SP>cm<SP>-2</SP>, but uniform doping with the silicon of such a high concentration is difficult due to the presence of a donor unintendedly coming into the nitride semiconductor during the epitaxial growth of oxygen or nitride cavities, etc., thus making difficult to control a doping concentration through the silicon only. <P>SOLUTION: An area closer to a barrier layer 40 that is subjected to the effect of polarization occurring as a result of heterojunction formation in a cap layer 50 is doped with a plurality of donors at a total concentration as high as the concentration of a two-dimensional electron gas, the donors forming an energy level higher than the Fermi level determined by the effect of polarization in a band gap of a nitride semiconductor making up the cap layer 50. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

  The present invention relates to a heterojunction field effect transistor made of a semiconductor containing nitride.

  In a conventional heterojunction field effect transistor made of a nitride-containing semiconductor, the gate electrode is formed directly on the semiconductor surface, and the drain current is large when operated by applying a pulse voltage to the gate electrode. A phenomenon that decreases (hereinafter referred to as “current collapse”) occurs, and as a result, the output and efficiency when actually operating at a high frequency are greatly reduced compared to the output and efficiency that can be predicted from the DC characteristics. . Since this current collapse is caused by a trap level formed on the semiconductor surface, it is effective to keep the gate electrode / semiconductor interface to which the electric field is most strongly applied away from the semiconductor surface in order to suppress the current collapse. For this purpose, it is desirable to adopt a recess gate structure in which only the region for forming the gate electrode is etched and then the gate electrode is formed. However, in order to apply the recess gate structure, it is necessary to etch the etching depth of the semiconductor layer directly under the gate electrode with good controllability, and it is difficult to control only by the etching rate. As a countermeasure, for example, in the case of a heterojunction field effect transistor using an AlGaN / GaN heterostructure, a GaN cap layer having a thickness equal to the etching depth is formed on the outermost surface to realize a GaN / AlGaN / GaN structure. However, a method of selectively etching only the GaN cap layer by using a difference in etching rate between GaN and AlGaN is employed. As described above, in order to suppress current collapse, it is necessary to keep the gate electrode / semiconductor interface away from the semiconductor surface. Therefore, it is preferable that the recess depth is deeper, and thus the thickness of the GaN cap layer is also thicker. Is preferred.

In the case of a GaN-based hetero field effect transistor, the impurity level formed on the semiconductor surface is a level formed at a deep energy level that cannot be excited to the conduction band at room temperature. Since it is located at an energy level higher than the Fermi level due to the strong polarization action, it becomes a supply source, and a two-dimensional electron gas having a concentration of about 1 × 10 ¹³ cm ⁻² is generated at the heterointerface. However, if a GaN cap layer having a thickness of approximately 50 nm or more is formed on the outermost surface in order to form a deep recessed gate structure, the two-dimensional electron gas concentration is significantly reduced due to being less affected by the surface level. The access resistance between the source / gate and between the gate / drain increases, and the drain current decreases.

  In order to avoid this, in the heterojunction field-effect transistor made of a nitride semiconductor described in Non-Patent Document 1, a desired two-dimensional electron gas concentration and The same concentration of silicon is delta doped. In the region near the barrier layer of the GaN cap layer, the effect of strong polarization can be obtained in the same manner as on the surface side of the barrier layer, so the energy level of the impurity level in the band gap formed by silicon delta doping is Fermi. The level becomes higher than the level, and the impurity level can be a source of the two-dimensional electron gas. Therefore, the above problem can be solved by adopting such a structure.

IEEE ELECTRON DEVICE LETTRS, VOL.29, NO.4 APRIL. 2008, P303 J.Appl.Phys., Vol. 83, No.11, 1 1998, p5787

In the case of a heterojunction field effect transistor using an AlGaN / GaN heterostructure, a two-dimensional electron gas having a concentration of about 1 × 10 ¹³ (cm ⁻² ) is usually generated per area. If silicon having a similar concentration is doped in a region having a thickness of 5 nm, for example, it is necessary to control the silicon doping concentration to a high concentration of about 2 × 10 ¹⁹ (cm ⁻³ ). A method of doping an n-type impurity such as silicon at the most uniform and high concentration in an epitaxial layer made of a nitride semiconductor is a method of doping the impurity during epitaxial growth by MOCVD or the like. In this method, However, if silicon having a concentration of 1 × 10 ¹⁹ (cm ⁻³ ) or more is doped, there is a concern that stress in the crystal increases and, therefore, defects are generated (see Non-Patent Document 2). It is difficult to dope silicon having a concentration of × 10 ¹⁹ (cm ^-3 ) or more.

  Also, in nitride semiconductors such as GaN or AlGaN, oxygen, nitrogen vacancies, carbon, and the like are also quasi in the energy band gap of the semiconductor, although their energy levels are different from those of silicon. Form a place. Therefore, if the level formed by these donors is located at an energy higher than the Fermi level due to the effect of polarization, it can be a supply source of a two-dimensional electron gas, similar to the impurity level formed by silicon. Since these are unintentionally mixed during crystal growth and the transistor manufacturing process, a two-dimensional electron gas higher than the concentration of doped silicon is generated in this case, and the desired two-dimensional electron gas concentration is not achieved.

  The present invention has been made based on the recognition of such problems, and its main purpose is to use oxygen, nitrogen vacancies, or carbon in a heterojunction field effect transistor made of a nitride semiconductor. By using a donor that can form a level in a band gap in a nitride semiconductor other than silicon as described above (a level that generates electrons) alone or with silicon as a dopant, to form a heterojunction To obtain a desired two-dimensional electron gas concentration by forming a high-concentration doping region in a region close to the barrier layer of the cap layer that can be affected by the generated polarization and further controlling the total donor concentration is there.

The subject of the present invention is a semiconductor device having a heterojunction field effect transistor made of a nitride semiconductor , comprising a channel layer, a barrier layer formed on the channel layer, and a gate formed on the barrier layer an electrode, a source electrode and a drain electrode formed in between the gate electrode on the barrier layer, is disposed on the barrier layer in contact with the side surfaces of the drain electrode side of at least the gate electrode, and a cap layer comprising a second nitride semiconductor having a smaller band gap than the first nitride semiconductor constituting the barrier layer, two-dimensional electron in the region of the barrier layer side of the channel layer gas is formed, among the cap layer, in the region of the barrier layer side affected by the polarization generated by the formation of the heterojunction, the cap layer A dopant forming a level at an energy position higher than a Fermi level determined by the polarization effect in the band gap of the second nitride semiconductor to be formed; and the dopant includes silicon, And a dopant other than silicon.

  According to the subject matter of the present invention, a highly doped region can be formed in a region near the barrier layer of the cap layer that can be affected by polarization caused by forming a heterojunction. As a result, a heterojunction field effect transistor capable of generating a two-dimensional electron gas having a desired concentration while suppressing current collapse can be realized. Therefore, an improvement in product yield is also expected.

  Hereinafter, various embodiments of the present invention will be described in detail along with the effects and advantages thereof with reference to the accompanying drawings.

It is a longitudinal cross-sectional view which shows the structural example of the heterojunction field effect transistor which consists of a nitride semiconductor which concerns on Embodiment 1 of this invention. It is a longitudinal cross-sectional view which shows the structural example of the heterojunction field effect transistor which consists of a nitride semiconductor based on the modification of Embodiment 1 of this invention. It is a longitudinal cross-sectional view which shows the structural example of the heterojunction field effect transistor which consists of a nitride semiconductor based on the modification of Embodiment 1 of this invention. It is a longitudinal cross-sectional view which shows the structural example of the heterojunction field effect transistor which consists of a nitride semiconductor based on the modification of Embodiment 1 of this invention. It is a longitudinal cross-sectional view which shows the structural example of the heterojunction field effect transistor which consists of a nitride semiconductor based on the modification of Embodiment 1 of this invention. It is a longitudinal cross-sectional view which shows the structural example of the heterojunction field effect transistor which consists of a nitride semiconductor based on the modification of Embodiment 1 of this invention. It is a longitudinal cross-sectional view which shows the structural example of the heterojunction field effect transistor which consists of a nitride semiconductor based on the modification of Embodiment 1 of this invention. It is a longitudinal cross-sectional view which shows the structural example of the heterojunction field effect transistor which consists of a nitride semiconductor based on the modification of Embodiment 1 of this invention. It is a longitudinal cross-sectional view which shows the structural example of the heterojunction field effect transistor which consists of a nitride semiconductor based on the modification of Embodiment 1 of this invention. It is a longitudinal cross-sectional view which shows the structural example of the heterojunction field effect transistor which consists of a nitride semiconductor based on the modification of Embodiment 1 of this invention. It is a longitudinal cross-sectional view which shows the structural example of the heterojunction field effect transistor which consists of a nitride semiconductor based on the modification of Embodiment 1 of this invention. It is a longitudinal cross-sectional view which shows the structural example of the heterojunction field effect transistor which consists of a nitride semiconductor based on the modification of Embodiment 1 of this invention. It is a longitudinal cross-sectional view which shows the structural example of the heterojunction field effect transistor which consists of a nitride semiconductor based on the modification of Embodiment 1 of this invention. It is a longitudinal cross-sectional view which shows the structural example of the heterojunction field effect transistor which consists of a nitride semiconductor based on the modification of Embodiment 1 of this invention. It is a longitudinal cross-sectional view which shows the structural example of the heterojunction field effect transistor which consists of a nitride semiconductor based on the modification of Embodiment 1 of this invention. It is a longitudinal cross-sectional view which shows the structural example of the heterojunction field effect transistor which consists of a nitride semiconductor based on the modification of Embodiment 1 of this invention. It is a longitudinal cross-sectional view which shows the formation process of the semiconductor device which concerns on Embodiment 2 of this invention. It is a longitudinal cross-sectional view which shows the formation process of the semiconductor device which concerns on Embodiment 2 of this invention. It is a longitudinal cross-sectional view which shows the formation process of the semiconductor device which concerns on Embodiment 2 of this invention. It is a longitudinal cross-sectional view which shows the formation process of the semiconductor device which concerns on Embodiment 2 of this invention. It is a longitudinal cross-sectional view which shows the formation process of the semiconductor device which concerns on Embodiment 2 of this invention. It is a longitudinal cross-sectional view which shows the formation process of the semiconductor device which concerns on Embodiment 2 of this invention. It is a longitudinal cross-sectional view which shows the formation process of the semiconductor device which concerns on the modification of Embodiment 2 of this invention.

(Embodiment 1)
FIG. 1 is a longitudinal sectional view showing a structural example of a heterojunction field effect transistor made of a nitride semiconductor according to the present embodiment.

In FIG. 1, the lowermost layer is a semi-insulating SiC substrate 10, and a channel layer 30 made of GaN is disposed on the upper surface of the substrate 10 via a buffer layer 20. A barrier layer 40 made of Al _0.3 Ga _0.7 N (corresponding to the first nitride semiconductor) is disposed on the upper surface of the channel layer 30. Further, on the upper surface of the barrier layer 40, a first cap layer 50 made of GaN (corresponding to the second nitride semiconductor) having a band gap smaller than that of Al _0.3 Ga _0.7 N forming the barrier layer 40 and having a thickness of 5 nm. Is disposed. The first cap layer 50 is formed of GaN by doping silicon (impurities), oxygen (impurities), and nitrogen vacancy donors in regions affected by polarization on the barrier layer 40 side in the first cap layer 50. Levels (including impurity levels) that generate electrons and have a concentration of 2 × 10 ¹⁹ cm ^-3 formed at an energy position higher than the Fermi level determined by the polarization effect in the band gap. Have. Further, a second cap layer 60 made of non-doped GaN is disposed on the upper surface of the first cap layer 50. Here, the region 70 is an element isolation region. The regions 80 and 90 are a source electrode and a drain electrode, respectively, and the region 100 is a gate electrode. In the manufacturing process of the present device, the first cap layer 50 and the second cap layer 60 in the regions where the source electrode 80, the drain electrode 90, and the gate electrode 100 are formed are removed and do not exist.

By adopting such a structure, a donor (impurity of a high concentration of 2 × 10 ¹⁹ cm ⁻³ can be easily obtained as compared with the conventional technique in which only the silicon is used as a dopant in the cap layer as described above. Can be mixed into the first cap layer 50, thereby generating a two-dimensional electron gas having a desired concentration (1 × 10 ¹³ cm ⁻² ). In addition, this structure makes it easy to selectively remove only the first and second cap layers 50 and 60 in the region of the gate electrode 100, and the gate recess structure effective for suppressing current collapse can be controlled. It can be manufactured well.

  In the structure of FIG. 1, the case of typical conditions is described, but the same effect as described above can be obtained even under the conditions shown in the following modifications.

(Modification 1)
If the first cap layer 50 and the second cap layer 60 in FIG. 1 are formed at least in a region in contact with the side surface of the gate electrode 100 on the drain electrode 90 side, the gate electrode where the electric field is most concentrated during transistor operation. The region on the drain side of the interface between 100 and the barrier layer 40 that is the electron supply layer can be moved away from the semiconductor surface (corresponding to the surface of the second cap layer 60 in this case), so that current collapse can be suppressed.

  Accordingly, the first cap layer 50 and the second cap layer 60 in FIG. 1 do not have to be formed in all regions other than the regions of the source electrode 80, the drain electrode 90, and the gate electrode 100. Therefore, as shown in the longitudinal sectional view of FIG. 2, a partial region in the upper surface of the barrier layer 40 (the gate electrode 100 on the drain electrode 90 side) is in contact with only the side surface of the gate electrode 100 on the drain electrode 90 side. The first cap layer 50 and the second cap layer 60 only need to be disposed only on the region in contact with the lower side surface.

(Modification 2)
If a region on the barrier layer 40 side of the first cap layer 50 that is affected by polarization generated by forming a heterojunction between the channel layer 30 and the barrier layer 40 is doped with a plurality of donors, the doping is performed. The donor (including impurities such as silicon) can be a source of the two-dimensional electron gas. Accordingly, the thickness of the first cap layer 50 in FIG. 1 or FIG. 2 is not necessarily 5 nm, and may be thicker than that. However, in the first cap layer 50, the region closer to the barrier layer 40 has a stronger polarization effect. Therefore, it can be said that the thickness of the first cap layer 50 is preferably thinner.

(Modification 3)
The dopants or the like mixed to form the donor (including the impurity level) in the first cap layer 50 in FIG. 1 or FIG. 2 need not necessarily be three kinds of silicon, oxygen, and nitrogen vacancies. There is no. That is, any donor (including dopant) may be used as long as its level is formed at an energy position higher than the Fermi level determined by the polarization effect within the band gap of the nitride semiconductor constituting the first cap layer 50. If this condition is satisfied, the donor (including the dopant) may be, for example, carbon, hydrogen, or magnesium.

(Modification 4)
In the first cap layer 50 of FIG. 1 or FIG. 2, the concentration of the donor (including impurities) formed by the above-described modification 3 is not necessarily 2 × 10 ¹⁹ cm ⁻³ . It is sufficient that the concentration per area determined by the product of the film thickness of the first cap layer 50 determined by the above-described modification 2 is a value that is substantially equal to the desired two-dimensional electron gas concentration. For example, when it is desired to set the concentration per area of the two-dimensional electron gas to 1 × 10 ¹³ cm ⁻² , when the thickness of the first cap layer 50 is 1 nm, the donor (including impurities). When the concentration is 1 × 10 ²⁰ cm ⁻³ and the thickness of the first cap layer 50 is 10 nm, the concentration of the donor (including impurities) may be 1 × 10 ¹⁹ cm ⁻³ . Further, the concentration of the donor (including impurities) need not be uniform in the first cap layer 50, and as described above, a plurality of donors (including impurities) in the first cap layer 50. If the total concentration of the first cap layer 50 is approximately equal to the desired two-dimensional electron gas concentration, for example, the closer to the barrier layer 40, the higher the concentration of the donor (including impurities). The concentration of the donor (including impurities) may be distributed in the depth direction.

(Modification 5)
The second cap layer 60 shown in FIG. 1 or 2 is not necessarily a non-doped nitride semiconductor layer, and impurities may be doped in the second cap layer 60. However, the region of the second cap layer 60 away from the barrier layer 40 is less affected by polarization, and the shallower the energy level of the doped impurity, the more likely it becomes a factor of gate leakage current. The impurity concentration is preferably as low as possible.

(Modification 6)
A material having a larger band gap (for example, AlN) than the material forming these layers 30 and 40 between the channel layer 30 and the barrier layer 40 in FIG. 1 or FIG. A spacer layer 110 made of may be provided as shown in FIG. By adopting such a structure, the confinement effect of the two-dimensional electron gas generated in the region on the barrier layer 40 side in the channel layer 39 can be increased, so that the concentration of the two-dimensional electron gas is increased. Further, since the alloy scattering is also reduced, the mobility of the two-dimensional electron gas is improved, and the current of the transistor can be increased and further the output can be increased.

(Modification 7)
When the band gap sizes of the channel layer 30, the spacer layer 110, the barrier layer 40, the first cap layer 50, and the second cap layer 60 in FIG. 3 are represented as B30, B110, B40, B50, and B60. If these band gaps are in the relationship of B30 <B40 <B110, B50 <B40, B60 <B40, the heterojunction field effect transistor is operated, and the concentration and mobility of the two-dimensional electron gas by the spacer layer 110 In addition, since only the cap layer in the region of the gate electrode 100 can be selectively removed, the channel layer 30 and the first and second cap layers 50 and 60 are not necessarily made of GaN, as shown in FIG. It is not necessary that the spacer layer 110 is made of AlN and the barrier layer 40 is made of Al _0.3 Ga _0.7 N. That is, these layers only need to be composed of a compound composed of at least two elements including N among Al, Ga, and N having different compositions of the elements constituting the layer. For example, the channel layer 30, the spacer layer 110, the barrier layer 40, the first cap layer 50, and the second cap layer 60 are composed of Al _X30 Ga _{1 -X30} N, Al _X110 Ga _{1 -X110} N, l _X40 Ga _{1 -X40} N, and Al, respectively. _X50 Ga _1-X50 N, Al _X60 Ga _1-X60 N, 0 ≦ X ₃₀ <1, 0 <X ₁₁₀ <1, 0 <X ₄₀ ≦ 1, 0 ≦ X ₅₀ <1, 0 ≦ X ₆₀ < It suffices if it is made of a compound semiconductor satisfying the relationships of 1, X ₃₀ <X ₄₀ <X ₁₁₀ , X ₅₀ <X ₄₀ , X ₆₀ <X ₄₀ . Furthermore, it is not always necessary to be composed of a compound semiconductor composed of at least two elements including N among three elements of Al, Ga, and N. For example, at least two kinds including N in Al and Ga to which In is added. You may be comprised with the compound semiconductor which consists of.

  This modification can also be applied to the example of FIG. 1 or FIG.

(Modification 8)
In the structure described in the modification example 7, the channel layer 30, the spacer layer 110, the barrier layer 40, the first cap layer 50, and the second cap layer 60 are N, Al, Ga, and N. (The structure shown in FIG. 3 is an example thereof.) Since a large polarization effect occurs in the barrier layer 40, the barrier layer 40 side in the channel layer 30 is formed. It is possible to generate a high-concentration two-dimensional electron gas in the area to be opened. Therefore, this structure is advantageous for increasing the current of the transistor and further increasing the output, and can be said to be a more preferable structure.

  This modification can also be applied to the example of FIG. 1 or FIG.

(Modification 9)
In the heterojunction field effect transistor, the higher the breakdown field of the nitride semiconductor material used for the channel layer 30, the higher the breakdown voltage. In Al _X Ga _1-X N, the higher the Al composition, the larger the band gap and the higher the dielectric breakdown electric field. For this reason, in the structure of the above-described modification 5, it is preferable that Al _x30 Ga _1-x30 N used for the channel layer 30 has a higher Al composition (x is close to 1). Further, as the band gap of the nitride semiconductor material used for the barrier layer 40 is larger, the gate leakage current flowing from the gate electrode 100 to the hetero interface through the barrier layer 40 becomes less likely to flow. For this reason, Al _X40 Ga _{1 -X40} N used as the barrier layer 40 is also preferably higher in Al composition.

(Modification 10)
Each of the channel layer 30, the barrier layer 40, the spacer layer 110, the first cap layer 50, and the second cap layer 60 shown in FIG. 3 does not necessarily have a structure composed of one layer having the same composition. That is, as long as the condition of the band gap size shown in Modification 4 is satisfied, the In composition, the Al composition, and the Ga composition may be spatially changed, or a multilayer composed of several different layers. It may be a film. Further, these layers may contain impurities that are n-type or p-type in the nitride semiconductor.

    This modification can also be applied to the example of FIG. 1 or FIG.

(Modification 11)
The semi-insulating SiC substrate 10 in each of FIGS. 1 to 3 may be silicon, sapphire, GaN, AlN, or the like. For example, when GaN is used as the substrate 10, the channel layer 30 and the spacer layer 110 (only in the case of application to FIG. 3) are not necessarily provided without providing the buffer layer 20 on the substrate 10. ), A barrier layer 40, and the like. Therefore, it is not always necessary to provide the buffer layer 20 on the upper surface of the substrate 10, and the buffer layer 20 may not be provided.

(Modification 12)
The source electrode 80 and the drain electrode 90 in FIGS. 1 to 3 are not necessarily barriers as long as ohmic contact with the two-dimensional electron gas generated in the region on the barrier layer 40 side in the channel layer 30 is realized. It does not have to be in contact with the layer 40. For example, a structure in which the source electrode 80 and the drain electrode 90 are in contact with the surface of the second cap layer 60 (see FIG. 4), or a structure in which the source electrode 80 and the drain electrode 90 are in contact with the inside of the second cap layer 60 (see FIG. 5), or a structure in which the source electrode 80 and the drain electrode 90 are in contact with the inside of the barrier layer 40 (see FIG. 6).

(Modification 13)
As shown in FIGS. 7 to 10, the n-type impurity has a high concentration in at least a part of the nitride semiconductor layer below the source electrode 80 and the drain electrode 90 in FIGS. 1 to 6. A doped region 120 may be provided. By adopting such a structure, the resistance between the source / drain electrodes of the two-dimensional electron gas generated in the region on the barrier layer 40 side in the channel layer 30 can be reduced. This is advantageous for increasing the current and also for increasing the output, and can be said to be a more preferable structure.

(Modification 14)
The source electrode 80 and the drain electrode 90 in FIGS. 1 to 10 are made of metal such as Ti, Al, Nb, Hf, Zr, Sr, Ni, Ta, Au, Mo, W, Pt, or these metals. It is formed of a multilayer film that is configured.

(Modification 15)
The gate electrode 100 in each of FIGS. 1 to 10 is compared with the case where the bottom surface of the gate electrode 100 is in contact with the surface of the second cap layer 60 unless the bottom surface of the gate electrode 100 is in contact with the surface of the second cap layer 60. Therefore, the current collapse can be suppressed, so that it is not necessarily in contact with the upper surface of the barrier layer 40. For example, a structure in which the bottom surface of the gate electrode 100 is in contact with the inside of the second cap layer 60 (see FIG. 11), or a structure in which the bottom surface of the gate electrode 100 is in contact with the inside of the barrier layer 40 (see FIG. 12). There may be. However, in order to improve the controllability of the etching depth of the nitride semiconductor layer directly under the gate electrode 100, it is preferable to use a difference in rate when etching layers having different structures. A structure in which the bottom surface of the gate electrode 100 as shown in each of FIGS. 1 to 10 is in contact with the vicinity of the interface between the barrier layer 40 and the first cap layer 50 is more preferable.

(Modification 16)
The gate electrode 100 in FIGS. 1 to 12 is not necessarily required to have a quadrangular sectional shape as shown in these drawings. For example, the vertical cross section of FIG. A gate electrode 101 having a T-type structure or a Y-type structure as shown in the plan view may be used. By adopting such a structure of the gate electrode 101, the gate resistance can be reduced while maintaining an area where the gate electrode 101 is in contact with the nitride semiconductor.

  Further, as shown in FIG. 14, the shape of the gate electrode 101 may be set so that the upper portion of the gate electrode 101 is in contact with the surface of the second cap layer 60. By adopting such a structure of the gate electrode 101, the electric field concentrated on the edge portion on the drain electrode 90 side of the gate electrode 101 can be relaxed at the time of high voltage operation, and current collapse is suppressed and at the same time withstand voltage. Can be increased.

(Modification 17)
The structure of the gate electrode 101 shown in FIG. 13 is opposed to the upper surface of the second cap layer 50 in the upper part 101TP that is not in contact with the first and second cap layers 50 and 60 in the gate electrode 101. Al, Ga, Si, Hf, Ti, etc. on at least a part or the entire upper surface of the second cap layer 50 so as to fill a space SP between the surface 101TPBS to be processed and the upper surface of the second cap layer 50 Among them, a structure in which an insulating film 130 made of oxide, nitride, oxynitride, or the like of at least one kind of atom may be provided (see FIG. 15). With such a structure, the electric field concentrated on the edge portion of the gate electrode 101 on the drain electrode 90 side during high voltage operation can be relaxed, so that the current collapse can be suppressed and the breakdown voltage can be increased. I can do it.

  Further, as shown in FIG. 16, the insulating film that entirely fills the space SP only in the space SP between the upper portion 101TP of the gate electrode 101 and the upper surface of the second cap layer 50 shown in FIG. 13. 130 may be provided. In this case, since the capacitance generated between the source electrode 80 and the gate electrode 101 and between the gate electrode 101 and the drain electrode 90 can be reduced, the gain and efficiency during high-frequency operation are improved. I can do it.

(Modification 18)
1 to 16, gate electrodes 100 and 101 are made of metal such as Ti, Al, Pt, Au, Ni and Pd, silicide such as IrSi, PtSi and NiSi2, or nitride metal such as TiN and WN. Or it is comprised by the multilayer film etc. which consist of these.

(Modification 19)
There is no need to individually adopt all the structures described above, and a structure in which the respective feature points are combined may be employed.

  In the above-described first embodiment and the modifications thereof, only the minimum necessary components that operate as a transistor are described, but finally, a protective film, a wiring, a via hole, etc. Is used as a device made of a nitride semiconductor.

(Embodiment 2)
17 to 22 are longitudinal sectional views showing an example of a manufacturing process of the heterojunction field effect transistor made of the nitride semiconductor having the above-described structure shown in FIG. In FIG. 17 to FIG. 22, the same reference numerals as those in FIG. 1 to FIG.

FIG. 17: By applying an epitaxial growth method such as MOCVD method or MBE method on the substrate 10, the buffer layer 20, the channel layer 30 made of GaN, the barrier layer 40 made of Al _0.3 Ga _0.7 N, and desired two-dimensional electrons A first cap layer 50 made of GaN containing a donor (including impurities) at a concentration equivalent to the gas concentration and a second cap layer 60 made of non-doped GaN are epitaxially grown sequentially from the bottom.

  In addition, when growing the first cap layer 50, the flow rate and pressure, temperature, and time of trimethylgallium, trimethylindium, ammonia, or silane and oxygen, which are raw material gases of GaN, are adjusted. Accordingly, the concentrations of silicon, nitrogen vacancies, and oxygen forming donors doped in the first cap layer 50 can be adjusted to desired concentration values.

  Alternatively, the growth is interrupted once before the second cap layer 60 is grown, and heat treatment is performed at a high temperature of about 1000 ° C. to promote desorption of nitrogen from the GaN, so that nitrogen vacancies are formed in the first cap layer 50. Can be formed.

  Alternatively, the growth can be interrupted once before the second cap layer 60 is grown, and oxygen can be incorporated into the GaN by heat treatment in oxygen at a high temperature of about 600 ° C.

  Alternatively, the concentration of the donor (including impurities) can be set higher by dividing the growth of the first cap layer 50 into a thickness of 1 nm to 2 nm and repeating the above process several times.

  As described above, after the first cap layer 50 is formed, the second cap layer 60 is formed thereon.

  As described above, oxygen or nitrogen vacancies can be mixed as a donor in a nitride semiconductor at a temperature lower than that during epitaxial growth of 1000 ° C. or less, and oxygen or nitrogen vacancies can be relatively easily and highly concentrated. Can be doped.

  In order to control the concentration of the two-dimensional electron gas generated after the epitaxial growth, the concentration of the donor (including impurities) to be doped may be accurately controlled by the above process.

FIG. 18: The second cap layer 60 and the first cap layer 50 corresponding to the region where the source electrode 80 and the drain electrode 90 are formed by a dry etching method using Cl ₂ or the like using the resist pattern as a mask 140. Remove a portion. When the Al composition ratios of the first cap layer 50 and the barrier layer 40 are different, in addition to a chlorine-based gas such as Cl ₂ , for example, a fluorine-based gas such as oxygen or SF ₆ is used during etching. As a result, only the first cap layer 50 can be selectively etched, and the control of the etching depth is improved.

  FIG. 19: After removing the resist pattern 140, for example, a metal such as Ti, Al, Nb, Hf, Zr, Sr, Ni, Ta, Au, Mo, W, Pt, or a multilayer composed of these metals A source electrode 80 and a drain electrode 90 made of a film are deposited by vapor deposition or sputtering, and then formed by a lift-off method or the like.

  FIG. 20: An element isolation region 70 is formed in the channel layer 30, the barrier layer 40, the first cap layer 50, and the second cap layer 60 outside the region for forming the transistor, for example, using an ion implantation method or etching. To do. FIG. 20 shows a method using an ion implantation method.

FIG. 21: Using the resist pattern or the like as a mask 150, a part of the second cap layer 60 and the first cap layer 50 corresponding to the region where the gate electrode 100 is to be formed is removed by a dry etching method using Cl ₂ or the like. When the Al composition ratio between the first cap layer 50 and the barrier layer 40 is different, in addition to a chlorine-based gas such as Cl ₂ , for example, a fluorine-based gas such as oxygen or SF ₆ is used during etching. Thus, only the first cap layer 50 can be selectively etched, and the first cap layer 50 can be etched under high depth controllability.

  FIG. 22: After removing the resist pattern 150, a metal such as Ti, Al, Pt, Au, Ni, Pd, a silicide such as IrSi, PtSi, NiSi2, or a nitride metal such as TiN, WN, or A gate electrode 100 made of a multilayer film composed of these materials is deposited by vapor deposition or sputtering, and then formed by a lift-off method or the like.

  By the above method, a heterojunction field effect transistor having the structure shown in FIG. 1 can be manufactured. That is, according to the present method, it becomes easy to selectively remove only the first and second cap layers 50 and 60 in the region of the gate electrode 100, and an effective gate recess structure for suppressing current collapse is obtained. It can be manufactured with good controllability.

  In the above description, only the minimum necessary components that operate as a transistor are described, but finally, after forming a protective film, a wiring, a via hole, and the like, the nitride semiconductor is used. A device as a heterojunction field effect transistor is completed.

  In the above, typical conditions are described, but a nitride semiconductor capable of obtaining the effects of the present invention under the conditions as shown in the following modifications of the second embodiment. A heterojunction field effect transistor can be manufactured.

(Modification 1)
When desired regions are etched by changing the mask patterns 140 and 150 at the time of etching shown in FIGS. 18 and 21, the nitride semiconductor heterojunction having the structure described in FIG. 2 of the first modification of the first embodiment. A field effect transistor can be manufactured.

(Modification 2)
In FIG. 17, after the channel layer 30 is grown, the spacer layer 110 made of a material having a larger band gap than the material forming the channel layer 30 and the barrier layer 40 is formed. A nitride semiconductor heterojunction field effect transistor having a structure as shown in FIG. 3 can be manufactured.

(Modification 3)
When the channel layer 30, the barrier layer 40, the first cap layer 50, and the second cap layer 60 shown in FIG. 17 are grown, trimethylammonium, trimethylgallium, trimethylindium, ammonia, or impurities used as a nitride semiconductor source gas The channel layer 30 and the barrier layer 40 are adjusted by adjusting the flow rate, pressure, temperature, and time of the silane or oxygen serving as the source gas, and adjusting the number of growth interruptions and the heat treatment conditions performed during the growth of the first cap layer 50. By changing the first cap layer 50 and the second cap layer 60 to a desired composition, film thickness, and doping concentration, various nitride semiconductor heterojunction electric fields shown in each of the modifications 2 to 10 of the first embodiment An effect transistor can be manufactured.

(Modification 4)
When the etching shown in FIG. 18 is performed, the nitride having various structures described in the modification 12 of the first embodiment is adjusted by adjusting the etching time and the gas flow rate and setting them to a desired etching depth. A semiconductor heterojunction field effect transistor can be manufactured.

(Modification 5)
After the etching shown in FIG. 18, the implantation dose is 1 × 10 ¹³ cm ⁻² to 1 × 10 ¹⁷ cm ⁻² , and the implantation energy is used by using the mask 140 used at the time of etching as it is and using an ion implantation method or the like. By implanting ions of n-type conductivity in a nitride semiconductor, such as silicon, into a desired region under conditions of 10 keV to 1000 keV, and then performing heat treatment to activate the implanted ions Thus, nitride semiconductor heterojunction field effect transistors having various structures described in Modification 13 of Embodiment 1 can be manufactured.

(Modification 6)
When the etching shown in FIG. 21 is performed, the etching time and the gas flow rate are adjusted and set to a desired etching depth, whereby the nitride semiconductor having various structures described in the modification 15 of the first embodiment is obtained. A terror junction field effect transistor can be manufactured.

(Modification 7)
When the gate electrode 100 shown in FIG. 22 is formed, the gate electrode is deposited by a vapor deposition method or the like using a resist pattern wider than the etching region, so that it is shown in FIG. 14 in the modified example 16 of the first embodiment. A nitride semiconductor heterojunction field effect transistor having such a structure can be manufactured.

(Modification 8)
Before performing the etching shown in FIG. 21, for example, using an evaporation method or a plasma CVD method, an oxide, nitride, or oxynitride of at least one kind of atoms of Al, Ga, Si, Hf, Ti, etc. An insulating film 130 made of a material or the like is deposited (see FIG. 23), and then a gate electrode 101 is formed, whereby the field effect transistor having the structure shown in FIG. 15 in the modified example 17 of the first embodiment. Can be produced. For final use as a device, it is necessary to form a wiring after part of the source / drain electrode covered with the insulating film 130 is removed by wet etching using, for example, hydrofluoric acid.

(Modification 9)
After the gate electrode 101 is formed as in the eighth modification of the present embodiment, all of the insulating film 130 is removed by wet etching using hydrofluoric acid or the like, so that FIG. 13 of the sixteenth modification of the first embodiment is shown in FIG. A field effect transistor having the structure shown in FIG. Further, the field effect of the structure shown in FIG. 16 of the modified example 17 of the first embodiment in which the insulating film in a desired region is left by adjusting the processing conditions (time and concentration) of wet etching using hydrofluoric acid or the like. Type transistor can be manufactured.

(Modification 10)
The three steps of forming the source electrode 80 and the drain electrode 90 shown in FIGS. 18 and 19, forming the element isolation region 70 shown in FIG. 20, and forming the gate electrode 100 (101) shown in FIGS. There is no need to perform in this order, and the order of the steps may be changed. For example, the element isolation region 70 may be formed before the source electrode 80 and the drain electrode 90 are formed.

(Modification 11)
Of course, it is not necessary to individually employ all the processes described above, and it is of course possible to use a process formed by combining the processes.

(Appendix)
In the present invention, “doping a donor” is a concept excluding the case of doping only silicon as a dopant (refer to the prior art such as Non-Patent Document 1).

  While the embodiments of the present invention have been disclosed and described in detail above, the above description exemplifies aspects to which the present invention can be applied, and the present invention is not limited thereto. In other words, various modifications and variations to the described aspects can be considered without departing from the scope of the present invention.

  10 semi-insulating substrate, 20 buffer layer, 30 channel layer, 40 barrier layer, 50 first cap layer, 60 second cap layer, 70 element isolation region, 80 source electrode, 90 drain electrode, 100 gate electrode, 101 gate electrode 110 spacer layer, 120 high-concentration n-type impurity region, 130 insulating film, 140 resist mask.

Claims (3)

A semiconductor device having a heterojunction field effect transistor made of a nitride semiconductor,
A channel layer;
A barrier layer formed on the channel layer;
A gate electrode formed on the barrier layer;
A source electrode and a drain electrode formed on the barrier layer with the gate electrode interposed therebetween;
It is disposed on the barrier layer in contact with the side surfaces of the drain electrode side of at least the gate electrode, a cap made of a second nitride semiconductor having a smaller band gap than the first nitride semiconductor constituting the barrier layer Layer and <br/>
A two-dimensional electron gas is formed in a region on the barrier layer side in the channel layer,
The effect of the polarization in the band gap of the second nitride semiconductor constituting the cap layer in a region on the barrier layer side affected by the polarization generated by forming a heterojunction in the cap layer Is doped with a dopant that forms a level at an energy position higher than the Fermi level determined by
The dopant contains silicon and a dopant other than the silicon,
Semiconductor device. The semiconductor device according to claim 1,
The dopant doped in the cap layer contains at least nitrogen vacancies,
Semiconductor device. The semiconductor device according to claim 1,
The dopant doped in the cap layer contains at least oxygen.
Semiconductor device.

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