JP5307377B2 - Power amplifier - Google Patents

Description

  The present invention relates to a power amplifier using a bipolar transistor, and more particularly to a power amplifier using a microwave monolithic integrated circuit (MMIC) for a wireless communication apparatus for improving operational characteristics.

  An output stage transistor of a power amplifier integrated circuit using bipolar transistors is generally configured to operate in parallel a plurality of one transistor called a transistor unit cell (hereinafter referred to as “unit cell”). Thereby, the target output power can be achieved. The unit cells constituting the output stage transistor are arranged at equidistant intervals, and the collector, base and emitter electrodes of each unit cell are connected in common with the respective electrodes of the adjacent unit cells. ing.

For example, a GaAs heterojunction bipolar transistor (hereinafter referred to as “HBT”) having an output power of 28 dBm (= 630 mW), a power added efficiency of 39.3%, an operating frequency of 1.88 GHz, and a collector-emitter voltage Vce = 3.4 V. When designing, it has been reported that the total emitter area of the output stage transistor is about 5400 μm ² (see Non-Patent Document 1). For example, when a double emitter transistor having an emitter area per emitter of 60 μm ² and 2 emitters is used for the unit cell, the number of unit cells of the output transistor is 45.

On the other hand, the arrangement of the output stage transistors in the power amplifier has an important influence on the operating characteristics.
That is, the performance required for the linear power amplifier includes factors such as high efficiency, low distortion, and thermal stability. In order to maximize these performances from the output transistor, it is desirable that all the unit cells in the parallel operation state operate uniformly. Here, the uniform operation means that the output power waveforms of the unit cells match.

  For example, power amplifiers have higher efficiency as output power approaches saturated output, while distortion tends to increase rapidly. When each unit cell is not operating uniformly, a specific unit cell reaches a saturated output and generates distortion, while the other unit cells have low output power and low efficiency. For this reason, the overall performance of the output stage transistor is degraded as compared with the case where the parallel operation of the unit cells is uniform.

In addition, as described above, in a specific unit cell that has reached the saturation output and generates distortion, more collector current flows and the amount of generated heat is larger than other unit cells. When a temperature distribution exists between the unit cells, the GaAs HBT reduces the collector current threshold value at which current collapse, which is one of the thermal instability phenomena, occurs. Uniformity is important for thermal stability.
Since the collector current of each unit cell has a positive temperature correlation, the temperature distribution as described above is emphasized by the self-heating of each unit cell, and the uniformity of each unit cell operation is further impaired. .
Therefore, it is desirable that the heat dissipation of each unit cell is high.

  By the way, the reason why each unit cell does not operate uniformly can be the difference in load impedance and heat dissipation of each unit cell. Since the saturation output waveform of the transistor is related to the knee voltage on the Ice-Vce (collector current vs. collector voltage) static characteristic curve representing the DC characteristic of the transistor, the difference in collector resistance, which is one of the knee voltage determining factors, is also This affects the uniform operation of each unit cell.

FIG. 6 shows a configuration example of electrode arrangement in a conventional output stage transistor disclosed in, for example, Patent Document 1 and the like, and this conventional configuration will be described below with reference to FIG.
This output stage transistor is configured by connecting two transistor unit cell rows in parallel.
That is, the transistor unit cell column C LINE is formed by connecting a plurality of transistor unit cells Tr in parallel. For example, in the configuration example shown in FIG. 6, the transistor unit cell column C LINE includes five transistor unit cells Tr. It has been made.

Specifically, this output stage transistor is configured to include a collector electrode wiring 101A, an emitter electrode wiring 102A, and base electrode wirings 103A and 103B.
The collector electrode wiring 101A includes two unit cell column collector electrodes 1A and 2A provided in parallel, and collector electrodes 11A corresponding to the number of unit cells Tr described above are formed. ing. In FIG. 6, in order to simplify the drawing and facilitate understanding, the unit cell column collector electrodes 1A and 2A are denoted by reference numerals representing one of the plurality of collector electrodes, and other components. Reference numerals will be omitted.

The emitter electrode wiring 102A is formed by forming emitter electrodes 25A corresponding to the number of unit cells on two opposing side edge portions so as to correspond to the unit cell column collector electrodes 1A and 2A. The emitter electrode wiring 102A is disposed on the lower layer side of the unit cell column collector electrodes 1A and 2A so as to intersect the unit cell column collector electrodes 1A and 2A, and is grounded via the via hole 7A. Has become. In addition, also about a some emitter electrode, a code | symbol shall be attached | subjected on behalf of one of the emitter electrodes similarly to the previous collector electrode, and another code | symbol shall be abbreviate | omitted.
The base electrode wirings 103A and 103B are arranged corresponding to the unit cell column collector electrodes 1A and 2A, respectively.

An equivalent circuit of the output stage transistor in such a configuration can be expressed as shown in FIG.
That is, one cell column is provided with five transistors Tr1a to Tr5a, and the other cell column is provided with five transistors Tr1b to Tr5b with collectors connected in common. The other cell row is connected to the output terminal 5A and the output terminal 6A, and the two output terminals 5A and 6A are connected to each other so that the collectors of the cell rows are connected to each other. It has become.
Keith Nellis and Peter J. Zampardi, "A Comparision of Linear Handset Power Amplifiers in Bipolar Technologies" IEEE J. Solid-State Circuits, October 2004, vol39, No.10, PP.1746-1754 JP 2006-294901 A (page 3-4, FIG. 1)

  By the way, in the above-described conventional configuration, since the width and length of the emitter electrode wiring 102A are formed to be equal, the heat dissipation is relatively uniform. On the other hand, the collector electrode wiring 101A has a narrow and long width especially for the collector electrodes 1A and 2A for the unit cell columns, so that there is a wiring resistance component and an inductance component between the unit cells. The load impedance and collector resistance are not uniform.

  In the HBT disclosed in Patent Document 1, it is proposed to use bumps for grounding the emitter. However, in the case of a power amplifier, bump formation points are concentrated on the output stage transistors. May be biased within the integrated circuit chip. As described above, when the bump formation location is uneven in the integrated circuit chip or the bump height is non-uniform, it is difficult to stably perform many connection operations when connecting to the mounting board. Therefore, from the viewpoint of easy connection work, conventional emitter grounding using via holes is superior.

  On the other hand, in order to improve the uniformity of the operation of each unit cell while ensuring the easy connection between the integrated circuit chip and the mounting substrate, it is necessary to improve the uniformity of the load impedance and the collector resistance. Although it is conceivable to increase the width of the electrode wiring or to reduce the arrangement interval of the unit cells, this causes a decrease in heat dissipation and emphasizes the temperature distribution, so that the thermal stability is remarkably increased. The problem of lowering arises.

  The present invention has been made in view of the above circumstances, and improves the uniformity of the operation of each unit cell while maintaining the ease of connection between the integrated circuit chip and the mounting substrate and good heat dissipation. An object of the present invention is to provide a power amplifier capable of performing

In order to achieve the above object of the present invention, a power amplifier according to the present invention comprises:
A collector electrode wiring formed with a plurality of collector electrodes corresponding to the number of unit cells, which is a basic unit forming one transistor, and an emitter electrode wiring formed with a plurality of emitter electrodes corresponding to the number of unit cells; A power amplifier using an output stage transistor having a base electrode wiring formed with a plurality of base electrodes corresponding to the number of unit cells,
The collector electrode wiring is connected at one end of each one so that two collector electrode wirings for a unit cell array in which a plurality of collector electrodes are arranged in a straight line are parallel to each other. Part is the output end,
The emitter electrode wiring has two side edge portions respectively parallel to the two unit cell column collector electrode wires, and the side edge portion has a unit cell number in the unit cell column collector electrode wiring. while corresponding plurality of emitter electrodes Ru is formed, it is grounded via the via hole,
Two base electrode wirings are provided corresponding to the two unit cell column collector electrode wirings, and a plurality of base electrodes corresponding to the number of unit cells in each of the unit cell column collector electrode wirings are formed. ,
The two unit cell column collector electrode wirings have the same length in the arrangement direction of the collector electrodes, and the same number of unit cells, but each unit cell connected as the output terminal output stage transistor end of the end portion of the column for the collector electrode wiring opposite side is routed connection is formed, is made by allowing a uniform impedance in the respective unit cells.

  According to the present invention, it is possible to equalize the load impedance of each unit cell while maintaining the ease of connection between the integrated circuit chip and the mounting substrate and good heat dissipation. As a result, the overall operating characteristics of the output stage transistor are reliably improved.

Embodiments of the present invention will be described below with reference to FIGS. 1 to 5.
The members and arrangements described below do not limit the present invention and can be variously modified within the scope of the gist of the present invention.
First, a configuration example of the output stage transistor of the power amplifier in the embodiment of the present invention will be described with reference to FIG. Here, the power amplifier is particularly for a wireless communication device, and is a microwave monolithic integrated circuit (MMIC).
The output stage transistor in the embodiment of the present invention used for such a power amplifier is formed by connecting a plurality of transistor rows (cell rows) CLINE composed of a plurality of transistors whose collectors are mutually connected, In the embodiment of the present invention, two transistor arrays are connected in parallel.

FIG. 1 shows a configuration example of such an output stage transistor, particularly a configuration example focusing on the electrode arrangement.
The output stage transistor in the embodiment of the present invention includes a collector electrode wiring 101 having two unit cell column collector electrode wirings 1 and 2 and an emitter electrode wiring having a plurality of emitter electrodes 25 to 34 formed therein. 102 and two base electrode wirings 103a and 103b in which a plurality of base electrodes 35 to 44 are formed (details will be described later).

The collector electrode wiring 101 has two unit cell column collector electrode wirings 1 and 2 parallel to each other, and one end of each is connected to each other by the output wiring 3. On the other hand, the other end portions of the two unit cell column collector electrode wirings 1 and 2 are connected to each other by the inter-cell column connection wiring 4.
Each of the unit cell column collector electrode wirings 1 and 2 basically has the same configuration. Hereinafter, one unit cell column collector electrode wiring 1 will be described, and the other will be described. The unit cell column collector electrode wiring 2 will be described instead. In the description of the collector electrode wiring 1 for one unit cell column below,
After the reference numerals of the constituent elements, the reference numerals of the corresponding constituent elements of the other unit cell column collector electrode wiring 2 are written in parentheses as necessary.

The unit cell column collector electrode wiring 1 (2) has an overall appearance of a rectangular shape, that is, more specifically, a rectangular shape, and more specifically, a longitudinal direction (in FIG. A plurality of collector electrodes 11 to 16 (17 to 22) are linearly arranged at an appropriate interval in the longitudinal axis direction.
The unit cell column collector electrode wiring 1 is formed with a larger number of collector electrodes by a predetermined number of unit cells. That is, in the embodiment of the present invention, since the unit cell column collector electrode wiring 1 (2) has 5 unit cells, six collector electrodes 11 to 16 (17 to 22) are provided. It has become.
This is because the other collector electrodes 12 to 15 (18 to 21) are adjacent to each other except for the collector electrodes 11 and 16 (17 and 22) located at the ends of the unit cell column collector electrode wiring 1 (2). This is because it is commonly used as a collector electrode in the unit cell.

Here, the unit cell is a unit in which one transistor is formed, and in the configuration example shown in FIG. 1, for convenience, a reference numeral is assigned to each unit cell as described below. .
That is, in one unit cell column collector electrode 1, Tr1a, Tr2a, Tr3a, Tr4a, Tr5a are sequentially formed from the inter-cell column connection wiring 4 side, and in the other unit cell column collector electrode wiring 2, the cell column Tr1b, Tr2b, Tr3b, Tr4b, and Tr5b are arranged in this order from the inter-connection wiring 4 side.

Therefore, in the unit cell column collector electrode wiring 1 (2), the collector electrodes 11, 12 (17, 18) are used in the unit cell Tr1a (Tr1b), and the collector electrodes 12, 13 (18, 19) are unit. Used in the cell Tr2a (Tr2b), the collector electrodes 13, 14 (19, 20) are used in the unit cell Tr3a (Tr3b), and the collector electrodes 14, 15 (20, 21) are used in the unit cell Tr4a (Tr4b). The collector electrodes 15 and 16 (21 and 22) are used in the unit cell Tr5a (Tr5b).
The collector electrodes 11 to 16 (17 to 22) have side edge portions so as to be spaced at an appropriate interval in the longitudinal axis direction of the unit cell column collector electrode wiring 1 (2) and to be orthogonal to the longitudinal axis direction. It protrudes in a rectangular shape from the outside toward the outside.

That is, collector electrodes 11 to 16 in one unit cell column electrode wiring 1 and 17 to 22 in the other unit cell column electrode wiring 2 are formed so as to protrude in opposite directions from the respective side edge portions. It has become.
The two unit cell column electrode wirings 1 and 2 are long in the longitudinal axis direction (left and right direction in FIG. 1), that is, in the arrangement direction of the collector electrodes 11 to 16 and 17 to 22. Are set the same.

  The output wiring 3 that connects one unit cell column collector electrode wiring 1 and the other unit cell column collector electrode wiring 2 at one end is formed into a rectangular shape in its entire planar appearance, and its length The two unit cell column collector electrode wirings 1 and 2 described above are parallel to each other at an appropriate interval on one side edge portion in the axial direction (the vertical direction in FIG. 1), and the output wiring 3 Are formed integrally with the output wiring 3 so as to be orthogonal to each other.

In the output wiring 3, the portions located near the end portions of the unit cell column collector electrode wirings 1 and 2 are set as output terminals 5 and 6, respectively.
The inter-cell column connection wiring 4 is formed in a rectangular shape and is opposite to the other end of the two unit cell column electrode wirings 1, 2, that is, the end connected via the output wiring 3. The end part of the side is connected.

  The emitter electrode wiring 102 is formed in a rectangular shape on the entire plane, and two side edge portions facing each other in the longitudinal axis direction (left and right direction in FIG. 1) are spaced apart from each other by appropriate intervals. Five emitter electrodes 25 to 29 and 30 to 34 are formed so as to protrude outward in a rectangular shape so as to be orthogonal to the longitudinal axis.

The emitter electrode wiring 102 is disposed on the lower layer side of the collector electrode wiring 101. At this time, the emitter electrodes 25 to 29 are arranged with respect to the longitudinal axis direction of one unit cell column collector electrode 1. The emitter electrodes 30 to 34 are arranged in the other unit so that their tip portions are positioned between the corresponding collector electrodes 11 to 16 in the unit cells Tr1a to Tr5a described above. The cell array collector electrode 2 is arranged so as to be orthogonal to the longitudinal axis direction, and the tip portion thereof is positioned between the corresponding collector electrodes 17 to 22 in each of the unit cells Tr1b to Tr5b described above. It has been established.
The emitter electrode wiring 102 is grounded via the via hole 7.

The base electrode wirings 103a and 103b are provided corresponding to the two unit cell column collector electrode wirings 1 and 2, both of which are formed in a relatively elongated rectangular shape as a whole. Base electrodes 35 to 39 and 40 to 44 project from one side edge portion in the longitudinal axis direction (left and right direction in FIG. 1) so as to correspond to the intervals between the previous emitter electrodes 25 to 29 and 30 to 34. It will be.
That is, in one base electrode wiring 103a, the base electrodes 35 to 39 are formed in a rectangular shape so as to be orthogonal to the longitudinal axis from one side edge portion in the longitudinal axis direction of the base electrode wiring 103a. Each interval is equal to the interval between the emitter electrodes 25 to 29.

Also, in the other base electrode wiring 103b, the base electrodes 40 to 44 are formed in a rectangular shape so as to be orthogonal to the longitudinal axis from one side edge portion in the longitudinal axis direction of the base electrode wiring 103b. Each interval is equal to the interval between the emitter electrodes 30 to 34.
The base electrode wiring 103a is disposed so that the tip portions of the base electrodes 35 to 39 are opposed to the tip portions of the emitter electrodes 25 to 29 with an appropriate interval, and the base electrode wiring 103b is The tip portions of the base electrodes 40 to 4 are arranged so as to face the tip portions of the emitter electrodes 30 to 34 with an appropriate interval.

  In such a configuration, for example, if the unit cell Tr1a is taken as an example, the unit cell Tr1a has the collector electrodes 11, 12, the emitter electrode 25, and the base electrode 35 to form one bipolar transistor. It has become. Although individual descriptions of Tr2a to Tr5a and Tr1b to Tr5b are omitted, each bipolar transistor has a collector electrode, an emitter electrode, and a base electrode shown in FIG. 1, as in Tr1a. .

FIG. 2 shows an electrical equivalent circuit of the output stage transistor in such a configuration, and this equivalent circuit will be described below.
In addition, the same code | symbol shall be attached | subjected about the thing corresponding to the component shown by FIG. For convenience, reference numerals Tr1a to Tr5a and Tr1b to Tr5b representing unit cells are simultaneously used as reference numerals of transistors formed in the respective unit cells.

As a result of the configuration shown in FIG. 1, Tr1a to Tr5a are connected to each other by the collector wiring electrode 1 for unit cell columns, and Tr1b to Tr5b are connected to each other by the collector wiring electrode 2 for unit cell columns. The circuit configuration is mutually connected (see FIG. 2).
The collector side of Tr5a is connected to the output terminal 5 and the collector side of Tr5b is connected to the output terminal 6, respectively. These two output terminals 5 and 6 are connected to each other by using the output wiring 3 described above. Connected circuit configuration.
On the other hand, the collector side of each of Tr1a and Tr1b is also connected to each other by inter-cell column connection wiring 4.

  The bases of Tr1a to Tr5a are connected to each other by using the base electrode wiring 103a described above. Similarly, the bases of Tr1b to Tr5b are also described above. Use of the base electrode wiring 103b results in a circuit configuration connected to each other. Although not shown in FIG. 2, the bases of Tr1a to Tr5a and the bases of Tr1b to Tr5 are connected to each other and the same input signal is applied. Yes.

Next, with respect to the operation characteristics of the output stage transistor in the embodiment of the present invention having such a configuration, various characteristic diagrams shown in FIGS. 3 to 5 and the same in the conventional circuit shown in FIGS. This will be described with reference to various characteristic diagrams.
First, the characteristic diagram shown in FIG. 3 will be described.
FIG. 3 is a characteristic line showing an example of the time change of the collector-emitter current Ice during the output saturation of the transistors Tr1a to Tr5a (or Tr1b to Tr5b) of each unit cell of the output stage transistor according to the embodiment of the present invention. FIG. In the figure, since the characteristics of Tr1a to Tr5a and Tr1b to Tr5b are the same, the notation of Tr1 to Tr5 is used. The same applies to FIGS. 4 and 5 described below.

Specifically, it is a characteristic example when the operating frequency is 1.95 GHz, the collector-emitter voltage Vce = 3.5 V, and the number of unit cells in one cell row is 5.
FIG. 8 shows a characteristic example of the conventional circuit shown in FIG. 6 under the same conditions. In FIG. 8, since the characteristics of Tr1a to Tr5a and Tr1b to Tr5b are the same, the display of Tr1 to Tr5 is used. The same applies to FIGS. 9 and 10 described below.

Comparing both, the peak value of the collector-emitter current Ice in each unit cell is more uniform than that of the conventional circuit in the output stage transistor of the embodiment of the present invention. Can be confirmed.
Specifically, the peak value of the transistor Tr5 in the embodiment of the present invention clearly decreases as compared with the transistor Tr5 in the conventional circuit, while the peak value of the transistor Tr1 increases as compared with the conventional circuit. As a whole, the peak values of the transistors Tr1 to Tr5 are made uniform.

FIG. 4 is a graph showing the impedance obtained when the load side is viewed from the collector of the transistors Tr1a to Tr5a (or Tr1b to Tr5b) of each unit cell of the output stage transistor according to the embodiment of the present invention. It is an impedance characteristic diagram shown in the Smith chart of Z0 = 5Ω.
Specifically, the operating frequency is 1.95 GHz, and a 5Ω pure resistor is connected between the collectors of the transistors Tr1a to Tr5a and Tr1b to Tr5b of each unit cell and the ground, and this is used as an alternative to the unit cell transistor. FIG. 6 is a characteristic diagram obtained by performing a simulation.
FIG. 9 shows an example of characteristics under similar conditions in the conventional circuit shown in FIG.

Here, the reason why the unit cell is replaced by a 5Ω pure resistor is as follows. That is, when a load curve is drawn on the collector-emitter current Ice vs. collector-emitter voltage Vce static characteristic curve of the transistor, the peak of the collector-emitter current Ice in FIG. 3 (or FIG. 8) is the knee voltage. On the other hand, the knee voltage depends on the transistor internal resistance (about 5Ω) between the collector and the emitter. Therefore, the impedance state of the transistor of each unit cell at the time of Ice peak is replaced with a 5Ω pure resistor.
Comparing both FIG. 4 and FIG. 9, it can be confirmed that the impedance in each unit cell is more uniform in the output stage transistor of the embodiment of the present invention than in the conventional circuit.

FIG. 5 shows a simulation of impedance when the load side is viewed from the collector of the transistors Tr1a to Tr5a (or Tr1b to Tr5b) of each unit cell of the output stage transistor in the embodiment of the present invention by changing the operating frequency. It is the impedance characteristic figure which showed the calculated | required result in the Smith chart of characteristic impedance Z0 = 5 (ohm).
Specifically, it is a characteristic diagram when the operating frequency is 10 MHz to 10 GHz. Note that the unit cell transistor is replaced with a 5Ω pure resistor in the same manner as described with reference to FIG. 4, and thus detailed description thereof is omitted here.
FIG. 10 shows an example of characteristics under similar conditions in the conventional circuit shown in FIG.

Comparing both FIG. 5 and FIG. 10, even when the operating frequency is changed, the impedance in each unit cell is higher than that of the conventional circuit in the output stage transistor of the embodiment of the present invention. Can be confirmed.
Since the operation of the power amplifier is determined by the Ice-Vce static characteristic curve of the transistor, the operating point, and the load impedance, the impedance uniformity as shown in FIGS. It can be understood that the uniformity of the Ice peak value of each unit cell as shown in FIG.

It is a block diagram which shows typically the structural example of the electrode arrangement | positioning of the output stage transistor in the power amplifier in embodiment of this invention. FIG. 2 is an equivalent circuit diagram of an output stage transistor having the electrode arrangement shown in FIG. 1. It is a characteristic diagram which shows the simulation result of the time change of the collector-emitter electric current Ice at the time of the saturation output in each unit cell of the output stage transistor in embodiment of this invention. It is the impedance characteristic figure which showed the result of having calculated | required by simulation the impedance in the specific operating frequency at the time of seeing the load side from the collector of each unit cell of the output stage transistor in embodiment of this invention. It is the impedance characteristic figure which showed the result of having calculated | required by the simulation in the specific operating frequency range at the time of seeing the load side from the collector of each unit cell of the output stage transistor in embodiment of this invention. It is a block diagram which shows typically the electrode arrangement | positioning of the conventional output stage transistor. FIG. 7 is an equivalent circuit diagram of an output stage transistor having the electrode arrangement shown in FIG. 6. FIG. 7 is a characteristic diagram showing a simulation result of a temporal change in collector-emitter current Ice during saturation output in each unit cell of the output stage transistor shown in FIG. 6. FIG. 7 is an impedance characteristic diagram showing, in a Smith chart, results obtained by simulating impedance in a specific operating frequency range when the load side is viewed from the collector of each unit cell of the output stage transistor shown in FIG. 6. FIG. 7 is an impedance characteristic diagram showing, in a Smith chart, results obtained by simulating impedance in a specific operating frequency range when the load side is viewed from the collector of each unit cell of the output stage transistor shown in FIG. 6.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1, 2 ... Unit cell row | line | column collector electrode wiring 3 ... Output wiring 4 ... Inter-cell row | line connection wiring 101 ... Collector electrode wiring 102 ... Emitter electrode wiring 103a, 103b ... Emitter electrode wiring

Claims (1)

A collector electrode wiring formed with a plurality of collector electrodes corresponding to the number of unit cells, which is a basic unit forming one transistor, and an emitter electrode wiring formed with a plurality of emitter electrodes corresponding to the number of unit cells; A power amplifier using an output stage transistor having a base electrode wiring formed with a plurality of base electrodes corresponding to the number of unit cells,
The collector electrode wiring is connected at one end of each one so that two collector electrode wirings for a unit cell array in which a plurality of collector electrodes are arranged in a straight line are parallel to each other. Part is the output end,
The emitter electrode wiring has two side edge portions respectively parallel to the two unit cell column collector electrode wires, and the side edge portion has a unit cell number in the unit cell column collector electrode wiring. while corresponding plurality of emitter electrodes Ru is formed, it is grounded via the via hole,
Two base electrode wirings are provided corresponding to the two unit cell column collector electrode wirings, and a plurality of base electrodes corresponding to the number of unit cells in each of the unit cell column collector electrode wirings are formed. ,
The two unit cell column collector electrode wirings have the same length in the arrangement direction of the collector electrodes, and the same number of unit cells, but each unit cell connected as the output terminal An output stage transistor in which an end opposite to the end of the column collector electrode wiring is connected to form an output stage transistor , which makes it possible to equalize impedance in each unit cell .

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