JP5308658B2 - Method for generating identification information of semiconductor integrated circuit - Google Patents

Description

  The present invention is directed to a semiconductor integrated circuit, and relates to a semiconductor integrated circuit having a function of generating identification information unique to each semiconductor integrated circuit and its application device.

  As disclosed in Japanese Patent Application Laid-Open No. 2004-101253, a system for measuring a plurality of items of biological and chemical samples using a plurality of semiconductor integrated circuits with sensor functions has been proposed. In this system, a plurality of semiconductor integrated circuits with sensor functions are put into one reaction cell containing a sample solution. In each semiconductor integrated circuit, a ligand that specifically binds to a different detection target is fixed, and a signal is output according to the detection amount of each detection target. Here, identification information is given to the semiconductor integrated circuit with the sensor function, and the sensor information of each semiconductor integrated circuit is individually read out using the identification information, and a plurality of detection objects can be measured collectively. it can. Further, WO02 / 45139 describes that in order to identify a large number of identical specification chips when sorting semiconductor integrated circuits, identification information is given to each chip and recorded in correspondence with the sorting result.

JP 2004-101253 A JP 2006-085411 A Japanese Patent No. 2980576 WO02 / 45139 JP 2006-85411 A

In a measurement system using a semiconductor integrated circuit with a sensor function disclosed in Japanese Patent Application Laid-Open No. 2004-101253, each semiconductor integrated circuit has unique identification information, and simultaneously processes sensor information from a plurality of semiconductor integrated circuits. Is possible. The present invention provides an optimum method for providing identification information to a semiconductor integrated circuit. In order to identify individual semiconductor integrated circuits, the main specifications required for the identification information are the following two points.
(1) The probability that the identification information of different semiconductor integrated circuits match each other is sufficiently small (specificity between chips)
(2) The probability that the identification information of the same semiconductor integrated circuit will fluctuate is sufficiently small (same chip reproducibility)
As a conventional method satisfying the above (1) and (2), (a) a ROM (Read Only Memory) is provided in the semiconductor integrated circuit and identification information is written therein; (b) electrically in the semiconductor integrated circuit. A writable nonvolatile memory is provided and identification information is written therein. (C) A fuse that can be processed by a current, light, mechanical cutter, etc. is provided in the semiconductor integrated circuit, and the identification information is written by processing the fuse. and so on. As for a circuit that realizes the singularity, many methods have been proposed as described in, for example, Japanese Patent No. 2980576.

  The same chip reproducibility by the conventional method shown in the above (a) to (c) will be examined. (A) is realized by changing the pattern of the wiring or diffusion layer for each chip. For this purpose, a photomask whose pattern is changed for each chip in the chip manufacturing process is used, or a maskless exposure means such as a particle beam or a laser is used. In the photomask, in order to realize the randomness between different chips, it is necessary to replace the mask for each exposure process, which increases the manufacturing cost. On the other hand, the maskless means lowers the manufacturing throughput. With regard to (b), a special manufacturing process for forming a nonvolatile memory is required, which also increases the cost. In general, in electrically rewritable nonvolatile memories, the area occupied by peripheral circuits other than memory cells such as a booster circuit is large, and the chip area increases. In (c), since it is necessary to process each chip, the manufacturing throughput is reduced.

  As one means for solving these problems, WO02 / 45139 uses the characteristic variation within the allowable range for quality assurance, such as the threshold voltage of the MOS transistor, and amplifies the variation of the static characteristic of the inverter circuit to identify the identification information. A method of generating is proposed. However, if random variations in device characteristics are small and systematic characteristic variations that depend on circuit patterns, etc. become dominant, identification information often coincides and the inter-chip specificity of identification information is impaired. . Also, if the variation in element characteristics is small, the input signal to the comparator is small, and if it is about the same as the thermal noise of the MOS, the frequency of value fluctuation for each sampling increases, and the same chip reproducibility of identification information is impaired.

  The present invention uses the characteristics variation within the allowable range for quality assurance, such as MOS transistors constituting a semiconductor integrated circuit, while the problems with the prior art, that is, the manufacturing cost, the manufacturing throughput, and the inter-chip specificity and identity of the identification information are the same. A method for solving problems related to chip reproducibility is provided.

  The present invention utilizes a plurality of types of characteristic variations within a range permitted for quality assurance, such as a MOS transistor constituting a semiconductor integrated circuit, for example, a threshold voltage, a parasitic capacitance, and a parasitic resistance of a MOS transistor. Sampling the gate output is a first means in order to use the characteristic variation that affects the characteristic. The second means is to execute sampling a plurality of times, analyze the sampling result, and use a value that occupies a large number as part of the identification information.

  The first means can be realized by the “transient offset detection method”. As shown in FIG. 1, the reference power supply generation circuit 15 is connected to the offset detection circuit 11, and the operating point of the offset detection circuit 11 is determined by the output of the reference power supply generation circuit 15. A timing generation circuit 12 is connected to the offset detection circuit 11, and a pair of offset detection circuits 11 and a comparison circuit 13 are activated at a timing defined by the output of the timing generation circuit 12, and are also generated by the timing generation circuit 12. The latch circuit 14 holds the comparison output of the pair of offset detection circuit elements included in the offset detection circuit 11. This value is used as one bit of the chip unique ID (UIDc) constituting the identification information. A circuit block in which the timing generation circuit 12 and the reference power generation circuit 15 are shared, and the circuit block 10a including the offset detection circuit 11, the comparison circuit 13, and the latch circuit 14 is provided in parallel for a predetermined number of bits is called a UIDc generation circuit. .

  The second means can be realized by the “majority method”. As shown in FIG. 7, the timing generation circuit 12 executes the sequence from the activation of the offset detection circuit 11 and the comparison circuit 13 to the holding of the offset comparison output by the latch circuit 14 in synchronization with the control signal a plurality of times. The counter circuit 17 counts the number of times the output value is “0” and the number of times the output value is “1”. The value having the largest count value is determined by the determination circuit 18 as the value of the bit in UIDc.

  By using the first “transient offset detection method”, that is, variations in characteristics of a plurality of characteristics, for example, variations in threshold voltage, parasitic capacitance, and parasitic resistance of a MOS, the identification information depends on only one characteristic variation. Therefore, the chip-specificity can be improved. FIG. 2 is a diagram showing a configuration for detecting an offset with a static transfer characteristic of an inverter as a conventional technique. In FIG. 2C, assuming that the transfer characteristic of one inverter is 110, the transfer characteristic when the threshold voltage of the pMOS 21 of another inverter is smaller than 110 is 112. When these two inverters are paired to form an offset detection circuit, one bit of UIDc can be generated by amplifying the output of the offset detection circuit. However, when the difference in threshold voltage is small and the output of the offset detection circuit is small, the corresponding 1 bit in UIDc becomes unstable.

  Therefore, attention is paid to the transient characteristics at the start of energization of the offset detection circuit element in which the pMOS 30 and the nMOS 31 shown in FIG. When the pair of offset detection circuit elements is turned from the off state to the on state, the voltage at the output terminal changes depending on the time constant determined by the on resistance and load capacitance of the pMOS and nMOS. Is used as one bit of identification information. By this transient offset detection method, the inter-chip specificity can be increased.

  The second chip, that is, sampling is performed a plurality of times, the sampling result is analyzed, and a value occupying a large number is used as a part of the identification information, so that the same chip reproducibility can be improved.

  The effect common to the first and second means is that a semiconductor integrated circuit having unique identification information can be manufactured at a low cost with a high manufacturing throughput because only a normal LSI process is used.

  In the present invention, identification information unique to each semiconductor integrated circuit device is generated based on variations in a plurality of physical parameters related to characteristics of a MOS transistor, a bipolar transistor, a diode, an impurity diffusion layer, a wiring, etc. constituting the semiconductor integrated circuit. . The difference from the prior art is that the present invention uses the transient response of the identification information generation circuit, and the identification information generation circuit is reset, started up, and the output latch is repeated a plurality of times, and the output information is accumulated each time. It is to select output information with high frequency.

  FIG. 1 shows an example of the configuration of a circuit that generates identification information composed of binary numbers having a bit number Nc. The identification information is constituted by a binary number having a bit number Nc generated by connecting Nc (10a, 10b,...) Chip unique ID (UIDc) bit generation circuits in parallel. The UIDc bit generation circuit 10a includes an offset detection circuit 11, a comparison circuit 12, and a latch circuit 14, and the output of the reference power supply circuit 15 is applied to the gates of the pMOS and nMOS of the offset detection circuit. In the UIDc bit generation circuit, the timing generation circuit 12 controls circuit reset, power supply to the circuit, sampling, and the like. The identification information samples the transient response, is binarized by the comparison circuit 13, and is latched by the latch circuit 14 to be 1 bit of UIDc.

An embodiment relating to a configuration method of the comparison circuit in the UIDc bit generation circuit 10a will be described. For comparison, FIG. 2A shows an offset detection circuit element using a CMOS inverter as a conventional technique. FIG. 2C is a diagram illustrating the transfer characteristics of the inverter. As in WO02 / 45139, by connecting the input and output of the MOS inverter, the voltage at the output terminal assumes a logic threshold V _M. FIG. 2B shows an equivalent circuit in which the pMOS and nMOS that are the components of the inverter are replaced by resistors R1 and R2, respectively. At this time, the potential of the terminal _Vout can be expressed as the following equation (1), where the power supply voltage is _Vdd . In the case of an inverter according to MOS, likewise pMOS, by considering the conductance of nMOS, V _M can be expressed by the following equation (2). Here k _p and k _n is defined by the formula (3) and (4). μ _p , μ _n are the mobility of holes and electrons, C _ox is the gate oxide thickness of the MOS, W and L are the gate width and length of the MOS, and V _Tp and V _Tn are the threshold voltages of the pMOS and nMOS. .

μ _p , μ _n , C _ox , W, L, V _Tp, and V _Tn all vary due to variations in MOS manufacturing, have a distribution within the same wafer, and even if adjacent MOSs are strictly It will not be the same value. There is a difference of several mV in terms of V _Tp and V _Tn . If the MOS has been manufactured exactly as designed, and the characteristic 110 shown in FIG. 2C is obtained, the characteristic 111 against the parameter fluctuation that increases the channel conductivity of the nMOS relative to the pMOS. For the parameter fluctuation that increases the channel conductivity of the pMOS relative to the nMOS, the transfer function shifts in the direction of the characteristic 112, and the magnitude of the output of the pair of inverters is binarized by the comparison circuit. As a result, it is possible to use one bit of identification information unique to the chip.

  In the present invention, not only physical parameters that determine static characteristics used in the prior art but also physical parameters that affect dynamic operation are used. A typical parameter that affects dynamic properties is capacitance. This will be described with reference to FIG. A switch 40 is provided between the source side of the nMOS 31 and the ground potential, and the value of the output terminal 41 after a predetermined time td after the switch 40 is changed from the OFF state to the ON state and the switch 56 is simultaneously changed from the ON state to the OFF state. read.

Here, 34, 35, 36, 37, 38, 39, 46, 47, 48, and 49 in the figure indicate capacitances. These assume a parasitic capacitance, but may be intentionally formed. The circuit of FIG. 3A can be expressed as an equivalent circuit as shown in FIG. 3B by setting the on-resistance of the pMOS 30 to R1. R1 corresponds to the resistor 44 in FIG. The time constant t _LH of the change of the output terminal 41 can be expressed as in Expression (5).

Here, R ₀ is an on-resistance of the pMOS and nMOS, and C _L is an amount determined from the capacitances 34, 35, 36, 37, 38, 39, 48, and 49, respectively. FIG. 3C is a diagram illustrating transient characteristics. Assuming that the transient characteristics of the offset detection circuit element when the values of pMOS, nMOS, and capacitance are exactly standard values are 113, the threshold voltage of the pMOS 21 of the inverter in another offset detection circuit element is 113. The transfer characteristic when it is smaller than the case is 114. In the present invention, attention is paid to transient characteristics in a pair of offset detection circuit elements, and 1 bit of identification information is generated depending on the magnitude of output at a predetermined time.

  In the example of FIG. 3, the pMOS and the nMOS are connected in series as an offset detection circuit element. However, as shown in FIG. 4, one of the MOSs may be replaced with a passive resistor. FIG. 4A shows an embodiment in which nMOS is replaced with a passive resistor, and FIG. 4C is an embodiment in which pMOS is replaced with a passive resistor. FIGS. 4B and 4D are equivalent circuits in which the pMOS and nMOS in FIGS. 4A and 4C are replaced with resistors R1 and R2, respectively.

  FIG. 5 shows a configuration example of an offset detection circuit according to the present invention. The two offset detection circuit elements shown in FIG. 3, that is, a first offset detection circuit element in which the pMOS transistor 30 and the nMOS transistor 31 are connected in series, and a second offset in which the pMOS transistor 30a and the nMOS transistor 31a are connected in series. An equalizing switch 51 for short-circuiting the output ends 57 and 58 of both offset detection circuit elements is provided with the detection circuit elements as a pair. In the initial state, the equalizing switch 51 is turned on and the switches 40 and 40a are turned off. During operation, the equalizing switch 51 is turned off and the switches 40 and 40a are turned on. Transient responses reflecting variations in MOS transistors and variations in parasitic capacitance are output to the respective output terminals 57 and 58, and 1 bit of identification information can be obtained by binarizing the response by a comparison circuit.

  FIG. 6 shows an embodiment in which a part of the MOS transistor in the offset detection circuit element is replaced with a passive resistor. In these offset detection circuits, the equalizing switch 51 is turned on and the switches 40 and 40a are turned off in the initial state, and the equalizing switch 51 is turned off and the switches 40 and 40a are turned on during operation. 57 and 58 are output transient responses reflecting variations in MOS transistors and variations in parasitic capacitance. By binarizing the transient responses using a comparison circuit, one bit of identification information can be obtained.

  A configuration example of an identification information generation circuit that samples the output of the offset detection circuit a plurality of times is shown in FIG. As a result, identification information composed of binary numbers having the bit number Nc can be generated. By connecting Nc (10a, 10b,...) Chip unique ID (UIDc) bit generation circuits in parallel, identification information of the number of bits Nc is generated.

  The UIDc bit generation circuit 10a includes an offset detection circuit 11, a comparison circuit 13, and a latch circuit 14. The output of the reference power supply circuit 15 is applied to the gates of the pMOS and nMOS constituting the offset detection circuit. The UIDc bit generation circuit is controlled by the timing generation circuit 12 for resetting the circuit, energizing the circuit, sampling, and the like. For the sampled identification information, the transient response is binarized by the comparison circuit 13 and temporarily recorded by the latch circuit 14. Sampling is repeated a plurality of times by the timing generation circuit 12, and the sampling result is input to the counter circuit 17. By inputting the counter circuit output to the determination circuit 18, a value occupying the majority of the plurality of latch circuit outputs (sampling results) is obtained, and this is set as one bit of UIDc.

Hereinafter, an operational problem and a solution of the UIDc bit generation circuit 10a will be described. The data latched by the latch circuit 14 may be binary data or multi-value data. In the case of binary data, binary “0” or “1” is latched at each sampling. Even in a device such as a MOS formed on the same chip, hole mobility μ _p , electron mobility μ _n , MOS gate capacitance C _ox , MOS gate width W, MOS gate length L, pMOS threshold voltage V _Tp , There are slight differences inherent to individual devices in terms of individual device parameters, such as nMOS threshold voltage V _Tn , parasitic capacitance, etc. due to manufacturing processes and material non-uniformities. If there is a difference in device parameter characteristics in the offset detection circuit element pair, an output difference occurs at the output ends 57 and 58 of the offset detection circuit element, and the latch output of the same offset detection circuit element pair is detected multiple times. The same value is obtained each time in the latch operation. However, among many offset detection circuit element pairs, a difference in device parameters such as a MOS transistor, a parasitic capacitance, and a parasitic resistance is probabilistically small, and a difference in output between the output terminals 57 and 58 is small. In some cases, binary data latched in a plurality of offset detection-latch operations do not match due to the influence of f noise.

  In order to solve this problem, a configuration in which a counter circuit 17 and a determination circuit 18 are provided in the identification information generation circuit of FIG. 1 is adopted. First, the output of the offset detection circuit described so far is latched, and the counter is incremented according to the output. The timing generation circuit performs the offset detection-latch sampling operation a plurality of times. In each sampling, the number of occurrences of “0” and “1” latched by the latch circuit is counted by the counter circuit 17, and data occupying the majority is adopted. According to this method, the probability of occurrence of output fluctuation when the device parameter difference is small can be greatly reduced.

  The effect of sampling multiple times is shown in FIG. In the binary output offset detection circuit, the difference in device parameters is small, and when sampling is performed a plurality of times, binary number x is output with probability of p and binary number y is output with probability of 1-p (x and y are When binary is different from each other) and y occupies a large number, x is erroneously set. If p is set to 0.01, the probability of erroneous setting in one sampling is 0.01, and the reliability as unique identification information cannot be ensured as it is. Therefore, sampling is performed n times and a majority decision is made, and the output occupying the majority is used as identification information. In this case, n is desirably an odd number so that the same number of sampling results are not obtained. The probability of r times of erroneous output after n times of sampling can be expressed by the following equation (6).

Using the equation (6), the erroneous setting rate in which the erroneous setting (probability in which the setting having a low appearance probability occupies the majority) is made by sampling n times is shown in the rightmost column of the table of FIG. Show. When p = 0.01, the erroneous setting rate is 0.01 after one sampling. However, if the sampling number is increased, the erroneous setting rate can be reduced to 3.4e ^-7 . FIG. 8B is a graph showing changes in the number of samplings and the erroneous setting rate.

  An embodiment of the UIDc bit generation circuit 10 according to the present invention will be described with reference to FIG. This is a circuit diagram of the UIDc generation circuit block configuration of FIG. One of the pair of offset detection circuit elements is a series connection of pMOS and nMOS represented by MP1 and MN1, and the other is a series connection of pMOS and nMOS represented by MP2 and MN2. FIG. 10 shows the overall configuration of the UIDc bit generation circuit of FIG. Here, only one timing generation circuit 104 may be provided in common for each UIDc bit generation circuit. The reference power supply circuit 15 may be provided for each UIDc bit generation circuit, or only one reference power supply circuit 15 may be provided in the chip and used in common.

  The operation timing will be described with reference to FIG. The identification information generation circuit is driven by a clock indicated by uid_clk. Although the setting of the clock frequency is arbitrary, for example, 847.5 kHz obtained by dividing the frequency 13.56 MHz often used for RF communication by 16 can be used. Normally, the identification information generation circuit is in an off state for reducing power consumption. However, if it is necessary to generate identification information, the identification information generation circuit is turned on by turning on the uid_enable signal. Enter the generation sequence. Thus, by turning on vp and vn in FIG. 9, the reference power supply circuit is set, and the nodes vb and vc rise to prepare for turning on the offset detection circuit. With the rise of It1, the switches 40 and 40a in the offset detection circuit element are turned on for two clock cycles. It2 is turned on for one clock cycle one clock cycle after the rise of It1, the output of the comparator circuit is latched at this timing, and It3 is turned on for one cycle simultaneously with the fall of It1 and It2, and is synchronized with this. At the same time as the counter is incremented, the equalizing switch 51 is turned on and the two outputs of the offset detection circuit element pair are short-circuited to reset the outputs to prepare for the next transient characteristic sampling. By repeating this a predetermined number of times (seven times in FIG. 11), the counter counts the output prvs of the offset detection circuit for each data (in the case of binary numbers, “0” and “1”, respectively). When the sampling is executed a predetermined number of times, the decision circuit 18 executes a “majority decision” in synchronization with the uidlt signal from the timing generation circuit, and the value of the output data occupying the majority is output as uid <0>. As shown in FIG. 10, uid <1>, uid <2>, ... can be generated by parallelizing the same circuit configuration as uid <0>, and chip-specific identification information is generated using these values. it can. For example, by providing eight offset detection circuits in parallel, 8-bit chip identification information such as (01010101) can be generated as a binary number.

  An example in which the identification information generation circuit of the present invention is applied to a sensor chip with communication function (hereinafter referred to as RFID sensor chip) 70 is shown in FIG. Details of the basic configuration of this chip are disclosed in Japanese Patent Application Laid-Open No. 2004-101253. FIG. 12A shows a configuration example of an RFID sensor chip on which the identification information generation circuit 72 is mounted so as to be connected to the control circuit 73. The identification information generated in 72 enables the reader 80 to individually communicate with a plurality of RFID sensor chips within a communicable range. The identification information generation circuit mounted on the RFID sensor chip preferably has the majority function described with reference to FIGS.

  The RFID sensor chip 70 is composed of, for example, one or a plurality of types selected according to the measurement purpose from a temperature sensor that measures the temperature of the solution, a pH sensor that detects the ion concentration in the solution, an optical sensor, and the like. A sensor 75 is incorporated. The measurement system shown in FIG. 12 controls the reader 80 that communicates with the RFID sensor chip 70 via the reader coil 81, processes the acquired measurement data, and evaluates and records the measurement result. A measurement control device 82 is used.

  The RFID sensor chip 70 is supplied with electric power by inductive coupling between the chip coil 76 and the reader coil 81, transmits and receives signals, and generates an internal clock signal. An induction current is excited in the chip coil 76 by, for example, an AC magnetic field of 13.56 MHz generated by the reader coil 81 using the reader 80 as a generation source, and this is rectified by the RF communication interface 71 to be a DC voltage source. This is supplied to each circuit in the chip as a power source of the RFID sensor chip 70. The 13.56 MHz AC magnetic field generated from the reader 80 via the reader coil 81 is also used as a carrier wave for sending a control signal for giving an instruction to each block of the RFID sensor chip to execute measurement and communication. The control signal carried on the carrier wave by the reader 80 is demodulated by the RF communication interface 71, decoded by the control circuit 73, and sent to each block of the RFID sensor chip via the logic circuit in 73. Further, the alternating magnetic field generated by the reader 80 is divided by the RF communication interface 71 and used for generating a chip internal clock signal. Next, communication from the RFID sensor chip to the reader will be described. Analog data, which is a measurement result detected by the sensor 75, is amplified by an amplifier in the circuit block 74, converted to digital data by an ADC, and then encoded by a control circuit 73. A constant (for example, resonance frequency or Q value) of a resonance circuit on the RFID sensor chip including the chip coil 76 is modulated by digital data encoded in the RF communication interface 71. Due to the modulation of the resonance circuit constant, a voltage fluctuation occurs at the output end (reader coil end) of the reader 80. The signal from the RFID sensor chip can be transmitted to the reader 80 by amplifying, demodulating, and decoding this. In the transmission / reception of the signal, the control circuit 73 has a function of controlling a sensor, an amplifier, an ADC, a sensor control circuit, and the like in addition to encoding. By referring to the unique ID (UIDc), each block of the RFID sensor chip is controlled while determining whether or not the control signal is directed to its own chip.

  FIG. 12B shows an example in which an ID (sensor identification information, Japanese Patent Application Laid-Open No. 2006-85411) peculiar to the type of sensor mounted on the chip is combined with identification information unique to the chip according to the present invention. This embodiment is effective in simplifying the control and realizing the simultaneity of the measurement by transmitting the control commands to the chips on which the same type of sensor is mounted at a time while identifying the individual chips.

  FIG. 13 is a conceptual diagram of a multi-item measurement system using an RFID sensor chip equipped with the identification information generation circuit of the invention. In the figure, chips 61, 62, and 63 are sensor chips with a wireless function on which an optical sensor is mounted, and a first DNA probe 64, a second DNA probe 65, and an antibody probe 66 are fixed on the surface, respectively. The chip 67 is a charge sensor (ISFET: Ion Sensitive Field Effect Transistor) that detects the hydrogen ion concentration, and the chip 68 is an RFID sensor chip on which a temperature sensor is mounted. These chips are put into a reaction vessel 90 containing a sample solution 91, and the temperature and pH of the sample and the target 92 in the sample are measured. Each RFID sensor chip can be independently controlled by a single reader 80 having a reader coil 81 by mounting a unique identification information generation circuit, individually reading information, and displaying the result on the measurement control device 82. It becomes possible to do.

  FIG. 14 shows a control flow when driving a plurality of RF sensor chips with the identification information (UIDc) generated in the present invention. Here, a case where the sensor type mounted on the RF sensor chip is only an optical sensor will be described. First, the RF sensor chip in the communication field of the reader coil is recognized by the “inventory” command from the reader, and the UIDc of each RF sensor chip is acquired. Here, since all the sensor types are optical sensors, first, a constant reverse voltage is applied to the photodiodes by the 'sensor initialization' command to store all charges. When signal light is incident during the subsequent signal accumulation period, the accumulated charges are sequentially discharged, and the charges are lost according to the amount of incident light, and the voltage applied in the reverse direction decreases. After a certain time, the reverse voltage is measured by the 'measure' command and AD conversion is performed. Finally, measurement is performed by sequentially reading out the sensor measurement values of each RF sensor using the UID.

  FIG. 15 shows a functional block diagram when the present invention is applied to a semiconductor integrated circuit 120 having a memory or arithmetic circuit 121. The identification information generation circuit 72 of the present invention can be formed without using a special process and has a small layout area. Therefore, the identification information generation circuit 72 can be easily incorporated into a semiconductor integrated circuit having a memory or an arithmetic function.

  As shown in FIG. 16, a probe 123 is brought into contact with a bonding pad 122 provided in a semiconductor integrated circuit 120 having a memory or an arithmetic function to supply power and input / output signals, and a characteristic measuring device 125 evaluate. According to this evaluation result, defective products and sorted products are classified. Conventionally, since a chip does not have a unique identification means, in order to classify a large number of chips, the position coordinates of the chips placed in a matrix are associated with the measurement results. With this method, there is a problem that the correspondence cannot be taken when the chip position is changed. In addition, there is a method of marking a result on a chip with ink or laser, but hardware is required for marking, and there is a limit to the amount of information that can be recorded. If the identification information generation circuit of the present invention is incorporated in the chip, the chip can be easily identified by the identification information unique to the chip read by the identification information reader 128 with the probe 126 in contact with the signal monitoring pad. The characteristic measurement device 125 and the identification information reading device 128 are controlled by the characteristic measurement control device 130, and the characteristic measurement result is recorded in the characteristic measurement control device 130 in association with the identification information. This eliminates the need for marking work, and enables sorting and classification work to be performed accurately and efficiently.

The figure which shows the circuit block of the identification information (UIDc) generation circuit specific to a chip. The figure explaining the conventional offset detection circuit element. The figure explaining an offset detection circuit element. The figure which shows the circuit block of a UIDc production | generation circuit. The figure which shows the effect of sampling multiple times of offset. The figure which shows the circuit structure of a UIDc generation circuit (for 1 bit). The figure which shows the drive timing of a UIDc production | generation circuit. The figure which shows the circuit structure of a UIDc production | generation circuit. The figure which shows the structure of the RFID sensor system provided with the UIDc generation circuit. The figure which shows the structure of the RFID sensor system provided with the UIDc generation circuit. The figure which shows the drive timing of the RFID sensor system provided with the UIDc production | generation circuit. The figure which shows the structure of the RFID sensor system provided with the UIDc generation circuit. The figure which shows the structural example of the multiple item simultaneous measurement system by the RFID sensor which comprised the UIDc production | generation circuit. The figure which shows the example of the control flow of the RFID sensor provided with the UIDc production | generation circuit. The figure which shows the example of the semiconductor integrated circuit which mounts the UIDc production | generation circuit for selection. The figure which shows the example which applied the UIDc production | generation circuit to the selection of a semiconductor integrated circuit.

Explanation of symbols

10a-b: circuit block of chip identification information (UIDc) generation circuit (for 1 bit), 11: offset detection circuit, 12: timing generation circuit, 13: comparison circuit, 14: latch circuit, 15: reference power supply circuit, 16 : UIDc bit 0 output terminal, 17: counter circuit, 18: determination circuit, 21: p-channel MOS transistor (pMOS), 22: n-channel MOS transistor (nMOS), 30: pMOS, 31: nMOS, 32: pMOS Gate terminal, 33: nMOS gate terminal, 40: switch, 41: output terminal, 42: pMOS n-well terminal, 43: nMOS p-well terminal, 44: equivalent resistance of pMOS channel, 45: equivalent resistance of nMOS channel 48: Load capacity, 49: Load capacity, 51: Equalizing switch, 56: Switch 57: Output of the offset detection circuit element, 58: Output of the offset detection circuit element, 61: RFID sensor chip, 62: RFID sensor chip, 63: RFID sensor chip, 64: DNA probe, 65: DNA probe, 66: Antibody, 67: RFID sensor chip, 68: RFID sensor chip, 70: RFID sensor, 71: RF communication interface, 72: Identification information generation circuit, 73: Control circuit, 74: Amplifier / ADC / sensor control block, 75: Sensor , 76: chip coil, 80: reader, 81: reader coil, 82: measurement controller, 90: reaction vessel, 91: reaction buffer, 92: target DNA, 100-103: UIDc generation circuit (for 1 bit) Block 104: Timing generation circuit 120: Semiconductor integration Path 121: memory or arithmetic function block 122: bonding pad 123: probe 124: wiring 125: characteristic measuring device 126: probe 127: wiring 128: identification information reading device 129: signal monitoring pad , 130: characteristic measurement control device

Claims (16)

A signal transmitting and receiving unit;
An identification information generating unit having N (N is an integer of 2 or more) bit generation circuits connected in parallel and generating an N-bit binary number as identification information;
A control unit that controls transmission of the identification information generated by the identification information generation unit from the signal transmission / reception unit,
The bit generation circuit includes:
A reference power supply circuit for generating a reference signal;
An offset detection circuit including two circuits connected in parallel, each of the two circuits including a transistor that receives an input of the reference signal;
First and second switches for energizing the two circuits including the transistor,
A comparison circuit that compares the magnitudes of the outputs of the two transistors and outputs a binarized signal;
A latch circuit for holding the output of the comparison circuit;
A timing generation circuit for controlling the opening and closing timing of the first and second switches and the timing for holding the output of the comparison circuit by the latch circuit;
The initial state by a timing signal generated from the timing generation circuit closing said first and second switches is open and energizing the two circuits including the transistor, was then generated from the timing generating circuit A semiconductor chip, wherein an output of the comparison circuit to which an output of the two transistors indicating a transient response is input is held in the latch circuit by a timing signal.   2. The semiconductor chip according to claim 1, further comprising a third switch for connecting the outputs of the two transistors, the timing signal generated from the timing generation circuit after the output of the comparison circuit is held in the latch circuit. And closing the third switch. 2. The semiconductor chip according to claim 1, wherein the reference power supply circuit and the timing generation circuit are provided in common to the N bit generation circuits. The semiconductor chip according to claim 1, further comprising a counter for counting each type output of an output of said latch circuit, and a determination section for outputting a decision on the output type in which the majority in the counter, the timing generator The circuit repeats a step of holding the output of the comparison circuit, to which the outputs of the two transistors indicating the transient response are input, in the latch circuit, a plurality of times.   5. The semiconductor chip according to claim 4, wherein the process is repeated an odd number of times. The semiconductor chip according to claim 2, wherein
The circuit including the transistor is a circuit in which a p-channel MOS transistor and an n-channel MOS transistor are connected in series.
The reference signal is applied to the gates of the p-channel MOS transistor and the n-channel MOS transistor,
The third switch connects the output terminals of two circuits with a node connecting drains of the p-channel MOS transistor and the n-channel MOS transistor as an output terminal,
The timing signal generated from the timing producing formation circuit, said third switch is turned off, it holds the output of the comparator circuit to the latch circuit when said first and second switches are on A featured semiconductor chip. Submit The semiconductor chip of claim 4, further comprising a circuit for digitizing and amplifies the sensor, the signal of the sensor, the control unit, the signal of the sensor is digitized from the signal transmission and reception unit A semiconductor chip that is controlled.   8. The semiconductor chip according to claim 7, wherein the process is repeated an odd number of times.   5. The semiconductor chip according to claim 4, further comprising a memory operation circuit.   10. The semiconductor chip according to claim 9, wherein the process is repeated an odd number of times. A sensor, a circuit for amplifying and digitizing the signal of the sensor, a wireless communication circuit, and N (N is an integer of 2 or more) bit generation circuits connected in parallel, and an N-bit binary number as identification information A semiconductor chip comprising: an identification information generating unit for generating the identification information; a control unit for controlling transmission of the identification information generated by the identification information generating unit and the digitized sensor signal from the wireless communication circuit;
In a wireless communication measurement system comprising a reader for transmitting a signal for controlling the sensor to the semiconductor chip and receiving the sensor signal,
The bit generation circuit of the semiconductor chip is
A reference power supply circuit for generating a reference signal;
An offset detection circuit including two circuits connected in parallel, each of the two circuits including a transistor that receives an input of the reference signal;
First and second switches for energizing the two circuits including the transistor,
A comparison circuit that compares the magnitudes of the outputs of the two transistors and outputs a binarized signal;
A latch circuit for holding the output of the comparison circuit;
A timing generation circuit for controlling the opening and closing timing of the first and second switches and the timing for holding the output of the comparison circuit by the latch circuit;
The initial state by a timing signal generated from the timing generation circuit closing said first and second switches is open and energizing the two circuits including the transistor, was then generated from the timing generating circuit The wireless communication measurement system, wherein an output of the comparison circuit to which an output of the two transistors indicating a transient response is input by a timing signal is held in the latch circuit. The wireless communication measurement system according to claim 11, further comprising: a counter that counts the output of the latch circuit for each output type; and a determination unit that determines and outputs an output type that occupies a large number in the counter, The timing generation circuit repeats a process of holding the output of the comparison circuit, to which the outputs of the two transistors indicating the transient response are input, in the latch circuit, a plurality of times. .   13. The wireless communication measurement system according to claim 12, wherein the process is repeated an odd number of times. A semiconductor integrated circuit including a storage operation circuit, and N (N is an integer of 2 or more) bit generation circuits connected in parallel, and including an identification information generation unit that generates an N-bit binary number as identification information;
A measuring device for measuring the memory operation circuit characteristics of the semiconductor integrated circuit;
A device that reads the identification information of the semiconductor integrated circuit and associates the identification information with the characteristics measured by the measurement device;
The bit generation circuit of the semiconductor integrated circuit is
A reference power supply circuit for generating a reference signal;
An offset detection circuit including two circuits connected in parallel, each of the two circuits including a transistor that receives an input of the reference signal;
First and second switches for energizing the two circuits including the transistor,
A comparison circuit that compares the magnitudes of the outputs of the two transistors and outputs a binarized signal;
A latch circuit for holding the output of the comparison circuit;
A timing generation circuit for controlling the opening and closing timing of the first and second switches and the timing for holding the output of the comparison circuit by the latch circuit;
The initial state by a timing signal generated from the timing generation circuit closing said first and second switches is open and energizing the two circuits including the transistor, was then generated from the timing generating circuit An output of the comparison circuit to which an output of the two transistors indicating a transient response is input by a timing signal is held in the latch circuit. In claim 14, wherein the sorting system includes a counter for counting each type output of an output of said latch circuit, and a determination section for outputting a decision on the output type in which the majority in the counter, the timing generator The circuit repeats a step of holding the output of the comparison circuit, to which the outputs of the two transistors indicating the transient response are input, in the latch circuit a plurality of times.   16. The sorting system according to claim 15, wherein the process is repeated an odd number of times.

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