JP5311466B2 - Memory control method and apparatus - Google Patents

Description

  The present invention relates to a memory control method and apparatus including refresh of a volatile memory such as a DRAM.

  Data stored in volatile memory cells, such as dynamic random access memory (DRAM) cells, disappears in a short time. For this reason, the memory cells must be periodically refreshed to hold data. Therefore, an integrated circuit including a large number of volatile memory cells such as a DRAM and an SDRAM has a function (auto-refresh function) for periodically executing a refresh cycle.

Patent Document 1 discloses an auto-refresh request generation circuit that generates an auto-refresh request at a predetermined interval, and holds the auto-refresh request for the dynamic random access memory when the auto-refresh request is generated, An auto-refresh control circuit is disclosed that includes a hold count circuit for counting and a circuit for making an auto-refresh request held in the dynamic random access memory until the held count is reached when an idle state is detected. In the memory controller including the auto-refresh control circuit, when the held auto-refresh request is executed, the hold count is updated based on the executed count.
JP 2005-310245 A

  The refresh timing for the SDRAM varies depending on the capacity of the SDRAM. For example, access is required 4096 times / 64 ms for 64 Mbits and 128 Mbits, and 8192 times / 64 ms for 256 Mbits and 512 Mbits. Furthermore, the refresh cycle needs to be performed in an idle state. Therefore, in Patent Document 1, an auto-refresh request is held when not in an idle state.

  Also, the memory cannot be accessed during the refresh cycle. If the time required for one refresh cycle is 140 ns, for example, if 8192 refresh cycles are executed during 64 ms, 1.15 ms is consumed for refresh and the memory cannot be accessed. In order to improve the memory transfer rate, it is necessary to reduce the refresh frequency, but in order to prevent data loss, the refresh frequency cannot be reduced.

  One aspect of the present invention holds a plurality of written first addresses that are write-accessed to a volatile memory device that includes a large number of memory cells accessible by address data including a first address and a second address. To the first address storage unit that has been written, and among the plurality of written first addresses, there is no write access and no read access within the first time that requires a refresh operation, and there is an unaccessed written first address. A dummy read unit that issues a dummy read command for performing a dummy read, and a first address that has been read-accessed among a plurality of written first addresses is erased from the first address storage unit A refresh control device having an update unit to perform. A typical volatile memory device is a DRAM, the first address is a row address, and the second address is a column address.

  For applications that may be repeatedly read to the same address, the update unit includes a function that determines that the read access is the final read access, and the written unit where the final read access was made. It is desirable to erase only the first address from the first address storage unit. Alternatively, the update unit includes a function of determining that the read access is a data holding type read access for securing re-reading with respect to the same address, and the written first data that has been subjected to the data holding type read access is included. Is preferably stored in the first address storage unit.

  In the method of issuing the auto refresh command, there is no means for knowing from the outside of the DRAM which row address is being refreshed. For this reason, it is necessary to perform refresh for the entire area of the DRAM, and a predetermined number of auto-refresh commands must be issued within a certain period. Therefore, the DRAM cannot be accessed for a certain time required for refresh. A memory cell of a volatile memory device such as a DRAM is also refreshed by memory read or memory write. Furthermore, it is only necessary to refresh only the memory cells that need to hold data among the many memory cells included in the volatile memory device. For this reason, in the present invention, data retention is guaranteed by storing a written row address and performing dummy read when there is no write or read access to the written row address during the refresh cycle. At the same time, the number of refreshes is suppressed. Furthermore, if there is a read access (or final read access) that can discard the data of the written row address, the number of refreshes is suppressed by erasing the read written row address.

Since this method generates a row address for dummy read, the time required for refresh (first consumption time) at which the frequency of dummy read is high is the time required for refresh using auto-refresh (second consumption time). ) May be longer. However, when the theoretical first consumption time and the second consumption time are the same, the actual first consumption time is shortened by the amount that the dummy read for the row address where the read access has been made is not issued. Therefore, the refresh control device of the present invention includes an auto-refresh unit that issues a predetermined number of auto-refresh commands to the volatile memory device within a first time, and a dummy read unit or an auto-refresh unit. further comprising a monitoring unit to enable. The monitoring unit auto-refreshes the volatile memory device by the first consumption time and auto-refresh unit required for performing dummy read on the plurality of first addresses already written held in the first address storage unit. When the first consumption time is equal to or shorter than the second consumption time, the dummy read unit is enabled, the auto-refresh unit is disabled, and the first consumption time is When the time is longer than the second consumption time, the dummy read unit is disabled and the auto refresh unit is enabled.

  This refresh control device can be incorporated into a memory control device. That is, another aspect of the present invention is a memory control device, which includes a refresh control device and an access request unit. The access request unit issues an access request to the volatile memory device based on a write access instruction including address data and a write command for writing to the volatile memory device, or a read access instruction including a read address data and a read command. Issue. The access request unit also supplies the refresh control device with write address data and read address data as address data of the refresh control device. The memory control device preferably includes an arbitration unit that arbitrates access to the volatile memory device between the access request and the dummy read command or the auto-refresh command.

  Another aspect of the present invention is a data processing device having the above memory control device, a volatile memory device controlled by the memory control device, and a data processing unit. The data processing unit includes a function of generating data to be written to the volatile memory device by a write access command and executing a process using data read from the volatile memory device by a read access command. A typical data processing device is a semiconductor integrated circuit device such as an ASIC, a processor, or a microcomputer. The data processing apparatus may be an information processing terminal such as a printer, a personal computer, a mobile phone, or a PDA.

Another aspect of the present invention is a memory control method including the following steps.
(1) First address storage of a plurality of written first addresses that have been write-accessed to a volatile memory device including a large number of memory cells accessible by address data including a first address and a second address To keep in the department.
(2) A dummy that performs a dummy read on an unaccessed written first address that does not have a write access and a read access within a first time that requires a refresh operation among a plurality of written first addresses. Issue a read command.
(3) Erasing, from the first address storage unit, the written first address that has been read-accessed among the plurality of written first addresses.

It is desirable that the memory control method further includes the following steps.
(4) Issue a predetermined number of auto-refresh commands to the volatile memory device within a first time.
(5) The volatile memory device is auto-refreshed by the first consumption time and the auto-refresh command required for performing the dummy read with respect to the plurality of written first addresses held in the first address storage unit. The second consumption time required for the comparison is compared, and when the first consumption time is the same as or shorter than the second consumption time, it is selected to issue a dummy read command, and the first consumption time is the second consumption time. If it is longer than the consumption time, choose to issue an auto-refresh command.

  FIG. 1 shows a schematic configuration of the printer. The printer 1 includes a printing mechanism (printer mechanism) 2 including a printing mechanism such as an inkjet head, a paper feed mechanism, and the like, and a printer controller 3. The printer controller 3 includes a printer mechanism controller 4 that controls the printer mechanism 2, a CPU 5, a ROM 6 that stores a program that runs on the CPU 5, a host device such as a personal computer (PC) 9, and an appropriate medium such as a LAN. It includes an interface 7 for connection by an interface, a serial interface such as USB, a data processing unit 10 for processing print data, and a bus 8 for connecting them. The data processing unit 10 is a data processing unit (ASIC) 11 designed by a user to perform various processes necessary for generating data for printing such as data decompression / decompression, color conversion, and error diffusion. And a memory (DRAM) 12 that provides a working data storage area, and a memory controller (DRAM controller) 13 that controls input / output between the ASIC 11 and the DRAM 12. The memory controller 13 is mounted on the ASIC 11 and is connected to the DRAM 12 via the memory interface 14.

  The DRAM controller 13 receives a write access instruction including a write address data (write address data) and a write command, a read address data (read address data) and a read access instruction including a read command, which are supplied from the ASIC 11. It is converted into an access request for the DRAM 12 and issued. The ASIC 11 generates data to be written to the DRAM 12 by a write access command, and executes processing based on data read from the DRAM 12 by a read access command. DRAM 12 is one example of a volatile memory device that includes a large number of volatile memory cells. The DRAM 12 is an SDRAM such as DDR, DDR2, or DDR3, for example. The DRAM controller 13 further includes a refresh control unit 20 that refreshes the DRAM 12.

  FIG. 2 shows the configuration of the DRAM controller 13 in more detail. The DRAM controller 13 decodes the write access instruction φ1 and the read access instruction φ2 issued from the access control unit 18 of the ASIC 11, and issues an access request unit 28 for issuing an access request to the DRAM 12, and a refresh control unit for refreshing the DRAM 12. 20 and an arbitration unit (arbiter) 29 that arbitrates input / output to / from the DRAM 12 from these units. The access request unit 28 has a row address (row address, first address) for accessing the address data (write address data and read address data, hereinafter referred to as addresses) included in the access instructions φ1 and φ2 to the DRAM 12. ) Ar and a column address (column address, second address) Ac are divided and issued to the DRAM 12. A large number of memory cells included in the DRAM 12 are first designated by a row address Ar, for example, a memory cell of 2 kbytes, and then a column is designated by a column address Ac, whereby data is written to a predetermined memory cell. Data can be read from the memory cell.

  The access request unit 28 further writes commands to the DRAM 12 or reads data from the DRAM 12 by using commands such as a RAS (row address strobe) signal, a CAS (column address strobe) signal, and a WE (write enable) signal. The DRAM 12 is controlled using the above. The access request unit 28 includes a timing adjustment FF (flip-flop) 27 for supplying an address and data to the DRAM 12. When the access request unit 28 further receives the access commands φ1 and φ2, the access request unit 28 sends the row address Ar and the command, that is, the write command Cw and the command included in the command φ1 or φ2 to the refresh control unit 20. A read command Cr is supplied.

  The refresh control unit 20 includes a write detection unit 21 that detects a write (write) by a write command Cw, a read detection unit 22 that detects a read (read) by a read command Cr, and a row address Ar supplied together with the write command Cw. Is stored as a written row address, and a row address holding unit (row address storage unit) 23 is stored. The row address holding unit 23 includes an SRAM 23m.

  The refresh control unit 20 includes an update unit 25 that controls registration 25 a and deletion 25 d of a plurality of row addresses Ar stored in the row address holding unit 23. The registering function 25 a registers the row address Ar in the row address holding unit 23 when the write detection unit 21 detects the write command Cw. The delete function 25d detects the read command Cr by the read detection unit 22 and further deletes the row address Ar at that time from the row address holding unit 23 when the final read determination unit 24 finds that the read is the final read. . The final read determination unit 24 detects the final read by the logical product of the read command Cr and the data discard valid signal φ3 supplied from the data discard valid determination unit 19 of the ASIC 11 and becomes data that does not require refreshing after the read. Judge that.

  The final read determination unit 24 is effective for mounting an application in which a read may be repeated at the same address. On the other hand, when an application in which reading is not repeated at the same address is mounted, the final read determination unit 24 may be omitted, and the row address Ar for read access may be deleted from the row address holding unit 23. When an application where the possibility of repeated reads is not zero is mounted at the same address, a data retention determination unit is provided in the ASIC 11, and a data retention type is obtained by a logical product of a data retention signal supplied therefrom and a read command Cr. It is desirable to provide a unit that determines read access. In the case of data holding read access, it is desirable to hold the row address read-accessed from the row address holding unit 23 without deleting it.

  The refresh control unit 20 further includes a dummy read unit 30. The dummy read unit 30 includes a plurality of already-written row addresses Ar stored in the row address holding unit 23, and has no write access and read access within a refresh cycle (first time) tr that requires a refresh operation. A dummy read command Cdr for performing a dummy read is issued to the row address Ar to which access has been written. The dummy read unit 30 includes a refresh counter 31 that counts the time from the last access for each of a plurality of row addresses Ar held in the row address holding unit 23, and a dummy read unit 31 when the refresh counter 31 reaches the refresh cycle tr. And a unit (dummy read command issuing unit) 32 for issuing commands.

  When the write detection unit 21 and the read detection unit 22 detect the write command Cw or the read command Cr, the refresh counter 31 resets the count of the row address Ar. When the dummy read command Cdr is issued from the dummy read command issuing unit 32, the count of the row address Ar is reset. For example, the refresh counter 31 may count down or count up a 64 ms refresh cycle tr. Therefore, first, when there is a write access to a certain row address Ar and data is written, the counter 31 is reset. Therefore, no dummy read is performed on the row address Ar during the refresh cycle tr. If there is a read access during the refresh cycle tr, the counter 31 is reset again, so that no dummy read is performed during the subsequent refresh cycle tr.

  Since the write access, read access, and dummy read access to the DRAM 12 are not performed simultaneously, the refresh cycle tr is not counted up (counted down) for a plurality of row addresses Ar at the same time. At the same time, the dummy read command Cdr is not issued. However, there is a possibility that read access or write access and dummy read access (dummy read command) conflict, and such access conflict is adjusted by an arbitration unit (arbiter) 29.

  The refresh control unit 20 further activates the auto-refresh unit 40 that issues a predetermined number of auto-refresh commands Car within the refresh cycle (first time) tr to the DRAM 12, and the validity of the auto-refresh unit 40 and the dummy read unit 30. And a monitoring unit 50 that selects invalidity. When the auto-refresh unit 40 becomes valid, for example, an auto-refresh command Car of 8192 times / 64 ms is issued to the 512 Mbits DRAM 12.

  The monitoring unit 50 includes a register 51 in which a time (second consumption time) Tb that is lost during the refresh cycle tr due to auto-refresh is set, a register 52 in which the time required for one dummy read is set, A counter 53 that counts the number of row addresses Ar held in the address holding unit 23, and a time required for dummy reading during the refresh cycle tr according to the time of the register 52 and the count value of the counter 53 (first consumption time) And a multiplier 55 for calculating Ta. The counter 53 is incremented by one when the registration unit 25a is selected in the update unit 25, and is decremented by one when the deletion unit 25d is selected, thereby setting the number of row addresses Ar held in the row address holding unit 23 (set). Count).

  The monitoring unit 50 further includes a comparator 56. When the second consumption time Tb is smaller than the first consumption time Ta, the selection signal φs is set to “1” to control the selector 57 and output from the auto-refresh unit 40. Enable the auto-refresh command Car. On the other hand, when the first consumption time Ta is equal to or shorter than the second consumption time Tb, the comparator 56 sets the selection signal φs to “0” to control the selector 57, and from the dummy read unit 30. The output dummy read command Cdr is validated. Therefore, in the refresh control unit 20, the first consumption time Ta required for performing dummy read on the plurality of written row addresses Ar held in the row address holding unit 23 and the auto refresh unit 40 The second consumption time Tb required for auto-refreshing the DRAM 12 is compared. When the first consumption time Ta is equal to or shorter than the second consumption time Tb, the dummy read unit 30 is enabled, and the auto-refresh unit 40 Is invalid. Conversely, when the first consumption time Ta is longer than the second consumption time Tb, the dummy read unit 30 is disabled and the auto-refresh unit 40 is enabled.

  FIG. 3 is a flowchart showing the operation of the refresh control unit 20. In step 71, the presence or absence of a command is confirmed. When a command is supplied from the ASIC 11 and the write detection unit 21 detects a write in step 81, the row address Ar is registered in the row address holding unit 23 by the update unit 25 in step 82 (step (1)). Next, in step 83, the first consumption time Ta and the second consumption time Tb are calculated by the monitoring unit 50, and as a result of comparison in step 84, the second consumption time Tb is greater than the first consumption time Ta. If shorter, the auto refresh unit 40 is validated in step 85. Conversely, if the first consumption time Ta is the same as or shorter than the second consumption time Tb, the dummy read unit 30 is validated in step 86 (step (5)).

  When the dummy read unit 30 is selected, a dummy read command Cdr may be issued to all the row addresses Ar held in the row address holding unit 23 by write access and / or read access to the DRAM 12. There are few. Therefore, the time (first consumption time) Ta consumed by performing the dummy read is a calculated value or the maximum value, and the actual consumed time is shorter than the first consumption time Ta. On the other hand, the DRAM controller 13 does not know which row address Ar is refreshed by the auto-refresh command Car, so it is necessary to issue a predetermined number of times (second consumption time) Tb consumed by auto-refresh. The second consumption time Tb is always consumed. Therefore, when the first consumption time Ta and the second consumption time Tb are equal, the monitoring unit 50 selects the dummy read unit 30 so that the time required for refreshing is shortened.

  In step 81, when the lead detection unit 22 detects a lead, in step 87, the final lead determination unit 24 determines whether or not it is the final lead. If the detected read is the final read, the data in the DRAM 12 at the read address may be discarded after being read, so there is no need for refresh. Accordingly, in step 88, the row address Ar held in the row address holding unit 23 is deleted (erased) by the update unit 25 (step (3)). In the case of an application in which reading may be repeated at the same address without determining the final read, the corresponding row address Ar may be deleted by read access. On the other hand, when the frequency of rereading is low, it is determined that the data holding read access is performed, and in the case of data holding read access, the row address read-accessed from the row address holding unit 23 is not deleted. You may make it hold | maintain.

  In step 81, access to the DRAM 12 occurs both when a write is detected and when a read is detected. Accordingly, the refresh counter 31 is reset at step 76. Thus, when the dummy read unit 30 is enabled, the dummy read command Cdr is not issued to the row address Ar unless the refresh cycle tr has elapsed since the last access. That is, among the plurality of already written row addresses Ar held in the row address holding unit 23, write access and read access are performed within a cycle (in time) of a refresh cycle (first time) tr that requires a refresh operation. A dummy read command Cdr for performing a dummy read is issued only to a non-accessed, written row address Ar (step (2)). Therefore, a decrease in the transfer rate of the DRAM 12 due to refresh can be suppressed.

  If no command is detected in step 71, in step 72, if the dummy read unit 30 is enabled by the selector 57, it is determined in step 74 whether or not the refresh counter 31 has been counted up. If the refresh cycle tr has elapsed according to the count of the refresh counter 31, in step 75, a dummy read command Cdr is issued from the dummy read unit 30 to the row address Ar that requires refresh. A dummy read command Cdr is issued to the row address Ar that has been write-accessed and the data has not been discarded when the refresh cycle tr elapses. Therefore, data that is written to the DRAM 12 by the dummy read and may be read later is effectively held.

  If the auto-refresh unit 40 is selected in step 72, an auto-refresh command Car is issued from the auto-refresh unit 40 at a predetermined timing in step 73 (step (4)). Therefore, data that may be written to the DRAM 12 and read later by the auto refresh is effectively held. Further, in the refresh control unit 20, even if the time consumed for refresh during the refresh cycle tr may be shortened by selecting the dummy read unit 30, the time consumed by refresh is reduced. The time Tb consumed by auto refresh is not exceeded at the maximum.

  As described above, by adopting the refresh control unit 20, when the amount of data written in the DRAM 12 is not so large, it is not necessary to issue the auto-refresh command Car to the DRAM 12, and the DRAM 12 by executing auto-refresh. It is possible to suppress a decrease in the transfer rate. For example, when auto refresh is performed, a time (waste time) in which the DRAM 12 of 1.15 ms (8192 times × 140 ns) cannot be accessed is generated during a refresh cycle tr of 64 ms. Generation can be suppressed.

  Further, the refresh control unit 20 refreshes the minimum necessary cells (row addresses) among the memory cells of the DRAM 12 by constantly updating the row address Ar to be subjected to dummy reading. Therefore, when the ASIC 11 is executing an application that uses the DRAM 12 locally like a cache and frequently repeats write access and read access, the dummy read command Cdr can also be suppressed. Therefore, it is possible to further suppress a decrease in transfer rate caused by refreshing the DRAM 12. In the best case, the dummy read command Cdr for refresh is not issued, and the time consumed for refreshing the DRAM 12 can be made zero.

  When the frequency of issuing the dummy read command Cdr is low, the arbitration unit 29 can prioritize read access or write access. Therefore, even if the dummy read command Cdr is issued, the dummy read is executed in a period in which no DRAM access occurs, so that the transfer rate is prevented from being lowered or the transfer rate is not lowered. It becomes possible to do.

  On the other hand, when the number of row addresses for issuing dummy reads increases to several tens of thousands, it is conceivable that the transfer rate decreases more than the auto refresh command control. In the refresh control unit 20, the monitoring unit 50 constantly monitors the refresh cycle consumption time Ta by dummy read, and automatically switches to auto refresh command control when the consumption time becomes longer. Therefore, the refresh time does not become longer than the consumption time Tb by the auto refresh command. For this reason, even if the refresh by dummy read is employed, the transfer rate when the auto refresh command control is employed is secured.

  In the above example, the cycle for issuing the dummy read is monitored by counting by the refresh counter 31, but various well-known methods can be employed for the refresh cycle monitoring means. The data processing unit 10 is not limited to the ASIC 11, and may be a general-purpose type processor or microcomputer. Further, the volatile memory device to be refreshed by the refresh control unit is not limited to the DRAM, but can be applied to other memories requiring refresh. In the above description, the printer and the printer controller are described as examples. However, the present invention can also be applied to memory control in a computer and other information terminals.

FIG. 2 is a block diagram illustrating a schematic configuration of a printer. It is a block diagram which shows the structure of a DRAM controller. It is a flowchart which shows operation | movement of a refresh control unit.

Explanation of symbols

10 data processing device, 11 ASIC, 12 DRAM
13 DRAM controller 20 Refresh control unit

Claims (10)

A first address storage for holding a plurality of written first addresses that have been write-accessed to a volatile memory device including a large number of memory cells accessible by address data including a first address and a second address And
A dummy read command for performing a dummy read on an unaccessed written first address that does not have a write access and a read access within a first time requiring a refresh operation among the plurality of written first addresses. A dummy lead unit that issues
An update unit for erasing, from the first address storage unit, a written first address that has been read-accessed among the plurality of written first addresses ;
An auto-refresh unit that issues a predetermined number of auto-refresh commands within the first time to the volatile memory device;
The volatile memory device is auto-refreshed by a first consumption time required for performing a dummy read on the plurality of written first addresses held in the first address storage unit and the auto-refresh unit. And comparing the second consumption time required for the operation, when the first consumption time is equal to or shorter than the second consumption time, the dummy read unit is enabled, the auto-refresh unit is disabled, And a monitoring unit that disables the dummy read unit and enables the auto-refresh unit when the consumption time of one is longer than the second consumption time .   2. The update unit according to claim 1, wherein the update unit includes a function of determining that the read access is a final read access, and only the first written address where the final read access has been performed is the first address. A refresh control device for erasing from the address storage unit.   2. The update unit according to claim 1, wherein the update unit includes a function of determining that the read access is a data holding type read access for ensuring re-reading for the same address, and the data holding type read access is performed. The refresh control device, wherein the written first address is held in the first address storage unit. In any one of claims 1 to 3, wherein the volatile memory device is a DRAM, the first address is a row address, the refresh controller. A refresh control device according to any one of claims 1 to 4 ,
An access request for issuing an access request to the volatile memory device based on a write access instruction including address data and a write command for writing to the volatile memory device, or a read access command including a read address data and a read command A memory control device comprising: an access request unit for supplying the write address data and the read address data to the refresh control device. 6. The memory control device according to claim 5 , further comprising an arbitration unit that arbitrates access to the volatile memory device by the access request and the dummy read command. A memory control device according to claim 5 or 6 ,
A volatile memory device controlled by the memory control device;
A data processing device comprising: a data processing unit for generating data to be written to the volatile memory device by the write access command and executing processing by data read from the volatile memory device by the read access command. A plurality of written first addresses that have been write-accessed to a volatile memory device including a large number of memory cells that can be accessed by address data including the first address and the second address are stored in a first address storage unit. Holding,
A dummy read command for performing a dummy read on an unaccessed written first address that does not have a write access and a read access within a first time requiring a refresh operation among the plurality of written first addresses. And issuing
Erasing, from the first address storage unit, a written first address that has been read-accessed among the plurality of written first addresses ;
Issuing a predetermined number of auto-refresh commands to the volatile memory device within the first time;
The volatile memory device is auto-refreshed by a first consumption time required for performing a dummy read on the plurality of written first addresses held in the first address storage unit and the auto-refresh command. A second consumption time required for the first consumption time is compared, and when the first consumption time is equal to or shorter than the second consumption time, the dummy read command is selected and the first consumption time is selected. And selecting to issue the auto-refresh command when the time is longer than the second consumption time . 9. The erasing according to claim 8 , wherein the erasing includes determining that the read access is a final read access, and only writing the first address that has been subjected to the final read access. Erasing from the address storage unit. 9. The erasing according to claim 8 , wherein the erasing is performed by determining that the read access is a data holding type read access for re-reading the same address and the data holding type read access is performed. Holding the first written address in the first address storage unit.

Images