JP5312151B2 - Semiconductor design support apparatus, high-level synthesis method, and semiconductor design support program - Google Patents

Description

  The present invention relates to a semiconductor design support apparatus for supporting semiconductor design using high-level synthesis that automatically generates a register transfer level from an operation description, a high-level synthesis method using this apparatus, and semiconductor design support for causing a computer to function as this apparatus. It is about the program.

  In conventional semiconductor integrated circuit design, all registers included in a circuit are described in a hardware description language such as Verilog-HDL or VHDL, and a register transfer level (RTL) that describes the operation of a combinational circuit between the registers. ). By inputting this RTL to a logic synthesis tool, a semiconductor integrated circuit is designed in a process of outputting a gate level in which functions between registers are assigned to all the gates and arranging and routing them.

  However, the circuit scale integrated on the semiconductor chip is increasing due to the recent improvement in the degree of integration of the semiconductor integrated circuit, and a very long design period is required to design the RTL by handwriting. On the other hand, in recent years, a high-level synthesis (or also called behavioral synthesis) technology that automatically generates RTL from a behavioral description with a higher abstraction level than RTL has been proposed, and a high-level synthesis tool that realizes this has also been proposed. It is commercially available.

  As the language for describing the behavior, a language such as C or C ++, which is generally popular as a computer program language, is often used. In the operation description, it is possible to describe only the operation to be realized by hardware, but it is not possible to describe the concept of hardware of the semiconductor integrated circuit such as a clock, a reset, and a register. For this reason, when the behavioral description for the semiconductor integrated circuit having the same function is compared with the RTL description, the behavioral description has a smaller amount of description than the RTL description, and as a result, the design period required for the handwritten design can be shortened.

  The behavioral description describes the specification of behavior only, and does not describe the specification about the implementation. However, due to general restrictions in high-level synthesis, the resulting implementation may be affected depending on the description method of the behavioral description. is there. In the behavioral description, the syntax of the array is used in order to efficiently use a collective storage area from the program. The array used in the behavioral description represents the storage elements required in the described algorithm. Even in high-level synthesis, arrays are generally assigned to storage elements such as memories and registers. Furthermore, the array is often described in a large size, and in this case, even in high-level synthesis, the array is directly assigned to a storage element of a large size.

  As a memory element allocated in a semiconductor integrated circuit, a register is first given, but the circuit area of the register is not efficient for securing a large memory area. Memory elements such as SRAM have high area efficiency, but the number of parallel address decoders that read and write individual elements in the storage area is limited. High semiconductor integrated circuit cannot be obtained.

  On the other hand, in the computer program described on the premise of the abundant memory resources mounted on the computer, it is not necessary to consider the arrangement restrictions as described above. However, if the behavioral description for high-level synthesis is based on such a computer program, the allocation of the array to the hardware in high-level synthesis may be limited in area or performance, and the desired circuit size or performance may not be obtained. There is.

  As a conventional technique for solving the above problem, a method of analyzing a control data flow flag obtained from a behavioral description in a high-level synthesis stage, and integrating a plurality of array variables to generate a circuit that can reduce the area and operate at high speed Has been proposed (see, for example, Patent Document 1).

  In the behavioral description, it is not always necessary to describe the implementation in consideration, so it is possible to describe an array variable that is not essential for the behavioral description. For example, the array variables as described above may be described in order to improve the observability during debugging.

JP 2005-346290 A

  In the conventional method disclosed in Patent Document 1, processing dependency of a plurality of array variables included in the behavioral description is analyzed from a control data flow graph used for high-level synthesis processing. In this case, array variables that are not essential for the behavioral description are also integrated with other array variables that are essential for the behavioral description, so that there is a possibility that the area efficiency is increased to some extent and the processing performance is prevented from being lowered.

  However, if an array is described in the input description, an assignment to a storage element always occurs. Therefore, an array that is not indispensable for the behavioral description is mounted as a storage element. In order to prevent the generation of a storage element due to such an unnecessary array variable, from the array variables that are generally used in the behavioral description, find the one corresponding to the unnecessary array variable, and further, the array It was necessary to manually correct the behavior description so that the variables were not used and the behavior specifications were maintained.

  It is very difficult and time-consuming to manually correct the behavioral description, and it is practically impossible particularly in a large-scale semiconductor integrated circuit. For this reason, in a large-scale semiconductor integrated circuit, generation of a memory element due to an unnecessary array variable cannot be prevented, resulting in an increase in circuit area and a decrease in processing performance.

  In addition, since the method disclosed in Patent Document 1 is performed on the analysis result during the high-level synthesis process, when using a commercially available high-level synthesis tool, as one function of the high-level synthesis tool There was a problem that it could not be easily implemented unless the technique to be implemented was built in.

  The present invention has been made to solve the above-described problems. When designing a semiconductor using a high-level synthesis tool, the high-level synthesis tool provides a desired level of high-level synthesis regardless of whether the high-level synthesis tool is a commercially available tool or an in-house tool. An object is to obtain a semiconductor design support apparatus capable of designing a semiconductor integrated circuit having a circuit size and performance, a high-level synthesis method using this apparatus, and a semiconductor design support program for causing a computer to function as this apparatus.

The semiconductor design support apparatus according to the present invention inputs an operation description describing the operation of a design circuit to be subjected to high-level synthesis, extracts all array variables included in the input operation description , and extracts the operation from the array variable. An array in which all three conditions are satisfied in the description: there is only one write location, there is a write array variable name, and the variable that appears in the write operation expression is only the subscript variable of the array. A processing unit that detects a variable as an array variable to be reduced and converts the behavior description into an operation description that does not use an array corresponding to the array variable to be reduced is provided.

According to the present invention, an operation description that describes the operation of a design circuit that is a target of high-level synthesis is input, all array variables included in the input operation description are extracted, The array variable to be reduced is an array variable for which all three conditions are satisfied, that is, that there is one place, the write array variable name exists, and that the variable that appears in the write operation expression is only the subscript variable of the array This is detected as a variable, and the behavioral description is converted into a behavioral description that does not use the array corresponding to the array variable to be reduced.
With this configuration, a behavioral description without a reducible sequence can be obtained. Therefore, by performing high-level synthesis using the behavioral description, unnecessary array variables can be created compared to the result of high-level synthesis based on the behavioral description before conversion. The resulting area and timing restrictions are relaxed, and as a result, a circuit with a small area or a circuit with high processing performance can be obtained. In addition, since the above-described behavioral description conversion is executed as preprocessing for high-level synthesis, the above-described effects can be easily obtained when used with any high-level synthesis tool including commercially available high-level synthesis tools.

It is a block diagram which shows the structure of the high-level synthesis system using the semiconductor design support apparatus by Embodiment 1 of this invention. It is a figure which shows an example of the array variable table stored in the memory | storage part in FIG. It is a figure which shows an example of the action description hold | maintained at the file recording part in FIG. It is a flowchart which shows the flow of operation | movement of the high-level synthesis system in FIG. It is a figure which shows the arrangement | sequence variable table which performed the arrangement | sequence list processing. It is a figure which shows the array variable table at the time of performing the list | wrist of array access to operation | movement description. It is a figure which shows the operation | movement description after description conversion.

Embodiment 1 FIG.
FIG. 1 is a block diagram showing a configuration of a high-level synthesis system using a semiconductor design support apparatus according to Embodiment 1 of the present invention, and shows a high-level synthesis system using a semiconductor design support apparatus according to the present invention. In FIG. 1, the high-level synthesis system 1 includes a semiconductor design support apparatus 2 and a high-level synthesis apparatus 3, and the high-level synthesis apparatus 3 executes a high-level synthesis process using the operation description processed by the semiconductor design support apparatus 2. The high-level synthesis apparatus 3 can be realized by a computer by causing a computer to execute a commercially available or in-house high-level synthesis tool, for example.

  The semiconductor design support apparatus 2 includes a processing unit 4, a storage unit 5, and a file recording unit 6. The processing unit 4 detects an array variable in which the behavior indicated in the behavior description does not change without holding data as an array variable from the behavior description to be subjected to high-level synthesis, and does not use the array variable. A means to convert to a description. The storage unit 5 is a storage unit that stores an array variable table in which data related to array variables included in the behavior description is registered in the general-purpose storage area. The file recording unit 6 is a storage unit that holds a behavioral description to be subjected to high-level synthesis as a file. The high-level synthesis apparatus 3 reads out the behavioral description and executes high-level synthesis.

  The processing unit 4 is a specific means in which hardware and software cooperate by causing a computer to read a program describing processing contents according to the spirit of the present invention and causing the computer to execute the program. It can be realized by the computer. The storage unit 5 and the file recording unit 6 can be constructed on a storage area of a storage device (for example, a hard disk device or an external storage medium) provided in the computer.

  FIG. 2 is a diagram showing an example of an array variable table stored in the storage unit in FIG. The array variable table is held in a fixed storage area of the storage unit 5 and used in processing by the processing unit 4 described later with reference to FIG. As shown in FIG. 2, in the array variable table, an entry for each line is assigned to each array included in the behavioral description. In one row of the array variable table, for example, the array variable name, all the program positions (number of rows) in which writing processing is described in the corresponding array, the array variable name when writing is performed from another array, and writing An arithmetic expression in the processing and data indicating a reading position of the corresponding array are stored.

  FIG. 3 is a diagram showing an example of the behavior description held in the file recording unit in FIG. 1, and an operation including three array variable names A, B, and C corresponding to the C language array variable syntax. A description is shown. That is, in the operation description, arrays corresponding to the array variable names A, B, and C are described, and storage elements are assigned to these arrays. Note that the behavioral description shown in FIG. 3 is an incomplete program as the behavioral description because only a part of the description necessary for explaining the program written in the C language is extracted.

Next, the operation will be described.
FIG. 4 is a flowchart showing the flow of the operation of the high-level synthesis system in FIG. 1, and will be described with reference to this figure.
First, when processing is started in the semiconductor design support apparatus 2, the processing unit 4 reads out a behavior description file to be subjected to high-level synthesis from the file recording unit 6, and stores all array variable names included in the behavior description. 5 is written into the array variable table 5 (step ST1; array listing). In the behavioral description shown in FIG. 3, array variable names A, B, and C are extracted and written for each row of the array variable table as shown in FIG.

  When the array listing is completed, the processing unit 4 separates all the program positions (number of rows) in which the writing process is described from the operation description into the corresponding array for each array of the array variable table. When an array is written from, the array variable name of the array, the arithmetic expression in the writing process, and the read position of the corresponding array are searched and extracted, and written to the array variable table (step ST2; array access list) ).

  In the behavioral description shown in FIG. 3, the place where the array variable name B is written is the description on the fifth line where the array variable name B array appears on the left side of the assignment operator (=). Therefore, “5” indicating the fifth line is written in “write location” of the array variable name B corresponding to the second line of the array variable table shown in FIG. In FIG. 3, the write operation expression for the array of array variable name B includes another array of array variable name A. Therefore, “write array variable name” of array variable name B of the array variable table shown in FIG. , “A” is written.

  Also, as shown in FIG. 3, since the write operation expression for the array of array variable name B is B [j] = funcb (A [j]), the array variable name B of the array variable table shown in FIG. In the “write operation expression”, the operation expression is written. Further, in the behavioral description shown in FIG. 3, the portion where the array of the array variable name B is read is the ninth line in which the arithmetic expression C [k] = funcc (B [k]) is described. For this reason, “8” is written in the “read location” of the array variable name B in the array variable table shown in FIG.

  For the array variables A and C registered in other rows in the array variable table shown in FIG. 5, the same processing is performed to complete the array access listing process, so that the array variable table in the state shown in FIG. Is obtained. The processing so far is automatically performed by the processing unit 4.

  The processing unit 4 performs the evaluation based on a predetermined determination condition for each row of the array variable table subjected to the array access list processing, thereby indicating the operation description without storing the data as an array variable. An array variable whose operation is not changed is detected, and it is determined that the array can be reduced (step ST3; array reduction determination). There are three conditions for the judgment condition: there are one write location, the existence of a write array variable name, and the only variable that appears in the write arithmetic expression is an array subscript variable. An array variable for which all of these are satisfied can be reduced.

  In the array variable table shown in FIG. 6, since the “write array variable name” is “not applicable” for the array variable name A, the above determination condition is not met and the array variable name A is not a target for array reduction. Also, for the array variable name C, the “reading location” is “not applicable”, and therefore is not a target for array reduction. On the other hand, the array variable name B is one place where the “write location” is “5”, the “write array variable name” exists (A), and the variable appearing in the “write operation expression” is Only j, which is a subscript variable, matches all the determination conditions, so it is determined that the arrangement can be reduced.

  When the array reduction determination is completed, the processing unit 4 converts the description according to a predetermined conversion rule so that the operation description does not use the array variable determined to be capable of array reduction while maintaining the operation content (step ST4). ; Description conversion). As a conversion rule, first, the description of “write location” corresponding to the array variable name that can be reduced in the array conversion table is deleted. For an arithmetic expression in which the array reference subscript in the array described in “Write arithmetic expression” is the only variable, convert it to a function definition in which the array subscript is replaced with an argument as it is and insert it into the behavior description. . Further, in the “read location”, the reading of the array corresponding to the operation description is converted into the function call of the newly inserted function (the function in which the array subscript is replaced with the argument as it is).

  Since “5” as shown in FIG. 6 is recorded in the “write location” of the array variable name B determined that the array can be reduced from the behavioral description shown in FIG. Delete the expression in the fifth line of the behavior description shown In this behavioral description, if the expression on the 5th line is deleted, there is no executable statement for the for loop starting from the 4th line, and there is no need to leave a description of the loop, so the for loop from the 4th line to the 6th line is deleted. Is done. Note that if an executable statement other than “write location” is included in the loop, the entire loop cannot be deleted.

  Next, the processing unit 4 defines a new function that takes j as an argument and returns a result of executing a write operation expression (assignment statement) in which only the subscript variable j of the array is a variable. Here, the new function name is named funcB. Furthermore, the reading description of the array with the array variable name B existing in the ninth line corresponding to the “reading location” is converted into a function call of the newly defined function funcB. The result of converting the behavioral description shown in FIG. 3 is the behavioral description shown in FIG. In FIG. 7, the sentence is not deleted and invalidated by commenting out.

  The high-level synthesis apparatus 3 reads out the behavioral description subjected to the processing from step ST1 to step ST4 from the file recording unit 6 and executes the high-level synthesis processing (step ST5; high-level synthesis). Even in the case where there is an array that is determined to be able to reduce the sequence in the behavioral description subject to high-level synthesis, the behavioral description after the description conversion in step ST4 has the same operation content as the original behavioral description. The number of sequences is reduced while maintaining.

  In high-level synthesis, the array included in the behavioral description is assigned to the storage element, so the area of the storage element or the number of access cycles to the storage element such as a memory or a register file is a major limitation of the circuit realized as a result of the high-level synthesis. It becomes. On the other hand, in the first embodiment, it is possible to reduce the restriction on the area or the number of cycles in high-level synthesis by reducing the number of arrays as described above. Therefore, it is possible to generate a circuit having a smaller area or a semiconductor integrated circuit having a smaller number of execution cycles.

  As described above, according to the first embodiment, an array variable that can be reduced in terms of operation is extracted from the array variables described in the behavior description, and the array variable is changed so that the operation content of the behavior description does not change. It is possible to obtain a behavioral description without a reducible sequence by performing description conversion for reducing the above. Also, by performing high-level synthesis using the converted behavioral description as an input for high-level synthesis, compared to the result of high-level synthesis using the behavioral description before conversion as input, the area and timing caused by unnecessary array variables The restriction is relaxed, and as a result, a circuit with a small area or a circuit with high processing performance can be obtained.

  In addition, the effect of the above-described reduction of array variables on high-level synthesis (behavioral synthesis) can be applied to a general high-level synthesis technique. Furthermore, since the process (steps ST1 to ST4) relating to the behavioral description conversion performed by the processing unit 4 is executed before the high-level synthesis process (step ST5) by the high-level synthesis device 3, a commercially available high-level synthesis tool is used. The above effects can be easily obtained by using with any high-level synthesis tool including

  In the first embodiment, the case where the behavioral description is written in C language is shown for convenience, but the gist of the present invention is not limited to a specific programming language. Therefore, the present invention can be similarly applied to a language used as an operation description input to high-level synthesis such as C ++, SystemC, and SystemVerilog.

  In the first embodiment, the case where the array variable table as shown in FIG. 2 is stored in the general-purpose storage area of the storage unit 5 has been described. However, in order to execute processing at higher speed, the array variable table is stored in the semiconductor. You may store in SRAM etc. which become an exclusive storage area in the design support apparatus 2. FIG.

  Furthermore, in the first embodiment, when the array variable table shown in FIG. 2 is created, as shown in FIG. 4, two processes, namely, the array listing in step ST1 and the array access listing in step ST2 are performed. However, it is not always necessary to divide into two processes, and step merging or division may be performed according to the convenience of the process implementation.

  Furthermore, in the first embodiment, the case where the semiconductor design support apparatus 2 is realized by causing the computer to execute the program describing the operation shown in FIG. 4 has been described. The contents and characteristics of the present invention are not dependent on the computer architecture or the like on which the program is executed.

  1 High-level synthesis system 2 Semiconductor design support device 3 High-level synthesis device 4 Processing unit 5 Storage unit 6 File recording unit

Claims (6)

An operation description that describes the operation of the design circuit that is the target of high-level synthesis is input, all array variables included in the input operation description are extracted, and there is one write location in the operation description from the array variable. The array variable for which all three conditions are satisfied is detected as the array variable to be reduced, that the write array variable name exists, and that the variable that appears in the write operation expression is only the subscript variable of the array. , semiconductor design support apparatus comprising a processing unit for converting the operation described in the non behavioral description using the sequence corresponding to the array variables of the reduction target. In the description of the array variable to be reduced in the operation description, the processing unit converts the write data arithmetic expression that uses only the array reference subscript variable as a function definition that replaces the subscript variable with an argument. The semiconductor design support apparatus according to claim 1 . In the description of the array variable to be reduced in the behavioral description, the processing unit converts the arithmetic expression of the read data of the array variable to be reduced into a function call of a function in which the array reference subscript variable is replaced with an argument. The semiconductor design support apparatus according to claim 2 . The processing unit generates an array variable table that lists the array variables included in the operation description and the description contents of the array variable in the operation description, and detects the array variable to be reduced with reference to the array variable table semiconductor design supporting apparatus according to any one of claims 1 to 3, characterized in that. In the high-level synthesis method using the semiconductor design support device according to any one of claims 1 to 4 ,
The processing unit extracts all array variables included in the input behavior description, and from the array variable, in the behavior description, there is one write location, the presence of a write array variable name, and a write operation. An array variable that satisfies all the three conditions that the variable that appears in the expression is only an array subscript variable is detected as an array variable to be reduced, and the operation description is an array corresponding to the array variable to be reduced Converting to a behavioral description that does not use
A high-level synthesis method comprising: a high-level synthesis apparatus including the step of inputting the behavioral description converted in the step and executing high-level synthesis. Semiconductor design support program for causing a computer to function claims 1 as semiconductor design supporting apparatus according to any one of claims 4.

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