JP5314949B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device including a MOS transistor requiring high driving capability and a method for manufacturing the same.

MOS transistors are electronic elements that play a central role in electronic technology, and miniaturization and high drive capability of MOS transistors are important. One method for increasing the driving capability of a MOS transistor is to increase the gate width to reduce the on-resistance. However, if the gate width is increased, there is a problem that the area occupied by the MOS transistor increases. In order to solve this problem, a technique for widening the gate width while suppressing an increase in the area occupied by the MOS transistor having the lateral MOS structure has been proposed. (For example, see Patent Document 1)
Hereinafter, a conventional semiconductor device will be described with reference to FIG. 4A, the trench structure 3 is provided in the well 11, and the gate electrode 7 is provided inside the trench portion having the trench structure via the gate insulating film 6 and on the upper surface of the planar portion where the trench is not formed. Formed. In the surface portion of the well 11, a source region 9 is provided on one side of the gate electrode 7, and a drain region 10 is provided on the other side. FIG. 4B is a cross-sectional view taken along the line AA in FIG. 4A and shows a planar portion. FIG. 4C is a cross-sectional view taken along the line BB in FIG. 4A, and is a cross-sectional view in a direction perpendicular to the channel. As shown in the BB cross-sectional view, since the gate electrode 7 is formed inside the trench portion 3, the total length of the curve formed by the gate insulating film 6 located under the gate electrode 7 is increased. This is the gate width.

As described above, in this technique, the effective gate width can be increased with respect to the length of the gate electrode 7 on the surface by forming the gate portion into a trench structure having a convex portion and a concave portion. Thus, the on-resistance per unit area can be reduced without lowering the breakdown voltage of the MOS transistor.
JP 2006-49826 A

  In the structure of the semiconductor device described above, there has been a problem that the driving ability cannot actually be obtained as expected. It has been found that the driving ability varies depending on the gate length, and that the driving ability tends to decrease as the gate length becomes shorter.

  This is a channel in which a large amount of current flows through the path A shown in FIG. 4D (planar part where the trench part 3 is not formed) among the channels generated between the source and the drain and connects the source and the drain. It can be inferred that the current does not flow so much in the path B flowing through the side surface of the trench portion 8 parallel to the bottom surface and the path C flowing through the bottom surface of the trench portion 8. For this reason, the shorter the gate length, the more the current is concentrated in the path A, which is considered to be the cause of the decrease in driving capability when the gate length is shortened.

  An object of the present invention is to improve the driving capability of a semiconductor device having a trench structure.

  In order to solve the above problems, the present invention uses the following means.

  (1) A trench structure formed in the first conductivity type semiconductor substrate, the depth of which varies intermittently in the gate width direction, and the inside of the trench portion and the upper surface of the planar portion defined by the trench structure via a gate insulating film A semiconductor device comprising: a gate electrode formed on the gate electrode; a second conductivity type source region formed on one side of the gate electrode; and a second conductivity type drain region formed on the other side of the gate electrode. In the device, a portion of the source region and the drain region facing each other across the trench portion has a depth reaching the same as or more than a bottom portion from an upper surface of the trench structure. .

  (2) A first conductivity type semiconductor substrate, a source region and a drain region of a second conductivity type that are spaced apart in the vicinity of the surface of the first conductivity type semiconductor substrate, and the source region and the drain region. A planar planar portion serving as the first channel region, a trench portion having a certain depth, the side surface and the bottom surface of which are disposed along the planar portion serving as the second channel region, and the planar portion. Part and a gate insulating film provided on the surface of the trench part, and a gate electrode provided on the gate insulating film, wherein the source region and the drain region through the trench part The depth of the diffusion region of the portion facing each other has a depth reaching the same as or more than the bottom from the top surface of the trench structure It was.

  Preparing a semiconductor substrate, removing a part of a region to be a channel region of the semiconductor substrate from the surface to the inside, forming a trench having a side surface and a bottom surface, and arranging a planar portion and a trench portion; A step of forming an oxide film on the surface of the trench portion and the planar portion, a step of applying a resist material, and patterning so that impurities can be introduced from the top surface to the bottom surface in the direction of the source region and drain region of the trench, and the semiconductor A step of ion-implanting impurities forming the first source region and the drain region while rotating the substrate; a step of removing the resist material and the oxide film to form a gate insulating film; and depositing polycrystalline silicon A step of forming a gate electrode, and a second source region and a drain region sandwiching the gate electrode And to the method for manufacturing the semiconductor device comprising the steps of forming.

  According to the present invention, in a part of the source region and the drain region of the semiconductor device described above, a photoresist film is applied and patterned on the trench portion before forming the gate electrode, and ion implantation is performed so that the trench portion is formed from the top surface to the bottom portion. It is possible to form a deeply diffused region. As a result, since the source region and the drain region are formed to a deep position with respect to the gate electrode of the trench transistor, the current concentration on the upper portion of the recess whose depth changes intermittently in the gate width direction is reduced. Since the current can also flow through the side surface and the bottom surface of the trench portion, the driving capability of the semiconductor device can be improved.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a flow chart in order of steps according to a schematic cross-sectional view showing a first embodiment of a method of manufacturing a semiconductor device of the present invention.

  FIG. 1A shows a first oxide semiconductor substrate, for example, a P-type semiconductor substrate 1 having an impurity concentration of 20 Ωcm to 30 Ωcm doped with boron, for example, as a thick oxide film 2 by a LOCOS method. A thermal oxide film having a thickness of 500 nm to 1 μm is formed in a desired region. The conductivity type of the substrate is not related to the essence of the present invention. Subsequently, as shown in FIG. 1B, the trench structure 3 is formed in the first conductivity type semiconductor substrate to a depth of, for example, several hundred nm to several μm. Only one groove-like recess forming the trench structure 3 may be arranged, or a plurality of grooves may be arranged side by side in a direction perpendicular to the drawing sheet. Thereafter, an oxide film 4 is formed with a film thickness of, for example, several hundreds of parts including and on the surface of the semiconductor substrate constituting the inside of the trench structure 3.

After that, as shown in FIG. 1C, a resist film 5 is applied, and as shown in FIG. 1D, the impurity addition to the source region and the drain region is the same as the top surface to the bottom surface of the trench structure 3. The resist film 5 in the source and drain regions is patterned to remove unnecessary portions so that it can be formed deeply as described above. Instead of the resist film here, it is also possible to perform patterning using a nitride film or a polycrystalline silicon film as a mask. Thereafter, as shown in FIG. 1E, as the impurity, for example, arsenic is preferably ion-implanted while spinning (rotating) the wafer at a dose of 1 × 10 ¹³ atoms / cm ² to 1 × 10 ¹⁶ atoms / cm ^2. To do.

  This process will be described in detail with reference to FIG. 2A and 2B are schematic views showing an ion implantation process into the trench structure of FIG. 1E, FIG. 2A shows the source region side, and FIG. It shows the drain region side when the wafer is rotated 180 °. As shown in FIG. 2A, impurities are added from the side surface to the bottom surface of the trench structure 3, and while the wafer is spun (rotated), ion implantation is performed at a low ion implantation incident angle. As shown in B), impurities can be added from the side to the bottom of the drain region located on the opposite side of the resist film 5 on the source region side. Further, FIG. 3A is a top view of FIG. 1E, and FIG. 1E is a cross-sectional view of the AA portion shown in FIG. Thereafter, the resist film 5 and the oxide film 4 are removed.

  Next, as shown in FIG. 1F, after forming the gate insulating film 6 with a thermal oxide film having a film thickness of, for example, 10 to several hundred nm, a polycrystalline silicon gate film is preferably formed on the gate insulating film 6. A film thickness of 100 nm to 500 nm is deposited, and an impurity is introduced by predeposition or ion implantation to form a gate electrode 7. Here, the impurity added by ion implantation is diffused and activated in the same manner as the formation of the gate insulating film 6 which is a thermal oxide film. In this step, both the diffused source region 9 and drain region 10 diffuse to a deep position from the top surface of the trench structure 3 to the same as or more than the bottom portion. Further, here, when the impurity addition by the above-described ion implantation is high concentration, the thermal oxide film becomes thick on the surface of each of the source region 9 and the drain region 10, so that the capacity between the gate and the drain is automatically reduced. Is possible.

On the other hand, by patterning the gate electrode 10 with the resist film 8, the structure as shown in FIG. Subsequently, as shown in FIG. 1G, impurities are added to the gate electrode 10 for forming a source region and a drain region by a self-alignment method. For example, arsenic is preferably ion-implanted at a dose of 1 × 10 ¹⁵ atoms / cm ² to 1 × 10 ¹⁶ atoms / cm ² . Up to this step, the form of the MOS transistor having the trench structure 3 is completed. After that, heat treatment is performed at 800 ° C. to 1000 ° C. for several hours, so that the source region 9 and the drain region 10 are formed as illustrated in FIG.

  Further, as the second embodiment, the impurity addition of the source region 9 and the drain region 10 for forming deeply from the top surface to the bottom of the trench structure 3 as described above or after the gate insulating film 6 is formed. It is possible to do.

  A plan view of the semiconductor device obtained in the first embodiment or the second embodiment up to the above is as shown in FIG. 3A is a cross-sectional view taken along the line AA in FIG. 3B, and FIG. 3D is a cross-sectional view taken along the line BB in FIG. 3C, in the trench transistor 12 having the trench structure 3, the source region 9 and the drain region 10 near the gate electrode 7 are formed from the top surface of the trench structure 3 to the same or deeper than the bottom portion, From FIG. 3D, the planar transistor 13 is formed to have the same depth in the entire source region 9 and drain region 10 even in the vicinity of the gate electrode 7.

  FIG. 5 is a schematic plan view of the semiconductor device obtained in the third embodiment. The difference from FIG. 3B is the position of the contact on the surface of the source region and the drain region. In FIG. 3B, the trench contact and the planar contact are arranged in a line, but in this embodiment, the planar contact 15 has a distance from the gate electrode 7 to reduce the parasitic resistance. The distance was shorter than the distance between the contact 14 and the gate electrode.

  As described above, in the present invention, in the trench transistor 12 having a trench structure, the depth is intermittently changed in the gate width direction by deepening from the top surface of the trench portion 3 to the same as or more than the bottom portion. Current concentration on the upper part can be alleviated, and the current can be allowed to flow also to the side and bottom surfaces of the trench part, so that the driving capability of the semiconductor device can be improved.

It is a typical sectional view flow showing the 1st example of the present invention. It is a schematic diagram of the ion implantation process in the schematic cross-sectional view flow showing the first embodiment. It is the cross-sectional schematic diagram and plane schematic diagram of the semiconductor device obtained by the 1st Example and the 2nd Example. It is sectional drawing and a schematic diagram which show a prior art and its subject. It is a plane schematic diagram of the semiconductor device obtained by the 3rd example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2, 4 Oxide film 3 Trench structure 5, 8 Resist film 6 Gate insulating film 7 Gate electrode 9 Source region 10 Drain region 11 Well 12 Trench part transistor 13 Planar part transistor 14 Trench part contact 15 Planar part contact

Claims (4)

Preparing a semiconductor substrate; and
Removing a part of a region to be a channel region of the semiconductor substrate from the surface to the inside, forming a trench having a side surface and a bottom surface, and arranging a planar portion and a trench portion;
Forming an oxide film on the surfaces of the trench part and the planar part;
Applying a resist material and patterning so that impurities can be introduced from the top surface to the bottom surface in the direction of the source and drain regions of the trench; and
Ion-implanting impurities forming the first source region and the drain region while rotating the semiconductor substrate;
Removing the resist material and the oxide film to form a gate insulating film;
Forming a gate electrode after forming the gate insulating film and depositing polycrystalline silicon;
Forming a second source region and a drain region with the gate electrode interposed therebetween. The first source region and the drain region formed from the top surface to the bottom of the trench portion are ion-implanted at a dose of 1 × 10 ¹³ atoms / cm ² to 1 × 10 ¹⁶ atoms / cm ^2. A method for manufacturing a semiconductor device according to claim 1 . Impurity diffusion and activation of the first source region and a drain region formed over the bottom of the trench portion upper surface, a semiconductor according to claim 1, characterized in that it is carried out simultaneously with the step of forming the gate insulating film Device manufacturing method. Claim 1 impurity doping process of the first source region and a drain region formed over the bottom of the trench upper surface is characterized by also be implemented in either before or after the process of forming the gate insulating film The manufacturing method of the semiconductor device as described in 2 ..

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