JP5316206B2 - Driving circuit - Google Patents

Description

  The present invention relates to a drive circuit that generates a drive signal and outputs it from an external terminal.

  Some semiconductor integrated circuits have a drive circuit that generates a drive voltage in response to a user's switch operation and outputs the drive voltage from an external terminal. This drive voltage is supplied to an external circuit connected to the external terminal, and drives the external circuit. In such a drive circuit, when the external terminal is short-circuited to the ground due to an external circuit failure or the like, the output of the drive voltage is stopped, and it is necessary to detect the short circuit.

  A system for performing short detection is described in, for example, Patent Document 1. Further, for example, Patent Document 2 discloses a circuit that performs short detection.

JP-A-8-223252 JP 2007-295800 A

  Since the drive circuit does not operate until the user performs a switch operation after turning on the power of the semiconductor integrated circuit, the voltage of the external terminal is indefinite, and there is a possibility that erroneous short-circuit detection is performed. In this case, since the operation of the drive circuit is stopped by the short circuit detection, there is a problem in that the drive signal cannot be output from the external terminal despite the user's switch operation.

  The present invention has been made in view of the above points, and an object thereof is to provide a drive circuit that prevents erroneous short-circuit detection and outputs a drive signal in accordance with an operation.

A drive circuit according to an embodiment of the present invention is a drive circuit (10) that generates a drive signal and outputs it from an external terminal (16) when a switch signal supplied from the switch circuit (12) is active.
A short detection circuit (18) that performs short detection when the voltage of the external terminal (16) is less than a reference voltage to stop the generation of the drive signal;
Said switch signal is chromatic operation control unit for operating the short-circuit detecting circuit (18) when it is active (17), a
The operation control unit (17) activates the short detection circuit (18) when the switch signal is active and the operation instruction signal supplied from the circuit (15) for monitoring and controlling the entire system is active. Make it work.

  Note that the reference numerals in the parentheses are given for ease of understanding, are merely examples, and are not limited to the illustrated modes.

  According to the present invention, it is possible to prevent erroneous short-circuit detection and to output a drive signal according to an operation.

It is a block block diagram of one Embodiment of the drive circuit using the short detection circuit of this invention. It is a circuit diagram of one embodiment of a short detection circuit. FIG. 2 is a signal waveform diagram of each part of the circuit in FIG. 1.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

<Configuration of drive circuit>
FIG. 1 is a block diagram showing an embodiment of a drive circuit according to the present invention. In FIG. 1, the drive circuit 10 is integrated in a semiconductor, and one end of an external switch SW1 is connected to the external terminal 11 of the drive circuit 10, and the other end of the switch SW1 is grounded.

  The external terminal 11 is connected to the switch circuit 12 in the drive circuit 10. The switch circuit 12 becomes a low level input when the switch SW1 is turned on, and generates a switch signal that represents active with a high level output, for example, and represents inactive with a low level output when the switch SW1 is turned off. This is supplied to the circuit 13 and the AND circuit 17. Although the switch SW1 generates a low active signal, the switch SW1 may generate a high active signal and supply it to the switch circuit 12.

  When the high-level switch signal is supplied from the switch circuit 12, the power supply circuit 13 generates a drive signal voltage of a predetermined voltage (for example, 5 V) and supplies it to the output driver 14. The output driver 14 operates only when an operation instruction signal indicating active at a high level, for example, is supplied from the monitor control circuit 15, and outputs the drive signal voltage from the power supply circuit 13 from the external terminal 16.

  The monitoring control circuit 15 performs monitoring and control of the entire system including the drive circuit 10, generates an operation instruction signal representing high-level activity when the system is normal, and supplies the operation instruction signal to the output driver 14 and the AND circuit 17. .

  When the switch signal supplied from the switch circuit 12 is active and the operation instruction signal supplied from the supervisory control circuit 15 is active, the AND circuit 17 generates an enable signal that indicates high level and indicates a short circuit. 18 is supplied.

  The short detection circuit 18 includes a comparator, and the non-inverting input terminal of the short detection circuit 18 is connected to the external terminal 16. A reference voltage Vref (for example, Vref = 0.5 V) is applied from the DC power supply 19 to the inverting input terminal of the short detection circuit 18.

  The short detection circuit 18 operates only when an enable signal indicating active is supplied from the AND circuit 17. When the voltage Vreg of the external terminal 16 is equal to or higher than the reference voltage Vref, the output terminal is set to a high impedance state, and the external terminal 16 Is less than the reference voltage Vref, a low-level short detection signal is generated and supplied to the power supply circuit 13. When the short detection circuit 18 is supplied with an enable signal indicating non-active from the AND circuit 17, the output terminal is set to a high impedance state.

  When the power supply circuit 13 is supplied with a high level switch signal from the switch circuit 12 and generates a drive signal voltage, when the low level short detection signal is supplied from the short detection circuit 18, the drive signal voltage Generation of.

  In the system using the drive circuit 10 of the present embodiment for a gas stove drive circuit, for example, the drive signal voltage output from the external terminal 16 is driven to open an actuator for opening and closing the gas control valve, For example, when the drive signal voltage is in the vicinity of 0 V, the gas control valve is closed by the restoring force of the spring and the like, and the fail safe is activated.

<Configuration of short detection circuit>
FIG. 2 shows a circuit diagram of an embodiment of the short detection circuit 18. In FIG. 2, a p-channel MOS transistor M1 and a resistor R1 are connected between a power supply Vcc and a power supply Vss to form a constant current source. The gates of the p-channel MOS transistors M2 and M3 are commonly connected to the gate and drain of the MOS transistor M1 to form a current mirror circuit. The sources of the MOS transistors M2 and M3 are connected to the power supply Vcc, and the drains are connected to the drains of the n-channel MOS transistors M4 and M5 and M3.

  The p-channel MOS transistors M4 and M5 constitute a differential circuit, and the sources of the MOS transistors M4 and M5 are connected to the power source Vcc via the current source MOS transistor M2.

  The gate of the MOS transistor M4 is connected to the terminal 21 which is a non-inverting input terminal of the short detection circuit 18, and the voltage Vreg of the external terminal 16 is supplied. The gate of the MOS transistor M5 is connected to the terminal 22 which is the inverting input terminal of the short detection circuit 18, and the reference voltage Vref is supplied from the DC power source 19. The drains of the MOS transistors M4 and M5 are connected to the drains of the n-channel MOS transistors M6 and M7, respectively.

  The gates of the MOS transistors M6 and M7 are connected in common and connected to the drain of the MOS transistor M6 to form a current mirror circuit, and the sources of the MOS transistors M6 and M7 are connected to the power supply Vss. MOS transistors M6 and M7 operate as a current source of the differential circuit.

  The drain of the MOS transistor M5 is connected to the gate of the n-channel MOS transistor M8. The drain of the MOS transistor M8 is connected to the drain of the MOS transistor M3, and the source of the MOS transistor M8 is connected to the power supply Vss. The MOS transistor M8 forms an output stage together with the MOS transistor M3.

  The drains of the MOS transistors M3 and M8 are connected to the drain of the n-channel MOS transistor M9 and the gate of the n-channel MOS transistor M10. The gate of the MOS transistor M9 is connected to the terminal 24 via the inverter 23, and the source of the MOS transistor M9 is connected to the power supply Vss. An output signal from the AND circuit 17 is supplied to the terminal 24. The MOS transistor M10 has a source connected to the power supply Vss and a drain connected to the output terminal 25.

  Here, when an enable signal (high level) indicating active is supplied from the AND circuit 17, the gate of the MOS transistor M9 becomes low level and the MOS transistor M9 is turned off. Therefore, the output of the differential circuit (M4, M5) is output from the output terminal 25 through the MOS transistors M8, M10.

  Here, when the voltage Vreg at the terminal 21 is higher than the voltage Vref at the terminal 22, the drain potential of the MOS transistor M5 is high, the drain potential of the MOS transistor M3 is low, the MOS transistor M10 is turned off, and the output terminal 25 is It becomes a high impedance state.

  When the voltage Vreg at the terminal 21 becomes lower than the voltage Vref at the terminal 22, the drain potential of the MOS transistor M5 decreases and the drain potential of the MOS transistor M3 increases. Therefore, the MOS transistor M10 is turned on and the output terminal 25 is driven to a low level. Outputs a short detection signal.

  On the other hand, when a low level representing non-active is supplied from the AND circuit 17, the MOS transistor M9 is turned on, the MOS transistor M10 is turned off, and the output terminal 25 is in a high impedance state.

  FIG. 3 is a signal waveform diagram of each part of the circuit of FIG. 3A shows the output signal of the AND circuit 17, FIG. 3B shows the voltage Vreg of the external terminal 16, and FIG. 3C shows the output of the short detection circuit 18. When the output signal of the AND circuit 17 is at a low level, the output terminal of the short detection circuit 18 is in a high impedance state. Only when the output signal of the AND circuit 17 is at a high level and the voltage Vreg of the external terminal 16 becomes 0 V, the short detection circuit 18 performs a short detection, and the output signal becomes a low level.

  As described above, the short detection circuit 18 operates only when the switch signal from the switch circuit 12 is active and the operation instruction signal from the monitoring control circuit 15 is active, and generates a short detection signal.

  That is, the short detection circuit 18 performs short detection only when the power supply circuit 13 and the output driver 14 are operating and outputting the drive signal voltage from the external terminal 16, so that erroneous short detection is performed when the drive circuit is turned on. The risk of doing so can be prevented.

  In the above embodiment, the monitor control circuit 15 is provided in the drive circuit 10, but a drive circuit without the monitor control circuit may be used. When the monitoring control circuit is not provided, the AND circuit 17 is not necessary, the short detection circuit 18 is operated when the switch signal supplied from the switch circuit 12 is active, and the short detection is performed when the switch signal is inactive. The output terminal of the circuit 18 is set to a high impedance state.

DESCRIPTION OF SYMBOLS 10 Drive circuit 11,16 External terminal 12 Switch circuit 13 Power supply circuit 14 Output driver 15 Monitor control circuit 17 AND circuit 18 Short detection circuit 23 Inverter M1-M10 MOS transistor SW1 switch

Claims (1)

A drive circuit that generates a drive signal and outputs it from an external terminal when a switch signal supplied from the switch circuit is active,
A short detection circuit that performs short detection when the voltage of the external terminal is less than a reference voltage and stops generation of the drive signal;
Have a, an operation control unit for operating the short-circuit detecting circuit when said switch signal is active,
The operation control unit operates the short detection circuit when the switch signal is active and an operation instruction signal supplied from a circuit for monitoring and controlling the entire system is active.
A drive circuit characterized by that.

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