JP5327441B2 - Pulse output device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a pulse output device for improving responsiveness on position control, and for achieving high speed and fine control by setting a new value corresponding to the next target position just until the end of the output of a stepping pulse corresponding to the previous setting. <P>SOLUTION: An output part 133-1 outputs stepping pulses necessary for reaching a target position to a stepping signal PS at pulse intervals designated by pulse interval designation data D2 on the basis of absolute position designation data D4 and pulse interval designation data D2 in response to an output instruction signal S1, and changes the logical value of a direction signal DS in association with a stepping direction necessary for reaching the target position. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

  The present invention relates to a pulse output device suitable for incorporation into, for example, a position control unit that is an element unit of a building block type PLC.

  A schematic diagram showing an application example of a building block type PLC including a position control unit is shown in FIG. In this application example, a lift device having a lift base 6 is controlled by a building block type PLC 1 including a CPU unit 11 and a position control unit 12.

  In the figure, a lifting base 6 to be subjected to position control is integrally coupled to a chain 5 wound between an upper sprocket 4a and a lower sprocket 4b, and vertically lifts as the chain 5 moves. It is possible to move up and down while being guided by the guide 7.

  The lower sprocket 4b is interlocked with the drive shaft of the motor 3, and the motor 3 is driven to rotate forward and reversely under the control of the motor drive device 2. A certain correlation is maintained between the rotation amount or rotation angle of the motor 3 and the lift amount of the lift base 6. Therefore, the height position of the elevating base 6 can be controlled in an open loop by controlling the rotation amount or the rotation angle of the motor 3 via the motor driving device 2.

  The motor driving device 2 operates to receive the step signal PS and the direction signal DS output from the position control unit 12 incorporated in the PLC 1 and rotate the motor 3 by a specified rotation amount or rotation angle. .

  The step signal PS is defined by a plurality of step pulse trains defined by a pulse number (N) and a pulse interval (T) (first step pulse trains defined by N1 and T1, N2 and T2). Second stepping pulse train, third stepping pulse train defined by N3 and T3,... Nth stepping pulse train defined by Nn and Tn) are sequentially included in series.

  The direction progression DS is a binary signal, and its logical value is the first logical value (for example, “H”) and counterclockwise (CCW) when the motor 3 is to be rotated clockwise (CW). When it is desired to do so, the second logical value (for example, “L”) is set.

  The motor rotation amount or rotation angle per step pulse included in the step signal PS is maintained constant by the motor driving device 2, and the rotation speed at that time is determined by the pulse interval (T) and is rotated. The direction is determined by the logical value of the direction signal DS, and the total rotation amount or rotation angle is determined by the number of pulses (N).

  Therefore, by controlling the number of pulses (N) and pulse interval (T) included in the step signal PS and the logical value of the direction signal DS, the rotation amount, rotation speed, and rotation direction of the motor 3 can be changed. In this way, the lifting / lowering amount, the lifting / lowering speed, and the lifting / lowering direction of the lifting / lowering base 6 can be accurately controlled.

  A block diagram showing the overall configuration of the position control unit is shown in FIG. 12, and a detailed configuration diagram of the entire PLC including the unit is shown in FIG. 13 (see, for example, Patent Document 1).

  As shown in FIG. 12, the position control unit 12 includes an MPU system 121, a pulse output ASIC 122, and an internal bus 123 that connects them. The MPU system 121 includes an MPU 121a that controls the entire system, a ROM 121b that stores a system program to be executed by the MPU 121a, and a RAM 121c that is used as a work area when the MPU 121a executes the system program. Has been. The bus interface 124 is for connecting the position control unit 12 to an inter-unit connection bus that connects the CPU unit 11.

  A detailed configuration diagram of the entire PLC including the position control unit is shown in FIG. As shown in the figure, the MPU system 121 executes a system program stored in the ROM 121b, thereby executing a command analysis processing unit P1, a unit conversion calculation processing unit P2, and a position control calculation processing unit (pulse unit). P3 and the pulse output command processing unit P4 are realized as firmware.

  Here, the command analysis processing unit P1 receives the control command received from the CPU unit 11 via the bus interface 124 (for example, “contents such as“ lift the lifting base 6 to the height Hmm ”in the lift device to be controlled”). To analyze.

  Together, the unit conversion calculation processing unit P2 and the position control calculation processing unit P3 are the target height expressed in a predetermined command unit system (mm) obtained as a result of the analysis in the command analysis processing unit P1. 14 (a), a series of speeds corresponding to each time-division instantaneous value of the speed profile from the current height to the target height are calculated as shown in FIG. 14 (a) and shown in FIG. 14 (b). As described above, a series of movement amount data expressed in a predetermined pulse unit system (number of stepping pulses) is output in time series.

  Based on a series of movement amount data output in time series from the position control calculation processing unit P3, the pulse output command processing unit P4 corresponds to the corresponding position control command data (output instruction data, pulse output number designation data, pulse interval). Designating data, direction designation data, etc.) and writing these data to the corresponding registers in the pulse output ASIC 122 constituting the pulse output device to command the output of the step signal PS and the direction signal DS. is there.

  A block diagram of a conventional pulse output ASIC is shown in FIG. As shown in the figure, the pulse output ASIC 122 includes an MPU / I / F control unit 1221, an output instruction unit 1222, and an output unit 1223.

  The MPU / I / F control unit 1221 is connected to the MPU bus 123 connected to the MPU system 121 and functions as an interface with the MPU system 121. The output instruction unit 1222 includes a register to which position control command data can be written from the MPU system 121 side via the MPU / I / F control unit 121. The output unit 1223 generates and outputs a step signal PS and a direction signal DS based on the position control command data written in the register of the output instruction unit 1222.

  The output instruction unit 1222 includes, as the registers, an output instruction register 1222a for storing output instruction data D0 (not shown), a pulse output number specifying register 1222b for storing pulse output number specifying data D1, and a pulse A pulse interval specifying register 1222c for storing the interval specifying data D2 and a direction specifying register 1222d for storing the direction specifying data D3 are included. The output instruction unit 1222 is configured to generate a predetermined output instruction signal S1 in response to the timing when the output instruction data D0 is written in the output instruction register 1222a.

  In response to the reception timing of the output instruction signal S1, the output unit 1223 sends the number of stepping pulses designated by the pulse output number designation data D1 stored in the pulse output number designation register 1222b to the pulse interval designation register 1222c. The direction signal is output in the step signal PS at the pulse interval specified by the stored pulse interval specification data D2, and in correspondence with the direction specified by the direction specification data D3 stored in the direction specification register 1222d. It is configured to change the logical value of DS.

In addition, the output unit 1223 includes a count function for generating current value data by counting the step pulses included in the step signal PS in a direction corresponding to the logical value of the direction signal DS. The current position data thus generated can be read from the MPU system 121 side via the MPU / I / F control unit 1221.
JP 2000-333909

  By the way, the pulse output command processing unit P4 (see FIG. 13) is based on the movement amount data string (see FIG. 14B) given in time series from the position control calculation processing unit P3 located in the preceding stage. The target position data and the speed data are determined one after another, and a necessary command is given to the pulse output ASIC 122 based on the determined data pairs (target position data and speed data).

  FIG. 16 shows a flowchart showing conventional MPU processing (corresponding to processing for realizing the function of the pulse output command processing unit P4) at that time.

  As shown in the figure, in this MPU process, first, as step 101, the “current position” is read from the output unit 1223 via the MPU / I / F processing unit 1221, and then as step 102, The “number of pulse outputs” is obtained from the absolute value of the difference between the read “current position” and the known “target position”.

  Next, as step 103, the “current position” and the “target position” are determined to be large and small. When “target position ≧ current position”, “CW direction designation” is set. When “target position <current position”, “CCW” As “direction designation”, “stepping direction” is obtained.

  Next, in step 104, the “pulse output number” obtained above is known to the pulse output number designation register 1222b, the pulse interval designation register 1222c, and the direction designation register 1222d via the MPU / I / F processing unit 1221. The “pulse interval” corresponding to the speed and the “stepping direction” obtained above are written.

  Finally, as step 105, the output instruction signal S1 is generated by storing the output instruction data in the output instruction register 1222a via the MPU / I / F processing unit 1221.

  However, such conventional MPU processing requires various pre-processing (steps 101, 102, 103) prior to data writing processing (steps 104, 105) for the output instruction unit 1222. When a new setting corresponding to the next target position is made during the output of the stepping pulse corresponding to the previous target position, the MPU of the MPU is changed when the output frequency of the stepping pulse becomes a high frequency (for example, about 1 MHz). Due to the relationship with the processing speed, the next setting must be completed considerably earlier than the end of the output of the stepping pulse corresponding to the previous setting (for example, about two stepping pulses). There is a problem that there is a possibility that the responsiveness is restricted and there is a risk of hindering high speed and fine control (see FIG. 17).

  The present invention has been made paying attention to the above-mentioned problems, and the object of the present invention is to reduce the load on the MPU by making the preprocessing prior to the data writing process to the output instruction unit as unnecessary as possible. Even if the step pulse corresponding to the previous target position is being output, a new setting corresponding to the next target position can be set until the end of the output of the step pulse corresponding to the previous setting. It is an object to provide a pulse output ASIC that improves the responsiveness of the device and enables high-speed and fine control.

  Still another object of the present invention is to provide a position control unit of a building block type PLC that enables high-speed and fine control by incorporating such a pulse output ASIC.

  Still other objects and operational effects of the present invention should be easily understood by those skilled in the art by referring to the following description of the specification.

  The above-mentioned [Problem to be Solved by the Invention] can be solved by a pulse output ASIC or a position control unit having the following configuration.

[Basic configuration]
That is, the pulse output device (13) of the present invention includes an MPU system (121) for generating position control command data, a step signal (PS) including a series of step pulse trains, and a logical value corresponding to the step direction. Position control command provided from the MPU system (121), which is interposed between the drive device (2) which advances a drive source such as a motor in a designated direction based on a direction signal (DS) having Based on the data, the step signal (PS) and the direction signal (DS) corresponding to the step signal are generated and output. More specifically, for example, it can be configured as a pulse output ASIC (generally a wired logic IC, but in some cases, it may be a programmable element such as an FPGA).

  That is, this pulse output device is connected to the MPU bus (123) connected to the MPU system (121) as shown in FIGS. 1, 3, 5, and 7, and is connected to the MPU system (121). MPU / I / F control unit (131) functioning as an interface between the MPU / I / F control unit (131) and the MPU system (121) side to which the position control command data can be written The output instruction unit (132) including the output signal, and the step signal (PS) and the direction signal (DS) are generated and output based on the position control command data written in the register of the output instruction unit (132). And an output unit (133).

  The output instruction unit (132), as the registers, includes an output instruction register (132a) for storing output instruction data (D0) and a pulse interval specification register (132b) for storing pulse interval specification data (D2). ) And an absolute position designation register (132c) for storing absolute position designation data (D4) representing the target position by the absolute position, and the output instruction data (D0) is written to the output instruction register In response to the determined timing, a predetermined output instruction signal (S1) is generated (132-1).

  In response to the output instruction signal (S1), the output unit (133) stores the absolute position designation data (D4) stored in the absolute position designation register (132c) and the pulse interval designation register (132b). Based on the pulse interval designation data (D2), the number of stepping pulses necessary to reach the target position designated by the absolute position designation data (D4) is represented by the pulse interval designation data (D2). Output in the step signal (PS) at a specified pulse interval, and change the logical value of the direction signal (DS) in correspondence with the step direction required to reach the target position. (133-1).

[Effects of basic configuration]
According to such a configuration, since the data (D0, D2, D4) to be written in the registers (132a, 132b, 132c) of the output instruction unit (132-1) are all known, the output The pre-processing prior to the data writing process for each register (132a, 132b, 132c) of the instruction unit (132-1) is almost unnecessary, and as shown in FIG. 8, by reducing the load on the MPU, the previous target can be obtained. Even when a stepping pulse corresponding to the position is being output, a new setting corresponding to the next target position can be made until just before the stepping pulse output ends, improving the responsiveness in position control, and at high speed. Fine control is possible.

[Modification 1]
The output unit (133) includes a step signal generation circuit (133a ′) for generating the step signal (PS) and the direction signal, like the output unit (133-2) shown in FIG. A direction signal generation circuit (133b) for generating (DS), an output stop instruction signal (S2) for stopping output of a stepping pulse in the stepping signal (PS), and a target position are reached. An absolute position control circuit (133c ′) may be included in order to generate direction designation data (D3) representing a necessary step direction.

  The absolute position control circuit (133c ′), as shown in FIG. 4, is obtained by adding / subtracting a step pulse included in the step signal (PS) according to a logical value of the direction signal. Current position register (133c'-1) for storing position data, current position data stored in the current position register (133c'-1), and absolute position stored in the absolute position designation register (132c) An output stop instruction signal (S2) is generated based on the comparison with the designated data (D4), and the step direction determined from the polarity of the difference between the current position data and the absolute position designated data (D4) is shown. An arithmetic circuit (1334-2) for generating the direction designation data (D3), and outputting the output stop instruction signal (S2) and the direction designation data (D3) thus generated. It may be.

  As shown in FIG. 3, the step signal generation circuit (133a ′) stores the step pulse in the pulse interval designation register (132b) in response to the timing of the output instruction signal (S1). At the pulse interval designated by the designated pulse interval designation data (D2), output is started during the step signal (PS) and the output stop instruction signal (S2) outputted from the absolute position control circuit (133c ′) ), The output of the stepping pulse may be stopped.

  As shown in FIG. 3, the direction signal generation circuit (133b) has a logical value corresponding to the direction indicated by the direction designation data (D3) output from the absolute position control circuit (133c ′). (DS) may be output.

[Effects of Modification 1]
According to such a configuration, in addition to the operational effects of the basic configuration, as shown in FIG. 4, in the arithmetic circuit (1334-2), the function of calculating the movement amount becomes unnecessary, and the circuit is correspondingly increased. There is an advantage that the configuration is simplified.

[Modification 2]
As in the output instruction unit (132-3) shown in FIG. 7, the output instruction unit (132) is a register for switching the position designation mode between the relative position designation mode and the absolute position designation mode. / Relative / absolute / switch register (132f) for storing absolute / switching data, pulse output number specifying register (132g) for storing pulse output number specifying data (D1), and direction specifying data are stored. And a predetermined relative / absolute / switching signal (S4) based on the relative / absolute / switching data written to the relative / absolute / switching register (132f). It may be configured to generate.

  When the relative / absolute / switching signal (S4) indicates the relative position designation mode, the output unit (133) can be configured like the output unit (133-4) shown in FIG. The step signal generation circuit (133a), like the step signal generation circuit (133a ″), responds to the timing of the output instruction signal (S1) and outputs a pulse output number designation register (132g). The number of stepping pulses designated by the pulse output number designation data (D1) stored in the pulse interval designation data (D2) stored in the pulse interval designation register (132b) It may be configured to output during the step signal (PS).

The direction signal generation circuit (133b) also has a logical value corresponding to the direction indicated by the direction specification data (D 6 ) stored in the direction specification register (132h) like the direction signal generation circuit (133b ′). May be configured to output a direction signal (DS).

  When the relative / absolute / switch signal (S4) indicates the absolute position designation mode, the output unit (133) can be configured like the output unit (133-4) shown in FIG. The step signal generation circuit (133a), like the step signal generation circuit (133a ″), in response to the timing of the output instruction signal (S1), the step pulse generation circuit (133a) At the pulse interval designated by the pulse interval designation data (D2) stored in the interval designation register (132b), output is started during the advance signal (PS) and output from the absolute position control circuit (133c ″). In response to the output stop instruction signal (S2), the output of the stepping pulse may be stopped.

  The direction signal generation circuit (133b) is the direction indicated by the direction designation data (D3) output from the absolute position control circuit (133c ″) like the direction signal generation circuit (133b ′) shown in FIG. The direction designation data (D3) output from the absolute position control circuit (133c ″) may of course be output so as to output a direction signal (DS) having a logical value corresponding to. The difference between the current position data obtained by adding or subtracting the step pulse included in the step signal (PS) according to the logical value of the direction signal (DS) and the absolute position designation data (D4). It is generated from the polarity and is not stored in the direction designation register 132h.

[Effects of Modification 2]
According to such a configuration, in addition to the operational effects of the basic configuration, as long as data corresponding to the “relative mode” is written in the relative / absolute switching register 132f, the “pulse interval” and the “pulse output” are performed as before. By directly specifying “number” and “stepping direction”, it is possible to generate a stepping signal PS and a direction signal DS having a desired signal form, while the relative / absolute switching register 132f has “absolute mode”. As long as the data corresponding to “” is written, simply by specifying the “pulse interval” and the “target position (absolute position)”, the step signal PS and the direction signal DS having the optimum signal form are automatically generated. It can be generated and can be used optimally depending on the application.

[Modification 3]
The output unit 133 includes a step signal generation circuit (133a) for generating the step signal (PS) and the direction signal (DS) like the output unit (133-1) shown in FIG. A direction signal generation circuit (133b) for generating a signal, output number designation data (D1) indicating the number of stepping pulses necessary to reach the target position, and a stepping direction necessary for reaching the target position An absolute position control circuit (133c) may be included to generate the direction designation data (D3).

  As shown in FIG. 2, the absolute position control circuit (133c) stores current position data obtained by adding or subtracting a step pulse included in the step signal according to a logical value of the direction signal. Current position register (133 c-1) for performing the difference between the current position data stored in the current position register (133 c-1) and the absolute position designation data (D 4) stored in the absolute position designation register Output number designation data (D1) is generated from the absolute value, and direction designation data (D3) indicating the stepping direction determined from the polarity of the difference between the current position data and the absolute position designation data (D4) is generated. And outputs the output number designation data (D1) and the direction designation data (D3) thus generated in synchronization with the output instruction signal (S1). It may be configured so.

  In response to the timing of the output instruction signal (S1), the step signal generation circuit (133a) has the number of outputs specified by the output number specifying data (D1) output from the absolute position control circuit (133c). The step pulse may be output in the step signal (PS) at a pulse interval designated by the pulse interval designation data (D2) stored in the pulse interval designation register (132b). Good.

  The direction signal generation circuit (133b) is configured to output a direction signal (DS) having a logical value corresponding to the direction indicated by the direction designation data (D3) output from the absolute position control circuit (133c). May be.

[Effects of Modification 3]
According to such a configuration, there is an advantage that the step signal generation circuit (1223a) used conventionally shown in FIG. 15 can be used in addition to the function and effect of the basic configuration.

[Modification 4]
In any of the basic configuration and third modifications described above, the output control unit (132), as the output control unit (132-2) shown in FIG. 5, as the register, further, the preset instructions a preset instructions register for storing the data (132d), and a preset value designation register for storing the preset value specified data (132e), and the preset instructions data the preset instructions register (132d) in response to the timing stored in, or may be configured to generate a predetermined preset instructions signal (S3).

The absolute position control circuit (133c) is stored as an absolute position control circuit shown in FIG. 5 (133c "), in response to said preset instructions signal (S3), the preset value specified register (132e) The preset value specified by the preset value specifying data may be configured to be preset in the current position register (133c ″ -1).

[Effects of Modification 4]
According to such a configuration, there is an advantage that a one-dimensional coordinate reference point for defining the current position can be freely determined.

[Application example]
The pulse output device according to the basic configuration and the first to fourth modifications can be applied to a position control unit of a building block type PLC. That is, this position control unit is a one-element unit of a building block type PLC (12) used together with the CPU unit (11), the input / output unit, and the like, and has the following configuration.

  That is, the position control unit includes an MPU system (121) connectable to an internal bus (123) connected to the CPU unit (11), and a pulse output device to which position control command data is given from the MPU system (121). (122).

  The MPU system (121) is expressed by a command analysis processing unit (P1) for analyzing a control command received from the CPU unit, and a predetermined command unit system obtained as a result of analysis in the command analysis processing unit. Based on the target position, a series of speeds corresponding to each time-division instantaneous value of the speed profile from the current position to the target position is calculated, and a series of movement amount data expressed in a predetermined pulse unit system is obtained in time series. A position control calculation processing unit (P2, P3) with unit conversion function to be output and a series of movement amount data output in time series from the position control calculation processing unit (P2, P3) with unit conversion function Based on the above, the target position data and speed data for the time being are determined one after another, and based on each of the determined data pairs (target position data and speed data), It includes the pulse output command processing unit to provide the necessary instruction to pulse output unit 122 and (P4).

  As the pulse output device, the pulse output device according to any one of the basic configuration and the first to fourth modifications is used.

[Function and effect of application example]
According to this position control unit, it is possible to make new settings corresponding to the next target position until just before the end of the output of the stepping pulse, thus improving responsiveness in position control and enabling high-speed and fine control. Become.

  According to the pulse output device of the present invention, since the data (D0, D2, D4) to be written to the registers (132a, 132b, 132c) of the output instruction unit (132) are all known, output is performed. The pre-processing prior to the data writing process for each register (132a, 132b, 132c) of the instruction unit (132-1) is almost unnecessary, and as shown in FIG. 8, by reducing the load on the MPU, the previous target can be obtained. Even when a stepping pulse corresponding to the position is being output, a new setting corresponding to the next target position can be made until just before the stepping pulse output ends, improving the responsiveness in position control, and at high speed. Fine control is possible.

  Hereinafter, a preferred embodiment of a pulse output device according to the present invention will be described in detail with reference to the accompanying drawings. In the following embodiments, the pulse output device according to the present invention is realized as an ASIC (Application Specific IC).

[First Embodiment]
FIG. 1 shows a configuration diagram (first embodiment) of a pulse output ASIC which is a pulse output device according to the present invention. As described above with reference to FIGS. 11 to 14, the pulse output ASIC 13 includes the MPU system 121 that generates position control command data, the step signal PS including a series of step pulse trains, and the step direction. Position control command data provided from the MPU system 121, which is interposed between the motor drive device 2 which advances a drive source such as a motor in a designated direction based on a direction signal DS having a logical value corresponding to The step signal PS and the direction signal DS corresponding to the signal are generated and output based on the above.

  The pulse output ASIC 13 is connected to an MPU bus 123 connected to the MPU system 121, and is connected to the MPU system 121 via an MPU / I / F control unit 131 and an MPU / I / F control unit 131. Output instruction unit 132-1 including a register to which position control command data can be written from the MPU system 121 side, and a step signal PS based on the position control command data written in the register of the output instruction unit 132-1 And an output unit 133-1 that generates and outputs the direction signal DS.

  The output instruction unit 132-1 includes, as the registers, an output instruction register 132a for storing output instruction data D0 (not shown), a pulse interval specification register 132b for storing pulse interval specification data D2, and a target And an absolute position designation register 132c for storing absolute position designation data D4 representing the position by the absolute position, and a predetermined output instruction in response to the timing when the output instruction data D0 is written in the output instruction register 132a The signal S1 is configured to be generated.

  The output unit 133-1 includes a step signal generation circuit 133a for generating the step signal PS, a direction signal generation circuit 133b for generating the direction signal DS, and a step pulse necessary for reaching the target position. An absolute position control circuit 133c for generating the output number designation data D1 representing the number of lines and the direction designation data D3 representing the stepping direction necessary to reach the target position.

  A detailed configuration diagram of the absolute position control circuit 133c shown in FIG. 1 is schematically shown in FIG. 2 using logic symbols.

  In FIG. 2, the data input D of the current position register 133c-1 is alternatively inputted with its own “Q output value +1” or “Q output value −1” via the switch 1333. The step signal PS is supplied to the clock input CK, and the switching operation of the switch 1333 is controlled by the direction signal DS. Therefore, the current position data 133c-1 stores current position data obtained by adding / subtracting the stepping pulse included in the stepping signal PS according to the logical value of the direction signal DS.

  The arithmetic circuit 1334-1 calculates the output number designation data from the absolute value of the difference between the current position data stored in the current position register 133c-1 and the absolute position designation data D4 corresponding to the target position stored in the absolute position designation register. In addition to generating D1, direction specifying data D3 indicating the stepping direction determined from the polarity of the difference between the current position data and the absolute position specifying data D4 is generated.

  An explanatory diagram of the ring count operation when the current position and the designated position are given is shown in FIG. As shown in the figure, in this arithmetic circuit 1334-1, assuming a ring count operation, if the current position <specified position, the stepping direction is clockwise (CW direction) and the movement amount is (specified position). -Current position), if current position> specified position, the stepping direction is counterclockwise (CCW direction) and the movement amount is (current position-specified position), and the current position = In the case of the designated position, the current direction is maintained as the stepping direction, and the movement amount is set to zero.

  Since the output number designation data D1 thus generated is latched in the register 1335 in synchronization with the generation timing of the output instruction signal S1, the output number designation data D1 and the direction designation data D3 are synchronized with the output instruction signal S1. Will be output to the outside.

  In response to the reception timing of the output instruction signal S1, the step signal generation circuit 133a outputs the number of step pulses designated by the output number designation data D1 output from the absolute position control circuit 133c to the pulse interval designation register 132b. Is output in the step signal PS at a pulse interval specified by the pulse interval specifying data D2 stored in the.

  The direction signal generation circuit 133b is configured to output a direction signal DS having a logical value corresponding to the direction indicated by the direction designation data D3 output from the absolute position control circuit 133c.

  According to the above configuration, the output number designation data D1 and the direction designation data D3 required for generating the step signal PS and the direction signal DS are automatically generated by the action of the absolute position control circuit 133c. Therefore, on the MPU system 121 side, as shown in FIG. 8, after writing the pulse interval designation data D2 and the absolute position designation data D4 corresponding to the target position into the pulse interval designation register 132b and the absolute position designation register 132c, (Step 201) By simply writing the output instruction data D0 into the output instruction register 132a (Step 201), the step signal PS and the direction signal DS required to approach the target position at a predetermined speed can be generated.

  At this time, since the data D0, D2, and D4 to be written to the registers 132a, 132b, and 132c of the output instruction unit 132-1 are all known, the registers 132a and 132b of the output instruction unit 132-1 are known. , 132c, the pre-processing prior to the data writing process becomes almost unnecessary, and the load on the MPU can be reduced by that amount. Even if the step pulse corresponding to the previous target position is being output, the step New settings corresponding to the next target position can be made until just before the end of pulse output, responsiveness in position control is improved, and high-speed and fine control is possible.

  According to the experiments by the present inventors, as shown in FIG. 9, when it is desired to set the target value to “4” during the output of the stepping pulse, the margin even during high frequency (for example, 1 MHz) output. It was confirmed that control could be implemented without need.

[Second Embodiment]
FIG. 3 shows a configuration diagram (second embodiment) of the pulse output ASIC according to the present invention. As described above with reference to FIGS. 11 to 14, the pulse output ASIC 13 also includes an MPU system 121 that generates position control command data, a step signal PS including a series of step pulse trains, and a step direction. Position control command data provided from the MPU system 121, which is interposed between the motor drive device 2 which advances a drive source such as a motor in a designated direction based on a direction signal DS having a logical value corresponding to The step signal PS and the direction signal DS corresponding to the signal are generated and output based on the above.

  The pulse output ASIC 13 is connected to an MPU bus 123 connected to the MPU system 121, and is connected to the MPU system 121 via an MPU / I / F control unit 131 and an MPU / I / F control unit 131. Output instruction unit 132-1 including a register to which position control command data can be written from the MPU system 121 side, and a step signal PS based on the position control command data written in the register of the output instruction unit 132-1 And an output unit 133-2 that generates and outputs the direction signal DS.

  The output instruction unit 132-1 includes the output instruction register 132a for storing the output instruction data D0, the pulse interval specification register 132b for storing the pulse interval specification data D2, and the target position as the absolute position as the register. And a predetermined output instruction signal S1 in response to the timing when the output instruction data D0 is written in the output instruction register 132a. It is configured as follows.

  The output unit 133-2 includes a step signal generation circuit 133a ′ for generating the step signal PS, a direction signal generation circuit 133b for generating the direction signal DS, and a step pulse in the step signal PS. An output stop instruction signal S2 for stopping output and an absolute position control circuit 133c 'for generating direction designation data D3 indicating a stepping direction necessary to reach the target position are configured.

  A detailed configuration diagram of the absolute position control circuit 133c ′ shown in FIG. 3 is schematically shown in FIG. 4 using logic symbols.

  In FIG. 4, the current “Q output value + 1” or “Q output value−1” is alternatively input to the data input D of the current position register 133c′-1 via the switch 1333. Further, the step signal PS is supplied to the clock input CK, and the switching operation of the switch 1333 is controlled by the direction signal DS. Therefore, current position data obtained by adding / subtracting the stepping pulse included in the stepping signal PS according to the logical value of the direction signal DS is stored in the current value register 133c′-1.

  The arithmetic circuit 1334-2 calculates the output stop instruction source signal (current position) based on the comparison between the current position data stored in the current position register 133c′-1 and the absolute position designation data D4 stored in the absolute position designation register 132c. = In the case of the designated position, “H”) S2 ′ is generated, and direction designation data D3 indicating the stepping direction determined from the polarity of the difference between the current position data and the absolute position designation data D4 is generated. The output stop instruction source signal S2 ′ and the direction designation data D3 are output. At this time, the edge from “L” to “H” of the output stop instruction source signal S2 ′ is converted to the output stop instruction signal S2 which is a minute width “H” pulse through the differentiating circuit 1336.

  Returning to FIG. 3, in response to the generation timing of the output instruction signal S1, the step signal generation circuit 133a ′ designates the step pulse by the pulse interval designation data D2 stored in the pulse interval designation register 132b. At the pulse interval, output is started during the step signal PS, and output of the step pulse is stopped in response to the output stop instruction signal S2 output from the absolute position control circuit 133c ′.

  The direction signal generation circuit 133b is configured to output a direction signal DS having a logical value corresponding to the direction indicated by the direction designation data D3 output from the absolute position control circuit 133c ′.

  According to the above configuration, the output stop instruction signal S2 and the direction designation data D3 required for generating the step signal PS and the direction signal DS are automatically generated by the action of the absolute position control circuit 133c ′. Therefore, on the side of the MPU system 121, as shown in FIG. 8, the pulse interval designation data D2 and the absolute position designation data D4 corresponding to the target position are written in the pulse interval designation register 132b and the absolute position designation register 132c. After that (step 201), only by writing the output instruction data D0 into the output instruction register 132a (step 202), the step signal PS and the direction signal DS required to approach the target position at a predetermined speed can be generated.

  At this time, since the data D0, D2, and D4 to be written to the registers 132a, 132b, and 132c of the output instruction unit 132-1 are all known, the registers 132a and 132b of the output instruction unit 132-1 are known. , 132c, the pre-processing prior to the data writing process becomes almost unnecessary, and the load on the MPU can be reduced by that amount. Even if the step pulse corresponding to the previous target position is being output, the step New settings corresponding to the next target position can be made until just before the end of pulse output, responsiveness in position control is improved, and high-speed and fine control is possible.

  Moreover, in the second embodiment, the absolute position control circuit does not need a function for calculating the movement amount, and there is an advantage that the circuit configuration is simplified correspondingly.

[Third Embodiment]
A block diagram (third embodiment) of a pulse output ASIC according to the present invention is shown in FIG. As described above with reference to FIGS. 11 to 14, the pulse output ASIC 13 also includes an MPU system 121 that generates position control command data, a step signal PS including a series of step pulse trains, and a step direction. Position control command data provided from the MPU system 121, which is interposed between the motor drive device 2 which advances a drive source such as a motor in a designated direction based on a direction signal DS having a logical value corresponding to The step signal PS and the direction signal DS corresponding to the signal are generated and output based on the above.

  The pulse output ASIC 13 is connected to an MPU bus 123 connected to the MPU system 121, and is connected to the MPU system 121 via an MPU / I / F control unit 131 and an MPU / I / F control unit 131. Output instruction unit 132-2 including a register to which position control command data can be written from the MPU system 121 side, and a step signal PS based on the position control command data written in the register of the output instruction unit 132-2. And an output unit 133-3 that generates and outputs the direction signal DS.

  The output instruction unit 132-2 includes the output instruction register 132a for storing the output instruction data D0, the pulse interval specification register 132b for storing the pulse interval specification data D2, and the target position as its absolute position. And a predetermined output instruction signal S1 in response to the timing when the output instruction data D0 is written in the output instruction register 132a. It is configured as follows.

  In addition, the output instruction unit 132-2 includes a preset instruction register 132d for storing preset instruction data and a preset value specifying register 132e for storing preset value specifying data D5. A predetermined preset instruction signal S3 is generated in response to the timing at which the instruction data is written to the preset instruction register.

  The output unit 133-3 includes a step signal generation circuit 133 a ′ for generating the step signal PS, a direction signal generation circuit 133 b for generating the direction signal DS, and a step pulse in the step signal PS. It includes an absolute position control circuit 133c ″ for generating an output stop instruction signal S2 for stopping output and direction designation data D3 indicating a stepping direction necessary to reach the target position.

  A detailed configuration diagram of the absolute position control circuit 133c ″ shown in FIG. 5 is schematically shown in FIG. 6 using logic symbols.

  6, the preset value designation data D5 and the output of the switch 1333 are alternatively input to the data input D of the current position register 133c ″ −1 via the switch 1337. On the output side, “Q output value + 1” or “Q output value−1” of the current position register 133c ″ −1 is alternatively output according to the logical value of the direction signal DS. The switching operation of the switch 1337 is controlled by the output of an AND gate 1338 that generates a logical product of the output instruction signal S1 and the preset instruction signal S3. The clock input CK of the current position register 133c ″ -1 is supplied with the output of an OR gate that generates a logical sum of the output of the AND gate 1338 and the output of the step signal PS.

  Therefore, in the current position register 133c ″ -1, an arbitrary preset value is read as the current position in response to the generation timing of the preset instruction signal S3, and the read current position is included in the step signal PS. Are added and subtracted and updated according to the stepping pulse and the logical value of the direction signal DS.

  The arithmetic circuit 1334-2 calculates the output stop instruction source signal (current position) based on the comparison between the current position data stored in the current position register 133c ″ -1 and the absolute position designation data D4 stored in the absolute position designation register 132c. = In the case of the designated position, “H”) S2 ′ is generated, and direction designation data D3 indicating the stepping direction determined from the polarity of the difference between the current position data and the absolute position designation data D4 is generated. The output stop instruction source signal S2 ′ and the direction designation data D3 are output.At this time, the edge from “L” to “H” of the output stop instruction source signal S2 ′ It is converted into an output stop instruction signal S2 which is a minute width “H” pulse through a differentiation circuit 1336.

  Returning to FIG. 5, the step signal generation circuit 133c responds to the generation timing of the output instruction signal S1, and the step pulse is designated by the pulse interval designation data D2 stored in the pulse interval designation register 132b. At intervals, output is started during the step signal PS, and output of the step pulse is stopped in response to the output stop instruction signal S2 output from the absolute position control circuit 133c ″.

  The direction signal generation circuit 133b is configured to output a direction signal DS having a logical value corresponding to the direction indicated by the direction designation data D3 output from the absolute position control circuit 133c ″.

  According to the above configuration, the output stop instruction signal S2 and the direction designation data D3 required for generating the step signal PS and the direction signal DS are automatically generated by the action of the absolute position control circuit 133c ″. Therefore, on the side of the MPU system 121, as shown in FIG. 8, the pulse interval designation data D2 and the absolute position designation data D4 corresponding to the target position are written in the pulse interval designation register 132b and the absolute position designation register 132c. After that (step 201), only by writing the output instruction data D0 to the output instruction register 132a (step 201), the step signal PS and the direction signal DS required to approach the target position at a predetermined speed can be generated.

  At this time, since the data D0, D2, and D4 to be written to the registers 132a, 132b, and 132c of the output instruction unit 132-2 are all known, the registers 132a and 132b of the output instruction unit 132-2 are known. , 132c, the pre-processing prior to the data writing process becomes almost unnecessary, and the load on the MPU can be reduced by that amount. Even if the step pulse corresponding to the previous target position is being output, the step New settings corresponding to the next target position can be made until just before the end of pulse output, responsiveness in position control is improved, and high-speed and fine control is possible.

  In addition, in the third embodiment, by appropriately operating the preset instruction register 132d and the preset value specifying register 132e, it is possible to freely determine a reference point of one-dimensional coordinates for defining the current position. There are advantages you can do.

[Fourth Embodiment]
A block diagram (fourth embodiment) of a pulse output ASIC according to the present invention is shown in FIG. As described above with reference to FIGS. 11 to 14, the pulse output ASIC 13 also includes an MPU system 121 that generates position control command data, a step signal PS including a series of step pulse trains, and a step direction. Position control command data provided from the MPU system 121, which is interposed between the motor drive device 2 which advances a drive source such as a motor in a designated direction based on a direction signal DS having a logical value corresponding to The step signal PS and the direction signal DS corresponding to the signal are generated and output based on the above.

  The pulse output ASIC 13 is connected to an MPU bus 123 connected to the MPU system 121, and is connected to the MPU system 121 via an MPU / I / F control unit 131 and an MPU / I / F control unit 131. Output instruction unit 132-3 including a register to which position control command data can be written from the MPU system 121 side, and a step signal PS based on the position control command data written in the register of the output instruction unit 132-3. And an output unit 133-4 that generates and outputs the direction signal DS.

  The output instruction unit 132-3 includes, as the registers, an output instruction register 132a for storing the output instruction data D0, a pulse interval specification register 132b for storing the pulse interval specification data D2, and a target position as its absolute position. And a predetermined output instruction signal S1 in response to the timing when the output instruction data D0 is written in the output instruction register 132a. It is configured as follows.

  The output instruction unit 132-3 includes a preset instruction register 132d for storing preset instruction data and a preset value specifying register 132e for storing preset value specifying data D5. A predetermined preset instruction signal S3 is generated in response to the timing at which data is written to the preset instruction register.

  Furthermore, the output instruction unit 132-3 uses the relative / absolute / switch register 132f for storing relative / absolute / switch data for switching the position designation mode between the relative position designation mode and the absolute position designation mode as the register. And a pulse output number specifying register 132g for storing the pulse output number specifying data D1 and a direction specifying register 132h for storing the direction specifying data D3, and the relative / absolute / switching register (132f). A predetermined relative / absolute / switching signal S4 is generated on the basis of the written relative / absolute / switching data.

When the relative / absolute / switching signal S4 indicates the relative position designation mode, in the output unit 133-4, the step signal generation circuit 133a ″ is responsive to the timing of the output instruction signal S1 in the pulse output number designation register. The number of stepping pulses specified by the pulse output number specifying data D1 stored in 132g is added to the stepping signal PS at the pulse interval specified by the pulse interval specifying data D2 stored in the pulse interval specifying register 132b. is configured to output, at the same time, the direction signal generating circuit 133B', to output the direction signal DS having a logical value corresponding to the direction indicated by the direction specifying data D 6 stored in the direction designation register 132h It is configured.

  When the relative / absolute / switching signal S4 indicates the absolute position designation mode, in the output unit 134-4, the step signal generation circuit 133a ″ sends the step pulse to the pulse interval in response to the timing of the output instruction signal S1. At the pulse interval designated by the pulse interval designation data D2 stored in the designation register 132b, output is started during the step signal PS and in response to the output stop instruction signal S2 outputted from the absolute position control circuit 133c ″ At the same time, the direction signal generation circuit 133b ′ outputs a logical value corresponding to the direction indicated by the direction designation data D3 output from the absolute position control circuit 133c ″. The direction signal DS is configured to be output.

[Effects of Fourth Embodiment]
According to the above configuration, in addition to the operational effects of the configuration of the third embodiment, as long as data corresponding to the “relative mode” is written in the relative / absolute switching register 132f, the “pulse interval”, By directly specifying the “number of pulse outputs” and the “stepping direction”, the stepping signal PS and the direction signal DS having a desired signal form can be generated, while the relative / absolute switching register 132f As long as the data corresponding to the “absolute mode” is written, the step signal PS and the direction signal automatically having the optimum signal form can be automatically specified simply by specifying the “pulse interval” and the “target position (absolute position)”. DS can be generated, and optimal usage is possible depending on the application.

[Application example]
The pulse output ASIC 13 according to the first to fourth embodiments described above can be applied to the position control unit 12 of the building block type PLC 1. That is, as shown in FIG. 11, the position control unit 12 is a one-element unit of a building block type PLC 1 that is used together with the CPU unit 11, the input / output unit, and the like, and has the following configuration.

  That is, as shown in FIG. 12, the position control unit 12 includes an MPU system 121 that can be connected to an internal bus 123 connected to the CPU unit 11, and a pulse output ASIC 13 (to which position control command data is given from the MPU system 121). Equivalent to 122 of the conventional example).

  As shown in FIG. 13, the MPU system 121 is represented by a command analysis processing unit P1 that analyzes a control command received from the CPU unit 11, and a predetermined command unit system obtained as a result of analysis in the command analysis processing unit. Based on the set target position, a series of speeds corresponding to each time-division instantaneous value of the speed profile from the current position to the target position is calculated, and a series of movement amount data expressed in a predetermined pulse unit system is obtained as a time series. Based on position control calculation processing units P2 and P3 with unit conversion function and a series of movement amount data output in time series from position control calculation processing units P2 and P3 with unit conversion function The target position data and speed data for the time being are determined one after another as a pair, and based on each determined data pair (target position data and speed data) And a pulse output command processor P4 to provide the necessary instructions to (corresponding to 122) output ASIC 13. As the pulse output ASIC 13, any of the pulse output ASICs 13 according to the first to fourth embodiments described above is employed.

[Function and effect of application example]
According to this position control unit, a new setting corresponding to the next target position can be made until just before the end of the output of the stepping pulse, so that the responsiveness in position control is improved and high-speed and accurate fine control is achieved. It becomes possible.

  The pulse output device (pulse output ASIC in the embodiment) of the present invention includes, for example, an MPU system that generates position control command data and a series of stepping pulse trains in a position control unit that is an element unit of a building block type PLC. Between a drive device that advances a drive source such as a motor in a designated direction based on a step signal (PS) including a direction signal (DS) having a logical value corresponding to the step direction By doing so, the responsiveness in position control in the position control unit is improved, and high-speed and fine control is possible.

It is a block diagram (1st Embodiment) of the pulse output ASIC which is an example of the pulse output device which concerns on this invention. It is a detailed block diagram of the absolute position control circuit shown by FIG. It is a block diagram (2nd Embodiment) of the pulse output ASIC which is an example of the pulse output device which concerns on this invention. FIG. 4 is a detailed configuration diagram of an absolute position control circuit shown in FIG. 3. It is a block diagram (3rd Embodiment) of the pulse output ASIC which is an example of the pulse output device which concerns on this invention. FIG. 6 is a detailed configuration diagram of the absolute position control circuit shown in FIG. 5. It is a block diagram (4th Embodiment) of the pulse output ASIC which is an example of the pulse output device which concerns on this invention. It is a flowchart which shows the MPU process of this invention. It is explanatory drawing of the pulse output waveform at the time of use of the pulse output ASIC which is an example of the pulse output device which concerns on this invention, a present value, and the timing of designated value change. It is explanatory drawing of the ring count operation | movement when the present position and the designated position are given. It is a schematic diagram which shows the application example of PLC containing a position control unit. It is a block diagram which shows the whole structure of a position control unit. It is a detailed block diagram of PLC. It is explanatory drawing of the MPU process in a position control unit. It is a block diagram of pulse output ASIC which is an example of the conventional pulse output device. It is a flowchart which shows the conventional MPU process. It is explanatory drawing of the pulse output waveform at the time of using pulse output ASIC which is an example of the conventional pulse output device, a present value, and the timing of command value change.

Explanation of symbols

1 PLC
DESCRIPTION OF SYMBOLS 2 Motor drive device 3 Motor 4a Upper sprocket 4b Lower sprocket 5 Chain 6 Lifting base 7 Lifting guide 11 CPU unit 12 Position control unit 13 Pulse output ASIC (this invention)
121 MPU system 121a MPU
121b ROM
121c RAM
122 Pulse output ASIC (conventional example)
123 Internal bus 124 Bus I / F part 131 MPU / I / F control part 132-1-3 Output instruction part 132a Output instruction register 132b Pulse interval designation register 132c Absolute position designation register 132d Preset instruction register 132e Preset value designation register 132f Relative / Absolute / switching register 132g Pulse output number designation register 132h Direction designation register 133-1-4 Output unit 133a, 133a ', 133a "Step signal generation circuit 133b, 133b' Direction signal generation circuit 133c, 133c ', 133c" Absolute Position control circuit 133c-1, 133c'-1, 133c "-1 Current position register P1 Command analysis processing unit P2 Unit conversion processing unit P3 Position control calculation processing unit P4 Pulse output command processing unit 1221 MPU / I / F control unit 12 22 Output instruction section 1222a Output instruction register 1222b Pulse output number designation register 1222c Pulse interval designation register 1222d Direction designation register S1 Output instruction signal S2 Output stop instruction signal S3 Preset instruction signal S4 Relative / absolute / switching signal D1 Pulse output number designation data D2 Pulse interval designation data D3 Direction designation data D4 Absolute position designation data D5 Preset value designation data
D6 Direction specification data

Claims (6)

Based on an MPU system (121) that generates position control command data, a step signal (PS) including a series of step pulse trains, and a direction signal (DS) having a logical value corresponding to the step direction, etc. Based on the position control command data given from the MPU system (121), which is interposed between the drive source (2) and the drive device (2) that advances in the designated direction. PS) and a pulse output device (13) for generating and outputting the direction signal (DS),
An MPU / I / F control unit (131) connected to an MPU bus (123) connected to the MPU system (121) and functioning as an interface with the MPU system (121);
An output instruction unit (132) including a register to which the position control command data can be written from the MPU system (121) side via the MPU / I / F control unit (131);
An output unit (133) for generating and outputting the step signal (PS) and the direction signal (DS) based on the position control command data written in the register of the output instruction unit (132-1); And
The output instruction unit (132)
As the registers, an output instruction register (132a) for storing output instruction data, a pulse interval specification register (132b) for storing pulse interval specification data (D2), and an absolute value that represents the target position by its absolute position An absolute position designation register (132c) for storing position designation data (D4), and a predetermined output designation signal (S1) in response to the timing when the output designation data is written in the output designation register Is configured (132-1) to generate
The output unit (133)
In response to the output instruction signal (S1), absolute position designation data (D4) stored in the absolute position designation register (132c) and pulse interval designation data (D2) stored in the pulse interval designation register (132b). ), The number of stepping pulses required to reach the target position specified by the absolute position specifying data (D4) is changed at the step interval specified by the pulse interval specifying data (D2). The signal is output during the advance signal (PS), and the logical value of the direction signal (DS) is changed (133-1) in accordance with the stepping direction necessary to reach the target position. A pulse output device characterized by that. The output unit (133)
A step signal generation circuit (133a ′) for generating the step signal (PS);
A direction signal generation circuit (133b) for generating the direction signal (DS);
An output stop instruction signal (S2) for stopping the output of the stepping pulse in the stepping signal (PS) and direction designation data (D3) indicating the stepping direction necessary to reach the target position are generated. Therefore, an absolute position control circuit (133c ') is included (133-2),
The absolute position control circuit (133c ′)
A current position register (133c′-1) for storing current position data obtained by adding or subtracting a step pulse included in the step signal (PS) according to a logical value of the direction signal;
Based on the comparison between the current position data stored in the current position register (133c'-1) and the absolute position designation data (D4) stored in the absolute position designation register (132c), an output stop instruction signal (S2) And an arithmetic circuit (1334-2) for generating direction designation data (D3) indicating a stepping direction determined from the polarity of the difference between the current position data and the absolute position designation data (D4). Have
The output stop instruction signal (S2) and the direction designation data (D3) generated in this way are output,
The step signal generation circuit (133a ′)
In response to the timing of the output instruction signal (S1), the stepping pulse is changed at the pulse interval designated by the pulse interval designation data (D2) stored in the pulse interval designation register (132b). The output is started during the signal (PS), and the output of the stepping pulse is stopped in response to the output stop instruction signal (S2) output from the absolute position control circuit (133c ′). And
The direction signal generation circuit (133b)
It is configured to output a direction signal (DS) having a logical value corresponding to the direction indicated by the direction designation data (D3) output from the absolute position control circuit (133c ′). The pulse output device (13) according to claim 1. The output instruction unit (132)
The register further includes a relative / absolute / switching register (132f) for storing relative / absolute / switching data for switching the position designation mode between the relative position designation mode and the absolute position designation mode, and a pulse output number designation. A pulse output number designation register (132g) for storing data (D1) and a direction designation register (132h) for storing direction designation data, and written to the relative / absolute / switching register (132f) Based on the relative / absolute / switching data, a predetermined relative / absolute / switching signal (S4) is generated (132-3),
When the relative / absolute / switching signal (S4) indicates the relative position designation mode,
In the output unit (133),
The step signal generation circuit (133a)
In response to the timing of the output instruction signal (S1), the number of stepping pulses designated by the pulse output number designation data (D1) stored in the pulse output number designation register (132g) is changed to the pulse interval designation register. (133a ″) configured to output the step signal (PS) at a pulse interval specified by the pulse interval specification data (D2) stored in (132b), and the direction signal generation circuit (133b)
It is configured (133b ′) to output a direction signal (DS) having a logical value corresponding to the direction indicated by the direction specifying data (D 6 ) stored in the direction specifying register (132h),
When the relative / absolute / switching signal (S4) indicates the absolute position designation mode,
In the output unit (133),
The step signal generation circuit (133a)
In response to the timing of the output instruction signal (S1), the stepping pulse is changed at the pulse interval designated by the pulse interval designation data (D2) stored in the pulse interval designation register (132b). The output is started during the signal (PS), and the output of the stepping pulse is stopped in response to the output stop instruction signal (S2) output from the absolute position control circuit (133c ″) (133a) ″)
The direction signal generation circuit (133b)
It is configured (133b ′) to output a direction signal (DS) having a logical value corresponding to the direction indicated by the direction designation data (D3) output from the absolute position control circuit (133c ″). The pulse output device according to claim 2. The output unit (133)
A step signal generation circuit (133a) for generating the step signal (PS);
A direction signal generation circuit (133b) for generating the direction signal (DS);
Absolute position control for generating output number designation data (D1) representing the number of stepping pulses necessary to reach the target position and direction designation data (D3) representing the stepping direction necessary to reach the target position Circuit (133c),
The absolute position control circuit (133c)
A current position register (133c-1) for storing current position data obtained by adding or subtracting a step pulse included in the step signal according to a logical value of the direction signal;
Output number designation data (D1) is generated from the absolute value of the difference between the current position data stored in the current position register (133c-1) and the absolute position designation data (D4) stored in the absolute position designation register. And an arithmetic circuit (1334-1) for generating direction designation data (D3) indicating a stepping direction determined from the polarity of the difference between the current position data and the absolute position designation data (D4),
The output number designation data (D1) and the direction designation data (D3) generated in this way are configured to be output in synchronization with the output instruction signal (S1).
The step signal generation circuit (133a)
In response to the timing of the output instruction signal (S1), the number of stepping pulses specified by the output number specifying data (D1) output from the absolute position control circuit (133c) is transferred to the pulse interval specifying register ( 132b) is configured to output in the step signal (PS) at a pulse interval specified by the pulse interval specification data (D2) stored in
The direction signal generation circuit (133b)
The direction signal (DS) having a logical value corresponding to the direction indicated by the direction designation data (D3) output from the absolute position control circuit (133c) is output. Item 2. The pulse output device according to Item 1. The output instruction unit (132)
As said register further includes a preset instructions register for storing the preset instructions data (132d), and a preset value designation register for storing the preset value specified data (132e), and the preset instructions data There in response to the timing stored in the preset instructions register (132d), is configured (132-2) to produce a predetermined preset instructions signal (S3),
The absolute position control circuit (133c)
In response to said preset instructions signal (S3), so as to preset the preset value specified in the preset value specified data stored in the preset value specified register (132e) to said current position register (133c "-1) 5. The pulse output device according to claim 2, wherein the pulse output device is configured as (133c ″). It is a one-element unit of a building block type PLC (12) used together with a CPU unit (11) and an input / output unit,
An MPU system (121) connectable to an internal bus (123) connected to the CPU unit (11), and a pulse output ASIC (122) to which position control command data is given from the MPU system (121),
The MPU system (121)
A command analysis processing unit (P1) for analyzing a control command received from the CPU unit;
Based on the target position expressed in a predetermined command unit system obtained as a result of the analysis in the command analysis processing unit, a series of speeds corresponding to each time-division instantaneous value of the speed profile from the current position to the target position is obtained. A position control arithmetic processing unit (P2, P3) with a unit conversion function that calculates and outputs in a time series as a series of movement amount data expressed in a predetermined pulse unit system;
Based on each of a series of movement amount data output in time series from the position control calculation processing unit (P2, P3) with unit conversion function, the target position data and speed data for the time being are determined as a pair one after another. And a pulse output command processing unit (P4) for giving a necessary command to the pulse output device (122) based on each determined data pair (target position data and velocity data),
A PLC position control unit, wherein the pulse output device according to any one of claims 1 to 5 is used as the pulse output device.

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