JP5328733B2 - Array substrate inspection method and inspection apparatus - Google Patents

Description

  The present invention relates to an inspection method and an inspection apparatus for an array substrate, and more particularly to an inspection method and an inspection apparatus for an array substrate for a liquid crystal display device.

  As shown in FIGS. 20 and 21, the array substrate of the active matrix liquid crystal display device includes a data signal line 1, a scanning signal line 2 intersecting the data signal line 1, a data signal line 1, and a scanning signal line 2. And a pixel 3 arranged at the intersection. Each pixel 3 includes a thin film transistor (TFT) and a pixel capacitor.

  Here, a conventional method for inspecting the array substrate will be described.

  First, a data signal is supplied to the data signal line 1 and one scanning signal line 2A is driven. As a result, charges are accumulated in the pixels 3 connected to one scanning signal line 2A (data signal writing).

  Next, a detection circuit 4 such as an integrator is connected to each data signal line 1 and one scanning signal line 2A is driven. As a result, the charge accumulated in the pixels 3 connected to one scanning signal line 2A is detected by the detection circuit 4 (reading of a data signal).

  By repeating the above operation for all scanning signal lines 2, the entire array substrate is inspected.

  According to this inspection method, since the charge amount detected from the defective pixel is different from the charge amount detected from the normal pixel, the quality of the pixel 3 can be determined.

  In this inspection method, since the scanning signal lines 2 are sequentially driven one by one, the address of the defective pixel can be specified, but there is a problem that it takes a long time to inspect all the pixels 3. Hereinafter, this conventional inspection method is referred to as “one-pixel sequential measurement method”.

Patent Document 1 below discloses an inspection method for an active matrix liquid crystal display device. This inspection method detects a line defect by simultaneously turning on two analog switches in order to short-circuit two video buses supplying data signals. However, Patent Document 1 does not disclose the feature of the present invention that drives a plurality of scanning signal lines simultaneously.
JP 2000-74974 A

  An object of the present invention is to provide an inspection method and an inspection apparatus that can shorten the inspection time of an array substrate.

Means for Solving the Problems and Effects of the Invention

Inspection method of the array substrate according to the present invention is an inspection method of an array substrate having a plurality of signal lines, N _{1 (2} or more integer) of the array substrate in the first inspection block, each containing the plurality of signal lines , A step of selecting a total of N ₁ signal lines from each of the first inspection blocks, and a step of simultaneously inspecting the selected N ₁ signal lines.

  According to this inspection method, since two or more signal lines can be inspected together, the inspection time can be shortened.

Preferably, the inspection method further includes dividing the array substrate into N ₂ (an integer greater than or equal to 2 different from N ₁ ) second inspection blocks each including a plurality of signal lines, and each of the second inspection blocks. And selecting a total of N ₂ signal lines one by one and re-inspecting the selected N ₂ signal lines simultaneously.

  In this case, it is possible to specify an address that is common among the initial inspection and the re-inspection as a defective candidate as a defective address.

Preferably N ₁ is 2. The inspection method further includes a step of reinspecting one signal line of the first inspection block.

  In this case, since there are two addresses listed as defect candidates, if one signal line is reexamined, the defect address can be specified without reexamining the other signal line.

More preferably, the re-inspection step includes dividing the array substrate into N ₂ (integer of 2 or more) second inspection blocks each including a plurality of signal lines, and 1 from each of the second inspection blocks. The method includes a step of selecting a total of N ₂ signal lines one by one and a step of simultaneously inspecting the selected N ₂ signal lines.

  In this case, since two or more signal lines can be reinspected together, the reinspection time can be shortened.

Preferably, the inspection method further includes a step of counting the number of defective signal lines according to the result of the inspection, and a step of re-inspecting the defective signal lines when the counted number is smaller than a predetermined number; Dividing the array substrate into N ₂ (an integer greater than or equal to ₂ different from N ₁ ) second test blocks each including a plurality of signal lines when the counted number is larger than a predetermined number; Selecting a total of N ₂ signal lines, one from each of the 2 test blocks, and re-inspecting the selected N ₂ signal lines simultaneously.

  In this case, the number of defects is counted in the first inspection, and the re-inspection method is switched according to the number of defects. When the number of defects is small, the defective signal lines are individually re-inspected. When the number of defects is large, two or more signal lines are re-inspected together, reducing the inspection time regardless of the number of defects. be able to.

An inspection apparatus for an array substrate according to the present invention inspects an array substrate having a plurality of data signal lines, a plurality of scanning signal lines intersecting the data signal lines, and a plurality of elements corresponding to the intersections of the data signal lines and the scanning signal lines. A scanning means for driving N1 scanning signal lines out of the scanning signal lines, and driving the N1 scanning signal lines to read each of the data signal lines from the corresponding N1 elements. Detecting means for detecting the outputted data signal. The driving unit drives N ₂ ( an integer greater than or equal to 2 different from N ₁ ) scanning signal lines among the scanning signal lines after the data signal read from the N ₁ elements is detected by the detecting unit. . The N ₁ scanning signal lines and the N ₂ scanning signal lines have a common scanning signal line. Detecting means detects the data signal read out from the corresponding N ₂ pieces of element by driving the _two scanning signal lines N to each of the data signal lines. N ₁ scanning signal lines are simultaneously inspected by driving the N ₁ scanning signal lines by the driving means and detecting the data signals read from the N ₁ elements by the detecting means . N ₂ scanning signal lines are simultaneously inspected by driving the N ₂ scanning signal lines by the driving means and detecting the data signals read from the N ₂ elements by the detecting means .

According to this inspection apparatus, two or more scanning signal lines are driven, data signals are read from two or more corresponding elements, and these are detected together, so that the inspection time can be shortened. . In addition, an address that is common among the initial inspection and the re-inspection can be identified as a defective address.

An inspection apparatus for an array substrate according to the present invention inspects an array substrate having a plurality of data signal lines, a plurality of scanning signal lines intersecting the data signal lines, and a plurality of elements corresponding to the intersections of the data signal lines and the scanning signal lines. A scanning means for driving two scanning signal lines out of the scanning signal lines, and reading the data signals from each of the two corresponding elements by driving the two scanning signal lines. Detecting means for detecting the outputted data signal. After the data signal read from the two elements is detected by the detection unit, the driving unit redrives one of the two driven scanning signal lines and does not redrive the other. The detecting means detects a data signal read from each corresponding element to each of the data signal lines by re- driving one of the scanning signal lines. The two scanning signal lines are simultaneously inspected by driving the two scanning signal lines by the driving means and detecting the data signals read from the two elements by the detecting means. One scanning signal line is re-inspected by re-driving one scanning signal line by the driving means and detecting a data signal read from one element by the detecting means .

According to this inspection apparatus, the two scanning signal lines are driven, the data signals are read from the corresponding two elements, and these are detected together, so the inspection time can be shortened. In addition, since there are two addresses listed as defect candidates, if one signal line is reexamined, the defect address can be specified without reexamining the other signal line.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

  Prior to describing the inspection method according to the embodiment of the present invention, the configuration of an array substrate to be inspected will be briefly described. Here, an array substrate of an active matrix liquid crystal display device will be described as an example.

  As shown in FIG. 1, the array substrate includes a data signal line 1, a scanning signal line 2 that intersects the data signal line 1, and a pixel 3 that is disposed at the intersection of the data signal line 1 and the scanning signal line 2. . Each pixel 3 includes a TFT 5 and a pixel capacitor 6. One source / drain of the TFT 5 is connected to the data signal line 1, the other source / drain is connected to one electrode of the pixel capacitor 6, and the gate is connected to the scanning signal line 2. The other electrodes of the pixel capacitors 6 are all connected in common. The data signal line 1 is connected to the data signal line driving circuit 7. The scanning signal line 2 is connected to the scanning signal line driving circuit 8. The data signal line driving circuit 7 supplies a data signal to the data signal line 1. The scanning signal line drive circuit 8 selectively drives the scanning signal line 2.

[Inspection method]
In the inspection method according to the present embodiment, the “two-pixel simultaneous measurement method” is first performed as the first inspection, and then the “defective address specifying method” is performed as the re-inspection.

1.2 Pixel simultaneous measurement method (first inspection)
(1) As shown in FIG. 2A, an array substrate 10 to be inspected is prepared. Here, it is assumed that the array substrate has 900 scanning signal lines and one defective pixel 3D on the 700th scanning signal line.

  (2) As shown in FIG. 2B, the array substrate 10 is virtually divided in half. Specifically, the array substrate 10 is divided into two inspection blocks 10A and 10B. Each inspection block 10A, 10B includes 450 scanning signal lines.

  (3) As shown in FIG. 3, a total of two scanning signal lines 2A are selected one by one from each inspection block 10A, 10B.

  (4) The two selected scanning signal lines 2A are simultaneously inspected. Specifically, one scanning signal line 2A is driven in the first half inspection block 10A, and at the same time, one scanning signal line 2A is driven in the second half inspection block 10B. The two scanning signal lines 2A to be driven are not particularly limited, but are relatively at the same position between the two inspection blocks 10A and 10B.

  The scanning signal line 2 is inspected by writing a data signal to the pixel 3 and reading the data signal from the pixel 3.

  First, in order to write a data signal to the pixel 3, the data signal line driving circuit 7 supplies the data signal to the data signal line 1, and the scanning signal line driving circuit 8 simultaneously drives the two scanning signal lines 2A. As a result, the two columns of TFTs 5 connected to the two scanning signal lines 2A are turned on, and charges are accumulated in the corresponding two columns of pixel capacitors 6.

  Next, in order to read out the data signal from the pixel 3, as shown in FIG. 4, the detection circuit 4 is connected to each data signal line 1, and the two scanning signal lines 2A are simultaneously driven by the scanning signal line driving circuit 8. . As a result, the two rows of TFTs 5 connected to the two scanning signal lines 2A are turned on, and the charges accumulated in the corresponding two rows of pixel capacitors 6 are detected by the detection circuit 4.

  If both of the two pixels 3 selected at the same time are normal, a charge amount (hereinafter referred to as “reference charge amount”) that is twice the normal amount (the charge amount detected from one pixel 3) is detected. If one pixel 3 is defective, a charge amount different from the reference charge amount is detected.

  (5) The operations (3) and (4) are repeated for all the scanning signal lines 2. Specifically, first, the first and 451th scanning signal lines 2 are simultaneously driven, and then the second and second scanning signal lines 2 are sequentially driven to the 450th and 900th scanning signal lines 2.

  As shown in FIG. 2C, in this example, when the 250 (= 700-450) -th scanning signal line 2 and the 700 (= 450 + 250) -th scanning signal line 2 are simultaneously driven, they differ from the reference charge. The amount of charge is detected. Therefore, the two pixels 3C on these two scanning signal lines 2 are listed as defective candidates.

  Since the two-pixel simultaneous measurement method described above measures the charge amount accumulated in the two pixels 3 at the same time, the inspection time can be shortened. If there is no defective pixel as a result, the inspection time is halved. When it is found that there is no defective pixel in the first inspection, the re-inspection described later is not necessary.

  Here, the two-pixel simultaneous measurement method is adopted as the first inspection, but instead, the array substrate is divided into three inspection blocks and the charge amount accumulated in the three pixels is measured simultaneously. “Measurement method” may be adopted. In general, a method of measuring an amount of electric charges accumulated in a plurality of pixels by dividing an array substrate into a plurality of inspection blocks is hereinafter referred to as a “multiple pixel simultaneous measurement method”.

  The two-pixel simultaneous measurement method described above can determine that one of the two pixels 3 selected at the same time is defective, but cannot determine which one is defective. In order to determine which one is defective, the following defective address specifying method is performed.

2. Defect address identification method (re-inspection)
As a method for specifying an address of a defective pixel, “defective candidate pixel individual measurement method”, “three-pixel simultaneous measurement method”, “one-side two-pixel simultaneous measurement method”, and “defective candidate pixel individual measurement method and multiple pixel simultaneous measurement method” Switching method ”. Hereinafter, these will be described in order.

2.1. Defective candidate pixel individual measuring method All pixels listed as defective candidates in the two-pixel simultaneous measuring method are re-inspected one by one in order. As shown in FIG. 2C, in this example, the 250th scanning signal line 2A is first driven to measure the amount of charge accumulated in the defective candidate pixel 3C, and then the 700th scanning signal line 2A is measured. The scanning signal line 2A is driven to measure the amount of charge accumulated in the defective candidate pixel 3C on the scanning signal line 2A. Since the pixel 3C on the 250th scanning signal line 2A is normal, a normal charge amount is detected. However, since the pixel 3C on the 700th scanning signal line 2A is defective, a different charge amount is detected. The Therefore, it is possible to determine that the pixel 3C is defective and specify its address.

However, the defective candidate pixel individual measurement method requires a long time for remeasurement for specifying a defective address. Therefore, if there are many defective pixels, the inspection time may be longer than the conventional one-pixel sequential measurement method. The inspection time when the combination of the multiple pixel simultaneous measurement method and the defective candidate pixel individual measurement method is employed is expressed by the following equation (1).

  In equation (1), Tscan is the time required to measure all pixels by the one-pixel sequential measurement method (including the defective pixel detection processing time), N is the number of pixels to be measured simultaneously, and Tmode is a method for switching the measurement method (mode) Time required, Taddr represents the time required to specify a defective address per pixel (Taddr = 0 in the one-pixel sequential measurement method), D represents the number of defective pixels, and Tana represents the time required for defect analysis per pixel. .

  For example, in the case of inspecting an XGA (eXtended Graphics Array) of 1024 × 768 pixels, assuming that Tscan = 4.67 seconds, Tmode = 0.10 seconds, Taddr = 0.11 seconds, and Tana = 1.20 seconds, FIG. The graph shown is obtained. The vertical axis represents the inspection time, and the horizontal axis represents the number of defective pixels. In the graph, when the conventional one-pixel sequential measurement method is adopted, when the two-pixel simultaneous measurement method is adopted as the first inspection, and when the three-pixel simultaneous measurement method is adopted as the first inspection, the inspection time is poor. Each pixel number dependency is shown.

As is apparent from this graph, when the number of defective pixels is small, the inspection time is shorter for the two or three pixel simultaneous measurement method than for the one pixel sequential measurement method, but when the number of defective pixels increases, the inspection time is sequentially measured for one pixel. The 2 or 3 pixel simultaneous measurement method is longer than the method. In this example, if there are 7 or more defective pixels, the 3-pixel simultaneous measurement method takes a longer inspection time than the 2- pixel sequential measurement method. In addition, when there are 11 or more defective pixels, the two-pixel simultaneous measurement method takes longer than the one-pixel sequential measurement method.

  As described above, when the defective candidate pixel individual measurement method is adopted as the defective address specifying method, the inspection time becomes longer when the number of defective pixels is large. Therefore, the following three-pixel simultaneous measurement method is preferably employed as the defective address specifying method.

2.2.3 Simultaneous Measurement Method for Pixels As shown in FIGS. 6A and 6B, when the two-pixel simultaneous measurement method is performed as the first inspection as described above and the existence of a defective pixel is found, As shown in (c), the number of inspection blocks is changed, and the entire array substrate 10 is inspected again. Details are as follows.

  (1) The array substrate 10 is divided into three inspection blocks 10C, 10D, and 10E. Each inspection block 10C, 10D, 10E includes 300 scanning signal lines 2.

  (2) A total of three scanning signal lines 2 are selected one by one from each inspection block 10C, 10D, 10E.

  (3) The three selected scanning signal lines 2 are simultaneously inspected. Specifically, one scanning signal line 2 is driven in the previous third inspection block 10C, one scanning signal line 2 is driven in the middle third inspection block 10D, and the rear 3 One scanning signal line 2 is driven in the inspection block 10E. Others are basically the same as the two-pixel simultaneous measurement method which is the first inspection. That is, the amount of charge accumulated in the three pixels 3 is detected simultaneously.

  (4) The operations (2) and (3) are repeated for all the scanning signal lines 2. Specifically, first, the first, 301st, and 601st scanning signal lines 2 are simultaneously driven, and then the 300th, 600th, and 900th scanning signal lines 2 are sequentially driven three by three.

  In this example, as a result of performing the two-pixel simultaneous measurement method shown in FIG. 6B, as shown in FIG. 7A, the two pixels 3C on the 250th and 700th scanning signal lines 2 are defective. As a candidate, as a result of performing the three-pixel simultaneous measurement method shown in FIG. 6C, as shown in FIG. 7B, the 100 (= 700-300-300) line and the 400 (= 100 + 300) line are obtained. The three pixels 3C on the 700 (= 100 + 300 + 300) -th scanning signal line 2 are listed as defective candidates.

  (5) As a result of performing the two-pixel simultaneous measurement method and the three-pixel simultaneous measurement method, the pixel 3C on the 700th scanning signal line 2A common to both is determined to be defective. Therefore, the address of the defective pixel 3D can be specified. Even when both of the pixels inspected by the two-pixel simultaneous measurement method are defective, these pixels are not inspected at the same time by the three-pixel simultaneous measurement method, so that each pixel can be determined as defective.

  Here, the 2-pixel simultaneous measurement method is adopted as the first inspection, and the 3-pixel simultaneous measurement method is adopted as the re-inspection (hereinafter referred to as “2-3 pixel simultaneous measurement inspection”), but is limited to this. There is nothing. For example, “2-5 pixel simultaneous measurement inspection”, “3-4 pixel simultaneous measurement inspection”, “3-2 pixel simultaneous measurement inspection”, “4-5 pixel simultaneous measurement inspection”, “4-6 pixel simultaneous measurement inspection” Etc. may be adopted. However, “2-4 pixel simultaneous measurement inspection” or the like cannot be adopted. This is because the addresses to be inspected are completely duplicated at the same time. In short, the number of pixels simultaneously measured in one inspection need not be a divisor or multiple of the number of pixels simultaneously inspected in the other inspection.

In general, the inspection time when the N ₁ -N ₂ pixel simultaneous measurement inspection is employed is expressed by the following equation (2).

In Expression (2), N ₁ is the number of pixels that are simultaneously measured in the first inspection, N ₂ is the number of pixels that are simultaneously measured in the re-inspection, and F is the presence / absence of a defective pixel (“1” if there is a defective pixel; Represents “0”). Others are the same as Formula (1).

For example, when XGA is inspected, if Tscan = 4.67 seconds, Tmode = 0.10 seconds, and Tana = 1.20 seconds, the graph shown in FIG. 8 is obtained. The graph shows the dependence of the inspection time on the number of defective pixels when the conventional one-pixel sequential measurement method is employed, when the 2-3 pixel simultaneous measurement inspection is employed, and when the 3-4 pixel simultaneous measurement inspection is employed. Are shown respectively.

  As is apparent from this graph, the reversal phenomenon of the inspection time as shown in FIG. 5 does not occur. If it is determined at the first inspection that there are no defective pixels, the re-inspection is not performed. Therefore, the inspection time in this case is only the time required for the first inspection, and is extremely short compared to the case where even one defective pixel exists.

2.3. One-side two-pixel simultaneous measurement method As shown in FIGS. 9A and 9B, when the two-pixel simultaneous measurement method is performed in the first inspection and the existence of a defective pixel is found, as shown in FIG. 9C. In addition, the two-pixel simultaneous measurement method may be performed again only for the first half or the second half of the array substrate 10 by re-examination. This is because if there is a defective pixel in either the first half or the second half, the address of that pixel may be specified, and if there is no defective pixel, it is sufficient to specify the address of the other pixel. Details are as follows.

  (1) The first half of the array substrate 10 is further divided in half. Specifically, the first inspection block 10A is divided into two inspection blocks 10F and 10G. Each inspection block 10F, 10G includes 225 scanning signal lines 2.

  (2) A total of two scanning signal lines 2 are selected one by one from each inspection block 10F, 10G.

  (3) Two selected scanning signal lines 2 are inspected simultaneously. Specifically, one scanning signal line 2 is driven in the inspection block 10F, and at the same time, one scanning signal line 2 is driven in the inspection block 10G.

  (4) The above operations (2) and (3) are repeated for all the scanning signal lines 2 in the first half inspection block 10A. Specifically, first, the first and 226th scanning signal lines 2 are simultaneously driven, and then the second and the 225th and 450th scanning signal lines 2 are sequentially driven.

  In this example, as a result of performing the two-pixel simultaneous measurement method shown in FIG. 9B, the two pixels 3C on the 250th and 700th scanning signal lines 2 are defective as shown in FIG. 7A. As a candidate, it is found that there is no defective pixel in the first half as a result of performing the two-pixel simultaneous measurement method shown in FIG. 9C again. As a result, the pixel 3C on the 700th scanning signal line 2 in the latter half is determined to be defective. Therefore, the address of the defective pixel 3D can be specified.

  According to this one-side two-pixel simultaneous measurement method, the same two-pixel simultaneous measurement method is adopted for the initial inspection and the re-inspection, so that a stable inspection result can be obtained.

2.4. Defect candidate individual pixel measurement method and switching method of multiple pixel simultaneous measurement method In the actual array substrate 10, the number of defective pixels is often 0 to 5. When the number of defective pixels is small, the inspection time is shorter when the defective candidate pixel individual measurement method is adopted as the defective address specifying method than when the plural pixel simultaneous measurement method is adopted. Therefore, when the number of defective pixels is small, the defective address specifying method may be switched to the defective candidate pixel individual measuring method, and when the number of defective pixels is large, the defective address specifying method may be switched to the multiple pixel simultaneous measuring method. This method can be realized by software as shown in FIG. 10, for example.

  (1) The number of defective pixels is counted based on the result of the multiple pixel simultaneous measurement method performed in the first inspection (S1).

  (2) It is determined whether or not the number of counted defective pixels is equal to or greater than a predetermined number (S2).

  (3) When the number of counted defective pixels is smaller than a predetermined number, the defective pixel address is individually specified by performing the above-described defective candidate pixel individual measurement method (S3).

  (4) If the number of counted defective pixels is greater than or equal to a predetermined number, the number of simultaneously measured pixels is changed, and the multiple pixel simultaneous measurement method is performed again (S4).

  (5) Based on the result of the multiple pixel simultaneous measurement method performed in the first inspection and the result of the multiple pixel simultaneous measurement method performed in the retest, the common address is specified as the address of the defective pixel (S5).

  In the graph of FIG. 11, when the conventional one-pixel sequential measurement method is adopted, the two-pixel simultaneous measurement method is adopted for the first inspection, and the defective candidate pixel individual measurement method and 3 for the re-examination as the defective address specifying method. The dependency of the inspection time on the number of defective pixels when the switching method of the simultaneous pixel measurement method is employed is shown.

  The number of defective addresses suitable for switching the defective address specifying method to the defective candidate pixel individual measuring method and the multiple pixel simultaneous measuring method can be obtained from the relational expression between the number of defective pixels and the inspection time. For example, when the number of defective pixels is 7 or more, the defective address identification method is switched to the three-pixel simultaneous measurement method.

[Inspection equipment]
The inspection method has been described above. Next, an example of an inspection apparatus for realizing the inspection method will be described.

  A known inspection apparatus generally called an array tester includes the scanning signal line drive circuit 8 shown in FIG. The scanning signal line drive circuit 8 generally includes a clock generator 81, a gate address counter 82, and a gate driver 83, as shown in FIG. The clock generator 81 generates a clock signal CK and supplies it to the gate address counter 82 and the gate driver 83. The gate address counter 82 generates a gate address for specifying a scanning signal line to be driven. The gate driver 83 includes a shift register (not shown) and a plurality of transistors (not shown). The start signal input according to the gate address is shifted by the shift register, and the scanning signal line is driven by the transistor.

  For example, since a 1280 × 1024 pixel SXGA (Super eXtended Graphics Array) has 1024 scanning signal lines, the first scanning signal line and the 513th scanning signal line are driven simultaneously as shown in FIG. The start signal ST is input at the same timing. The start signal ST is input to the shift register in the gate driver 83 according to the gate address, and is shifted according to the clock signal CK in the shift register. As a result, scanning signals G1 to G1024 (not shown after G515) are applied from the gate driver 83 to the scanning signal lines. In this example, two scanning signal lines are simultaneously driven after time Ttest.

  As shown in FIG. 14, four switchable gate drivers 831 to 834 may be used. Each of the gate drivers 831 to 834 includes a 256-bit shift register (not shown). When the two-pixel simultaneous measurement method is performed, both the two switches 835 and 836 may be turned on, and the start signal ST may be input to the first bits of the gate drivers 831 and 833. The start signal ST input to the gate driver 831 is shifted in the gate drivers 831 and 832. As a result, the scanning signal lines in the first half of the array substrate are sequentially driven. At the same time, the start signal ST input to the gate driver 833 is shifted in the gate drivers 833 and 834. As a result, the scanning signal lines in the second half of the array substrate are driven in sequence. When only the first half of the array substrate is selected, the switch 835 is turned on and the switch 836 is turned off. When only the second half of the array substrate is selected, the switch 835 is turned off and the switch 836 is turned on.

  It is not always necessary to use a gate driver as described above, and any hardware may be used as long as it can drive one or more desired scanning signal lines.

  In the above, four methods are exemplified as the defective address specifying method, but other methods may be adopted.

  In the two-pixel simultaneous measurement method described above, as shown in FIG. 15, first, the scanning signals G1 and G513 are simultaneously activated while the data signal DT is applied in order to write the data signal DT to the two pixels. . Next, in order to read the data signal DT from the two pixels, the scanning signals G1 and G513 are simultaneously activated. The read data signal DT is integrated, and the charge amount for the two pixels is measured.

  On the other hand, in another defective address specifying method, when the two-pixel simultaneous measurement method is performed as the first inspection, the data signal DT is first written to the two pixels as shown in FIG. While the signal DT is applied, the scanning signals G1 and G513 are sequentially activated one by one. Next, in order to read out the data signal DT from the two pixels, the scanning signals G1 and G513 are activated one by one in order. By doing so, first, the data signal DT is read from the first pixel, and then the data signal DT is read from the second pixel. These data signals DT are continuously integrated. Therefore, if the integral value is acquired at time T1, the charge amount for one pixel can be measured. If the integral value is acquired at time T2, the charge amount for two pixels can be measured.

  In the first inspection, as described above, the quality of the two pixels is collectively determined based on the measured charge amount for the two pixels. In the re-inspection, only two pixels determined to be defective are targeted, and the quality of the one pixel is determined based on the measured charge amount for one pixel. Thus, by determining which of the two pixels is defective, the address of the defective pixel can be specified. Therefore, it is not necessary to rescan the array substrate as in the four address identification methods described above.

  As shown in FIG. 17, the inspection apparatus for realizing this defective address specifying method includes two sample and hold (S & H) circuits 11 and 12 connected to each data signal line 1. The sample hold circuit 11 samples and holds the charge amount for one pixel at time T1 when the scanning signal G1 is inactivated. The sample hold circuit 12 samples and holds the charge amount for two pixels at time T2 when the scanning signal G513 is inactivated. Both the charge amount data for one pixel and the charge amount data for two pixels are stored in the memory 13. In the two-pixel simultaneous measurement method, which is the first inspection, only charge amount data for two pixels is transferred to the PC, and pass / fail is determined based on this. The charge amount data for the remaining one pixel is not transferred to the PC until the address of the defective pixel is specified from the two pixels.

  Since the current array tester secures a fixed time as a writing and reading cycle, the inspection time does not increase even if the two scanning signal lines 2 are driven one by one within that time. Further, since only the measured charge amount for two pixels is transferred to the PC and the quality is determined, the charge amount measurement time does not become longer than the above case.

  It is ideal to drive the scanning signal line at the timing shown in FIG. 16, but in actuality, due to capacitive coupling between the scanning signal line and the data signal line, as shown in FIG. Noise may enter the data signal DT at the time of activation T1. When such noise enters, the measured value of the charge amount becomes unstable.

  Therefore, in order to exclude such noise, as shown in FIG. 19, the scanning signal G1 may be continuously activated even after the scanning signal G513 is activated. In this case, the amount of charge for one pixel sampled and held at time T1 includes the coupling capacitance between the scanning signal line and the data signal line. However, since the two-pixel simultaneous measurement method, which is the first inspection, compares the measured charge amount with the charge amount measured at several neighboring pixels, the accuracy of pass / fail judgment is ensured.

  This inspection method does not drive two scanning signal lines at the same time. However, since the charge amount of two pixels is measured together, the two scanning signal lines are simultaneously inspected. Absent.

  In the above, an array substrate using a three-terminal element such as a TFT as a pixel switching element has been exemplified, but the present invention can also be applied to an array substrate using two terminals such as a diode. Further, the present invention can be applied not only to the active matrix type but also to a simple matrix type liquid crystal display device. Further, the present invention is not limited to the liquid crystal display device and can be applied to any array substrate having a plurality of signal lines.

  While the embodiments of the present invention have been described above, the above-described embodiments are merely examples for carrying out the present invention. Therefore, the present invention is not limited to the above-described embodiment, and can be implemented by appropriately modifying the above-described embodiment without departing from the spirit thereof.

  The present invention can be used for inspection of an array substrate having a plurality of signal lines, and in particular, can be used for inspection of an array substrate of an active matrix liquid crystal display device.

It is a functional block diagram which shows the structure of the matrix type liquid crystal display device used as the object of the test | inspection method by embodiment of this invention. It is a conceptual diagram which shows the method of test | inspecting by the 2 pixel simultaneous measurement method first as a test | inspection method by embodiment of this invention, and then reinspecting by the defect candidate pixel separate measurement method. It is a conceptual diagram which shows the 2 pixel simultaneous measuring method shown in FIG. It is a circuit diagram which shows the test | inspection apparatus used with the 2 pixel simultaneous measuring method shown in FIG. It is a graph which shows the defect pixel number dependence of the test | inspection time by the conventional 1 pixel sequential measurement method, 2 pixel simultaneous measurement method, and 3 pixel simultaneous measurement method. FIG. 5 is a conceptual diagram showing a method of inspecting first by a two-pixel simultaneous measurement method and then re-inspecting by a three-pixel simultaneous measurement method as a defective address specifying method as another inspection method according to an embodiment of the present invention. (A) is a figure which shows the pixel of a defect candidate by the result of the 2 pixel simultaneous measurement method, (b) is a figure which shows the pixel of the defect candidate by the result of the 3 pixel simultaneous measurement method. A conventional method of inspecting with a one-pixel sequential measurement method, a method of first inspecting with a two-pixel simultaneous measurement method and re-inspecting with a three-pixel simultaneous measurement method, and a method of first inspecting with a three-pixel simultaneous measurement method and simultaneously measuring four pixels It is a graph which shows the defect pixel number dependence of the inspection time by the method of re-inspecting by a method. It is a conceptual diagram which shows the method of reinspecting with the one-side two pixel simultaneous measuring method as another defective address identification method by embodiment of this invention. It is a flowchart which shows the switching method of the defect candidate pixel separate measurement method and the several pixel simultaneous measurement method as another defect address identification method by embodiment of this invention. 11 is a graph showing the dependency of the inspection time on the number of defective pixels by the conventional method of inspecting by the one-pixel sequential measurement method and the switching method shown in FIG. FIG. 2 is a functional block diagram illustrating a configuration of a scanning signal line driving circuit illustrated in FIG. 1. FIG. 13 is a timing chart showing an operation of the gate driver shown in FIG. 12 by the two-pixel simultaneous measurement method shown in FIG. 3. FIG. 4 is a functional block diagram showing another configuration of a gate driver for realizing the two-pixel simultaneous measurement method shown in FIG. 3. FIG. 4 is a timing diagram illustrating a scanning signal and a data signal according to the two-pixel simultaneous measurement method illustrated in FIG. 3. FIG. 4 is a timing diagram showing a scanning signal and a data signal when the two-pixel simultaneous measurement method shown in FIG. 3 is performed as still another defective address specifying method according to the embodiment of the present invention. It is a functional block diagram which shows the structure of the test | inspection apparatus for implement | achieving the 2 pixel simultaneous measuring method shown in FIG. FIG. 17 is a timing chart for explaining a problem of the two-pixel simultaneous measurement method illustrated in FIG. 16. FIG. 19 is a timing diagram illustrating a scanning signal and a data signal according to the two-pixel simultaneous measurement method that solves the problem illustrated in FIG. 18. It is a conceptual diagram which shows the 1 pixel sequential measuring method which is the conventional inspection method of an array substrate. It is a circuit diagram which shows the test | inspection apparatus used with the 1 pixel sequential measurement method shown in FIG.

DESCRIPTION OF SYMBOLS 1 Data signal line 2 Scan signal line 3 Pixel 4 Detection circuit 7 Data signal line drive circuit 8 Scan signal line drive circuit 10 Array substrate 10A-10G Inspection block

Claims (2)

An inspection apparatus for inspecting an array substrate having a plurality of data signal lines, a plurality of scanning signal lines intersecting the data signal lines, and a plurality of elements corresponding to intersections of the data signal lines and the scanning signal lines. And
Drive means for driving N ₁ (an integer greater than or equal to 2) scanning signal lines among the scanning signal lines;
Detecting means for detecting data signals read from the corresponding N ₁ elements to the respective data signal lines by driving the N ₁ scanning signal lines;
The driving means detects N ₂ (two or more integers different from N ₁ ) scanning signals among the scanning signal lines after the data signals read from the N ₁ elements are detected by the detecting means. Drive the line,
The N ₁ scanning signal lines and the N ₂ scanning signal lines have a common scanning signal line,
It said detecting means detects a data signal read out to each of said data signal lines from the corresponding N ₂ pieces of element by driving the N ₂ scanning signal lines,
The N _one scanning signal lines are simultaneously inspected by driving the N _one scanning signal lines by the driving means and detecting a data signal read from the N _one elements by the detecting means ,
The N ₂ scanning signal lines are simultaneously inspected by driving the N ₂ scanning signal lines by the driving unit and detecting a data signal read from the N ₂ elements by the detecting unit. An inspection apparatus for an array substrate. An inspection apparatus for inspecting an array substrate having a plurality of data signal lines, a plurality of scanning signal lines intersecting the data signal lines, and a plurality of elements corresponding to intersections of the data signal lines and the scanning signal lines. And
Driving means for driving two of the scanning signal lines;
Detecting means for detecting a data signal read to each of the data signal lines from two corresponding elements by driving the two scanning signal lines;
The drive means re-drives one of the two driven scanning signal lines after the data signal read from the two elements is detected by the detection means , and does not re-drive the other,
The detecting means detects a data signal read to each of the data signal lines from one corresponding element by re- driving the one scanning signal line ,
The two scanning signal lines are simultaneously inspected by driving the two scanning signal lines by the driving unit and detecting a data signal read from the two elements by the detecting unit,
The one scanning signal line is re-inspected by re-driving the one scanning signal line by the driving unit and detecting a data signal read from the one element by the detecting unit. Array substrate inspection device.

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