JP5338089B2 - Charge erase method - Google Patents

Description

  The present invention relates to a charge erasing method, and more particularly to a charge erasing method using a charge erasing apparatus that moves and erases charges inside a wafer by applying charges to a substrate using an ionizer.

  A semiconductor element may be broken even when charged by a very small amount of charge, and countermeasures against static electricity are a major issue in the semiconductor manufacturing process. Conventionally, in a semiconductor manufacturing process, a method of erasing charges on a wafer surface by an ionizer (for example, refer to Patent Document 1) or a method of erasing charges by irradiating a wafer with ultraviolet rays and transmitting the ultraviolet rays through the film (for example, Patent Document 2) is known.

  FIG. 2 shows a wafer rotation processing apparatus having a function of neutralizing charges on a wafer surface by a conventional ionizer. In FIG. 2, the wafer rotation processing apparatus 11 includes a cylindrical container 12, a wafer support unit 14, and a discharge unit (not shown). A wafer support 14 is provided in the cylindrical container 12. Wafer 4 is supported on wafer support 14 by vacuum suction. Moreover, the discharge part is provided in the position where a chemical | medical solution and a pure water can be dripped at the wafer surface 4a. The processing apparatus 11 further includes an ion generation unit 18 that generates ions in the atmosphere, and ions generated from the ion generation unit 18 reach the wafer surface 4a supported by the wafer support unit 14. . When liquid is dropped from the discharge unit onto the wafer surface 4a and the wafer support unit 14 is rotated at a rotation speed of 1000 to 6000 rpm, the wafer surface 4a is charged with positive static electricity. Therefore, a negative voltage is applied to the ion generation unit (that is, the needle electrode) 18 by the power supply unit 20.

  As a result, the atmosphere around the needle electrode 18 is ionized and corona discharge occurs. This corona discharge generates positive ions 19a and negative ions 19b. Of the generated ions, most of the positive ions 19 a gather around the needle-like electrode 18. Then, the negative ions 19b are carried to the wafer surface 4a by the down flow. Since the wafer surface 4a is positively charged by static electricity, the negative ions 19b that have been transported and the positive ions on the wafer surface 4a combine to eliminate the charge. Thereby, static electricity generated on the wafer surface 4a can be removed. However, in this method, only static electricity on the wafer surface 4a can be removed, and charges accumulated in the wafer 4 in the wafer manufacturing process cannot be removed.

On the other hand, in the conventional method of irradiating ultraviolet rays, charges accumulated in the wafer such as an oxide film and a passivation film can be removed by transmitting the ultraviolet rays inside the wafer. However, due to the characteristics of the film, particularly the difference in absorption edge wavelength, the ultraviolet rays may not be sufficiently transmitted, and charge erasure may be incomplete. Therefore, by providing flat electrodes on the top and bottom of the wafer in addition to the ultraviolet irradiation means and generating an electric field between the flat electrodes, the charge in the passivation film is moved to the surface of the passivation, and then the surface is irradiated with ultraviolet rays. Charges can be erased with certainty (see, for example, Patent Document 2).

  FIG. 3 shows an electrostatic eraser disclosed in Patent Document 3. In order to erase the static electricity charged on the wafer 4 having the passivation film 3 formed on the silicon substrate 1 through the semiconductor circuit film 2 including the insulating film, the upper electrodes 6 for applying a high electric field are formed on both upper and lower sides of the wafer 4. And the lower electrode 7 are provided in a pair of parallel plate electrodes. The wafer 4 is placed on the lower electrode 6. The upper electrode has a slit shape, and ultraviolet rays from the mercury lamp 5 installed above the upper electrode can reach the wafer 4 without being obstructed by the upper electrode 6. The charges in the passivation film 3 are moved to the surface of the passivation film 3 by the electric field generated by the upper electrode 6 and the lower electrode 7, and the charges are erased by being irradiated with ultraviolet rays there. However, since there is a distance between the upper electrode 6 and the lower electrode 7 in this method, the electric field strength generated between the electrodes is small, and the speed at which the charge accumulated in the wafer 4 moves to the surface of the passivation film 3 is increased. In this case, a long process is required to sufficiently remove the charges inside the wafer.

Further, in order to increase the movement speed of charges inside the wafer 4, it is necessary to apply a large voltage to the upper electrode 6 and the lower electrode 7, which increases the power consumption and increases the running cost. Furthermore, since an expensive mercury lamp 5 is used to remove the charges that have finally moved to the surface of the passivation film 3, the apparatus price increases, and the mercury lamp 5 also consumes a large amount of power and requires a running cost.
JP 2001-77006 A Japanese Patent Laid-Open No. 9-69478 JP 62-44995 A

The first problem in the above-described prior art is that a long processing time is required to sufficiently remove the charges inside the wafer. The reason is that since there is a distance between the upper electrode and the lower electrode, the electric field strength generated between the electrodes is small, and the speed at which the charge accumulated in the wafer moves to the surface of the wafer cannot be increased.
The second problem is that the apparatus cost and running cost are required. This is because it is necessary to apply a large voltage to the upper electrode and the lower electrode in order to increase the movement speed of electric charges inside the wafer, resulting in increased power consumption and running cost. Furthermore, since an expensive mercury lamp is used to finally remove the charges that have moved to the surface of the wafer, the price of the apparatus increases, and even the mercury lamp consumes a large amount of power and requires a running cost.
The present invention has been made under such circumstances, and a first object of the present invention is to provide a charge erasing apparatus that removes charges on the wafer surface and inside at high speed. A second object of the present invention is to provide a charge erasing apparatus that removes charges on the wafer surface and inside at a low cost.

To achieve the above object, according to the present invention, a first ionizer that blows ions to the upper surface side of a semiconductor substrate, a second ionizer that blows ions to the lower surface side of the semiconductor substrate, and a heater that heats the semiconductor substrate. The first ionizer and the second ionizer have means for controlling the potential of the surface of the semiconductor substrate, and the heater is outside the ion spray region of the first ionizer or the second ionizer. In the charge erasing method using the charge erasing device disposed in the substrate, after the semiconductor substrate is heated to a predetermined temperature, the second ionizer applies a charge to the surface on the lower surface side of the semiconductor substrate and charges the surface. The first ionizer erases the charge on the upper surface of the semiconductor substrate, and the second ionizer then removes the electric charge on the lower surface of the semiconductor substrate. Charge erasing method characterized by erasing the charge of the surface is provided.

  The first effect of the present invention is that ions are blown from the top and bottom of a semiconductor substrate by an ionizer, and the front and back of a thin wafer are charged with charges having different signs, so that a strong electric field is generated inside the wafer. The movement of the charge is accelerated by acting on the whole charge, and the movement of the charge is further accelerated by heating the wafer by the heater, so that the charge on the wafer surface and inside can be removed at high speed. The second effect is that the use of an ionizer that is lower in cost and lower in power consumption than a mercury lamp makes it possible to remove charges on the wafer surface and in the interior at a low cost.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[First Embodiment]
FIG. 1 is a schematic diagram of a charge erasing device according to a first embodiment of the present invention. The charge erasing apparatus shown in FIG. 1 includes a first ionizer 101 disposed on the upper side of a wafer 4 with respect to a wafer 4 composed of a silicon substrate 1, a semiconductor circuit film 2 including an insulating film, and a passivation film 3. In order to install the wafer 4 on the heat plate 105, the second ionizer 102 installed on the lower side of the wafer 4, the heat plate 105 that does not interfere with the ion spraying range 102 d of ions sprayed by the second ionizer 102. Insulating support pins 103. As the ion generator of the ionizer, for example, the conventional one described in FIG. 2 can be used.

  The first ionizer 101 includes ionizer electrodes and nozzles 101a for blowing ions together with air, an upper surface electrometer 101b for measuring the surface potential of the wafer 4, and ions ejected from the ionizer based on the values of the upper surface electrometer 101b. And an upper potential control unit 101c for controlling the amount. The second ionizer 102 ejects the ionizer based on the values of the ionizer electrode and nozzle 102a for blowing ions together with air, the lower surface potential meter 102b for measuring the surface potential of the wafer 4, and the lower surface potential meter 102b. And a lower potential control unit 102c for controlling the amount of ions. The insulating support pins 103 are formed of an insulating material such as plastic so that the electric charges of the wafer 4 charged by the first ionizer 101 and the second ionizer 102 do not escape to the heat plate 105, The wafer 4 is supported with a minimum contact area so as not to be contaminated with metal.

  The heat plate 105 heats the wafer 4 to a predetermined temperature uniformly without contact. For example, by heating the wafer 4 at a temperature higher than 100 ° C., the charge movement in the wafer 4 is promoted, and the charge can be neutralized effectively. The heat plate 105 has an opening 105a near the center, and is configured such that ions blown from the second ionizer 102 are blown to the lower surface of the wafer 4 through the opening 105a. Therefore, the opening 105 a is configured to have a size that includes the ion spraying range 102 d sprayed from the second ionizer 102.

Next, the operation of the charge erasing device of the present embodiment will be described with reference to FIGS. 1 and 5 and the charge erasing method will be described. FIG. 5 is a flowchart showing a charge erasing method using this charge erasing apparatus.
First, the temperature of the heat plate 105 is heated so that the temperature of the semiconductor substrate (wafer) 4 becomes a predetermined temperature (step (1)). Next, when the passivation film 3 is negatively charged, negative ions are blown against the lower surface of the silicon substrate 1 by the lower second ionizer 102. The amount of negative ions to be sprayed is controlled by the lower potential control unit 102c by measuring the surface potential of the lower surface of the silicon substrate 1 using the lower surface potential meter 102b in the second ionizer 102. At this time, the silicon substrate 1 is charged with more negative charges than the negative charge amount in the passivation film 3. Since the silicon substrate 1 is supported by the support pins 103 made of an insulating material, the charged negative charges are accumulated in the silicon substrate 1. Accordingly, an electric field is generated from the upper surface of the passivation film 3 toward the silicon substrate 1 inside the passivation film 3. Therefore, the negative charges accumulated in the passivation film 3 are moved to the upper surface side of the passivation film 3 due to the influence of the electric field (step (2)).

  Next, using the first ionizer 101 on the upper side, positive ions are sprayed on the upper surface of the passivation film 3 to attract negative charges to the surface of the passivation film 3 and neutralize the collected negative charges. The amount of negative ions to be sprayed is controlled by the upper surface potential control unit 101c by measuring the surface potential of the upper surface of the passivation film 3 with the upper surface potential meter 101b (step (3)). Next, positive ions are blown from the second ionizer 102 to the lower surface of the silicon substrate 1 to neutralize the charge of the silicon substrate 1 (step (4)).

  As described above, the charge inside the wafer is attracted to the wafer surface by applying charges different from those inside the wafer to the wafer surface by the ionizers provided at the top and bottom of the wafer, and the same charge as that inside the wafer is attracted to the wafer surface. A sign charge is applied. As a result, the internal potential of the wafer can be gradually changed toward the potential below the wafer that exceeds the ground potential, so that the internal charges can be moved and removed faster than in the prior art. The charge applied to the lower surface of the wafer is finally neutralized by the lower second ionizer. In addition, since an ionizer that is lower in cost and lower in power consumption than a mercury lamp is used, it is possible to remove charges on the wafer surface and in the interior at a low cost.

Next, a case where the passivation film 3 of the wafer (semiconductor substrate) 4 is positively charged will be described.
In step (2), positive ions are sprayed onto the lower surface of the silicon substrate 1 by the second ionizer 102 below the wafer. Next, in step (3), negative ions are sprayed on the upper surface of the passivation film 3 using the upper first ionizer 101 to attract positive charges to the surface of the passivation film 3 and neutralize the collected positive charges. To do. Next, negative ions are blown from the second ionizer 102 to the lower surface of the silicon substrate 1 to neutralize the charge on the silicon substrate 1 (step (4)).

As described above, in the first embodiment, in step (2), a charge is applied to the lower surface of the semiconductor substrate by the second ionizer and charged, and in step (3), the charge on the upper surface of the semiconductor substrate is erased by the first ionizer ( In step (4), the second ionizer erases the charge on the lower surface of the semiconductor substrate. However, the following process can also be used. That is, in step (2), a charge is applied to the upper surface of the semiconductor substrate by the first ionizer and charged, and in step (3), the charge on the lower surface of the semiconductor substrate is erased (neutralized) by the second ionizer. In 4), a process of erasing charges on the upper surface of the semiconductor substrate by the first ionizer is used.
In this embodiment, the number of ionizer electrodes and nozzles 101a of the upper first ionizer 101 is singular, but may be plural. Further, the number of ionizer electrodes and nozzles 102a of the second ionizer 102 on the lower side is one, but a plurality may be used.

[Second Embodiment]
Next, a second embodiment will be described with reference to FIG.
FIG. 4 is a diagram schematically showing the charge erasing device according to the second embodiment of the present invention.
In the charge erasing apparatus of this embodiment, a first ionizer 101 installed on the upper side of the wafer, a second ionizer 102 installed on the lower side of the wafer, and an ion spraying range 102d with respect to the wafer (semiconductor substrate) 4. The base 104 that is not interfered with, the insulating support pins 103 for placing the wafer 4 on the base 104, and the lamp heating unit 110 that heats the wafer 4 are configured.
The upper first ionizer 101 ejects the ionizer based on the values of the ionizer electrode and nozzle 101a that blows ions together with air, the upper surface potential meter 101b that measures the surface potential of the wafer 4, and the upper surface potential meter 101b. The upper potential control unit 101c controls the amount of ions.

The lower second ionizer 102 is an ionizer based on the values of an ionizer electrode and nozzle 102a for blowing ions together with air, a lower surface potential meter 102b for measuring the surface potential of the wafer 4, and a lower surface potential meter 102b. And a lower potential control unit 102c for controlling the amount of ions ejected by the.
The insulating support pins 103 are formed of an insulating material so that the charges of the wafer 4 charged by the first ionizer 101 and the second ionizer 102 do not escape to the base 104, and the back surface of the wafer 4 is contaminated with dust or metal. The wafer 4 is supported with a minimum contact area.
The lamp heating unit 110 rapidly heats the wafer 4 in a non-contact manner, and includes a reflector 110a, a lamp 110b, a temperature control unit 110c, and a radiation thermometer 110d, and controls the temperature of the wafer 4. To do.

The operation of the charge erasing device of the second embodiment is the same as that of the first embodiment.
As described above, ions are blown from the top and bottom of the wafer by the ionizer, and the front and back surfaces of the thin wafer are charged with different signs of electric charge. As a result, a strong electric field is generated inside the wafer, acting on the electric charge in the entire substrate and moving the charge. Since the wafer is heated and the movement of charges is further accelerated by heating the wafer, the charges on the wafer surface and inside can be removed at high speed. In addition, since an ionizer that is lower in cost and lower in power consumption than a mercury lamp is used, it is possible to remove charges on the wafer surface and in the interior at a low cost. In addition, the wafer can be rapidly heated by using a lamp as the heating means.

As described above, in the second embodiment, the lamp heating unit 110 heats the upper surface of the passivation film 3, but may heat the lower surface of the silicon substrate 1. Moreover, although the ionizer electrode and the nozzle 101a of the 1st ionizer 101 were single, multiple may be sufficient. Moreover, although the ionizer electrode and the nozzle 102a of the 2nd ionizer 102 were single, multiple may be sufficient. Moreover, although the lamp heating unit 110 was single, multiple may be sufficient.
In the above description, the case where the passivation film 3 is negatively charged has been described. However, when the passivation film 3 is positively charged, the second ionizer 102 first sprays ions on the lower surface of the silicon substrate 1. Is also a positive ion.

1 is a configuration diagram of a charge erasing device according to a first embodiment of the present invention. Sectional drawing of the conventional charge erasing apparatus. Sectional drawing of the conventional charge erasing apparatus. The block diagram of the charge erasing apparatus which concerns on the 2nd Embodiment of this invention. The flowchart which shows the charge erasing method using the charge erasing apparatus of the 1st Embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Semiconductor circuit film containing an insulating film 3 Passivation film 4 Wafer (semiconductor substrate)
101 First ionizer 101a Ionizer electrode and nozzle 101b Upper surface potential meter 101c Upper potential control unit 101d Ion spray range 102 Second ionizer 102a Ionizer electrode and nozzle 102b Lower surface potential meter 102c Lower potential control unit 102d Ion spray range 103 Insulating Support Pin 104 Base 105 Heat Plate 105a Heat Plate Opening 110 Lamp Heating Unit 110a Reflector 110b Lamp 110c Temperature Control Unit 110d Radiation Thermometer 110e Radiation Area

Claims (4)

A first ionizer that blows ions to the upper surface side of the semiconductor substrate; a second ionizer that blows ions to the lower surface side of the semiconductor substrate; and a heater that heats the semiconductor substrate, the first ionizer and the second ionizer The ionizer has means for controlling the potential of the surface of the semiconductor substrate, and the heater is a charge erasing method using a charge erasing device arranged outside the ion spraying region of the first ionizer or the second ionizer. Then, after the semiconductor substrate is heated to a predetermined temperature, an electric charge is applied to the surface on the lower surface side of the semiconductor substrate with the second ionizer to charge the surface, and then the surface on the upper surface side of the semiconductor substrate with the first ionizer. The charge on the lower surface of the semiconductor substrate is erased by the second ionizer. Method. The first ionizer has a plurality of electrodes and nozzles for blowing ions on the upper surface side of the semiconductor substrate, and the second ionizer has a plurality of electrodes and nozzles for blowing ions on the lower surface side of the semiconductor substrate. The charge erasing method according to claim 1, wherein: The charge erasing method according to claim 1, wherein the semiconductor substrate is placed on the heater via an insulating support pin. The heater is in a plate shape having an opening, and is disposed between the second ionizer and the semiconductor substrate, and ions blown from the second ionizer pass through the opening and the lower surface of the semiconductor substrate. The charge erasing method according to claim 3, wherein the charge erasing method is sprayed on a side surface.

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