JP5338445B2 - Pulse booster and output voltage control circuit - Google Patents

Description

  The present invention relates to a pulse booster circuit and an output voltage control circuit that reduce fluctuations in output voltage.

The pulse booster circuit is built in an LSI (Large Scale Integrated circuit) and is often used in a power supply voltage conversion circuit that supplies power to the LSI internal circuit.
In recent LSIs, a plurality of power supply voltages such as 3 V, 5 V, 10 V, and 20 V are required for the power supply of the LSI internal circuit, and a higher voltage than the power supply voltage supplied from the outside to the LSI is required. Often needed. Conventionally, when such a plurality of power supply voltages are required, a plurality of power supply voltages are generated outside the LSI and supplied to the LSI. However, recently, there is a tendency that the power supply voltage supplied to the LSI is a single power supply voltage, and a plurality of required power supply voltages are generated in the LSI based on a single power supply voltage input from outside the LSI. Is required to be generated in
In addition, in a device applied to a mobile application to be carried and used, the power source of the device is generally driven by a battery, and the device is required to be small and light in combination with the battery. For this reason, there is an increasing demand for lowering the power supply voltage for battery-powered power supplies.

JP 2004-222396 A

  By the way, in a power source generated by an external power source, it is easy to perform smoothing with a capacitor or the like for reducing a minute voltage fluctuation superimposed on an output voltage, that is, a ripple voltage. In a circuit configured in an LSI, it is difficult to secure a capacitor capacity inside the LSI, and even if a capacitor is separately mounted outside the LSI, the mounting capacity increases, which is not practical.

Further, in the conventional technique, the following method is used as a method for suppressing the amplitude of a minute voltage fluctuation superimposed on the output voltage of the pulse booster circuit built in the LSI.
As a first method, there is a method of distributing the output power by dividing the configuration of the pulse booster circuit.
For example, a configuration in which the pulse booster circuit 300 is divided into a plurality of components such as the pulse booster circuits 301 to 303 is conceivable as compared with the configuration in which the pulse booster circuit 200 illustrated in FIG. In this method, the load current per one pulse booster circuit can be reduced as in the divided pulse booster circuit 301, and the ripple voltage per individual pulse booster circuit can be reduced. However, when the number of divisions of the pulse booster circuit is increased, a number of pulse booster circuits that require a large mounting area are arranged in the same LSI. As a result, the layout area of the LSI increases and a lot of dead space is generated on the layout, which increases the cost of the LSI.

  As a second method, in a pulse booster circuit connected in multiple stages, there is a method of shifting the timing (phase) at which each pulse booster circuit (PUMP2) operates using a delay circuit (see FIG. 9).

In this method, voltage fluctuations depending on the timing at which the individual pulse booster circuits are operated can be dispersed in the time axis direction, and an increase in voltage fluctuation width due to concentration of operations at the same timing can be reduced.
However, there is a problem that the timing of the voltage fluctuation generated by the operation of the pulse booster circuit is merely dispersed, and the amount of voltage fluctuation generated is not fundamentally reduced.

Hereinafter, an example of a pulse booster circuit using a conventional technique will be shown, and the problem of voltage fluctuation generated from each pulse booster circuit will be described.
FIG. 10 is a block diagram showing a configuration example of a conventional pulse booster circuit.
This figure shows a pulse booster circuit 200 that outputs a signal PUMPOUT having a boosted voltage by performing a boosting operation based on input clocks CLK1 to CLK3.
The pulse booster circuit 200 includes a clock signal control unit 10b, a voltage conversion unit 20, and a determination unit 40.

The determination unit 40 in the pulse booster circuit 200 operates as a hysteresis type comparator that divides the voltage output from the voltage conversion unit 20 and determines the voltage based on a predetermined comparison voltage. The determination unit 40 outputs the “L (low)” level when the voltage of the input signal is lower than the reference, and outputs the “H (high)” level when the voltage is high.
The clock signal control unit 10b controls whether or not each of the input clocks CLK1 to CLK3 is output based on the control signal PUMPEb. Further, the clock signal control unit 10b generates and outputs an inverted signal CLK02B corresponding to the clock CLK2. The clock signal control unit 10b outputs each clock when the control signal PUMPEb is at “H (high)” level.
The voltage converter 20 outputs a boosted voltage based on the input clock. The voltage conversion unit 20 includes a voltage conversion unit 20a and a voltage conversion unit 20b having the same circuit configuration. Based on the input clock, the voltage boosting operation and the charging operation for the capacitor which are repeatedly performed are reversed by 180 degrees and reversed. The phase is That is, the voltage conversion unit 20a and the voltage conversion unit 20b are supplied with clocks CLK2 and a clock obtained by inverting the clock CLK2, respectively, and perform phase switching. A configuration example of the voltage conversion unit 20 will be described with reference to FIG.

The voltage conversion unit 20 illustrated in FIG. 11 includes a voltage conversion unit 20b having the same configuration as the voltage conversion unit 20a. A configuration example of the voltage conversion units 20a and 20b will be described on behalf of the voltage conversion unit 20a.
The voltage converter 20a includes a clock buffer 22, a field effect transistor (FET) 28, and charge pumps 31 and 32.
The clock buffer 22 in the voltage conversion unit 20a outputs an inverted clock of the input clock CLK02. The FET 28 functions as a diode connected to the power supply VDD and supplies power to the charge pump 31.
The charge pump 31 includes a voltage doubler circuit 21, an FET 24, an FET 29, and a capacitor 26.
The voltage doubler circuit 21 in the charge pump 31 outputs a voltage (referred to as “voltage 2VDD”) approximately twice the power supply voltage based on the input clock. The voltage doubler circuit 21 charges the capacitor 26 with the voltage 2VDD output in accordance with the input clock. The FET 24 charges the capacitor 26 with the power supply voltage VDD when the voltage output from the voltage doubler circuit 21 is not output depending on the phase of the input clock. Thus, the voltage 2VDD and the power supply voltage VDD are switched according to the phase of the input clock, thereby repeating the boosting operation, and the boosted voltage is output via the FET 29.

The charge pump 32 includes a voltage doubler circuit 23, an FET 25, an FET 30, and a capacitor 27.
The voltage doubler circuit 23 in the charge pump 32 outputs a voltage (referred to as “voltage 2VDD”) approximately twice the power supply voltage based on the input clock. The voltage doubler circuit 23 charges the capacitor 27 with the voltage 2VDD output in accordance with the input clock. The FET 25 charges the capacitor 27 with the power supply voltage VDD when the voltage output from the voltage doubler circuit 23 is not output depending on the phase of the input clock. Thus, the voltage 2VDD and the power supply voltage VDD are switched according to the phase of the input clock, thereby repeating the boosting operation, and the boosted voltage is output via the FET 30.
The charge pump 32 is connected to the subsequent stage of the charge pump 31 described above, and is boosted by the charge pump 31. The charge pump 32 further adds a voltage boosted by the charge pump 32 itself to the output voltage.

The voltage doubler circuits 21 and 23 are different in input signal, but the same configuration can be applied to the internal configuration. A configuration example of the voltage doubler circuits 21 and 23 will be described as a representative of the voltage doubler circuit 21.
FIG. 12 is a block diagram illustrating an example of the voltage doubler circuit 21.
The voltage doubler circuit 21 includes a capacitor 211 and FETs 212, 213 and 214. The capacitor 211 is charged to the power supply voltage VDD via the FET 212 when the clock CK1 input from the terminal TB221 is at “L” level. When the clock CK1 changes to the “H” level, a voltage 2VDD obtained by adding the amplitude of the clock CK1 (referred to as the power supply voltage VDD) and the previously charged power supply voltage VDD is generated on the source side of the FET 212. Further, a switch is configured in combination with the FET 213 and the FET 214. When the clock CK <b> 2 input from the terminal TB <b> 222 is “H” level, the terminal voltage of the terminal TB <b> 223 becomes the ground potential via the FET 214. When the clock CK <b> 2 input from the terminal TB <b> 222 is at “L” level, the terminal voltage of the terminal TB <b> 223 becomes the voltage 2VDD generated at the terminal of the capacitor 211 via the FET 213.
As described above, in the voltage doubler circuit 21, the ground potential and the voltage 2VDD are alternately repeated as the voltage output according to the states of the FET 213 and the FET 214.

  The clock CLK01 synchronized with the clock CLK1 (FIG. 10) is input to the TB 201a of the voltage conversion circuit 20a and the TB 203b of the voltage conversion circuit 20b, and the clock CLK2 (FIG. 10) is in phase with the TB 202a of the voltage conversion circuit 20a. The clock CLK02 (inverted from the clock CLK2 (FIG. 10) is input to the TB 202b of the voltage conversion circuit 20b, and the clock CLK3 (to the TB 203a of the voltage conversion circuit 20a and the TB 201b of the voltage conversion circuit 20b are input A clock CLK03 synchronized with FIG. 10) is input. As a result, it is possible to easily switch charging and output of the boosted voltage according to the respective phases in combination.

  With the configuration described above, in the pulse booster circuit 200, the determination unit 40 detects the voltage output from the voltage conversion unit 20, and outputs the control signal PUMPEb based on the detection result. The clock signal control unit 10 is controlled by the input control signal PUMPEb, and supplies each clock to the voltage conversion unit 20 when it is determined that the voltage output from the voltage conversion unit 20 is low.

  FIG. 13 is a timing chart showing the operation of the pulse booster circuit 200. Of the input clocks CLK1 to CLK3, the clock CLK2B obtained by inverting the clock CLK2, and the signal PUMPOUTb output to the terminal TB104, waveforms output from the charge pump 20a side are shown. The signal PUMPOUTb output to the terminal TB104 of the pulse booster circuit 200 is a waveform obtained by adding the waveform output from the charge pump 20b side not shown in this figure. In the phase where the voltage of the signal PUMPOUTb shown in this figure is not output, there is an output from the charge pump 20b side, and an interpolated voltage is output.

  Focus on the phase of the clock CLK2. If time t22 is used as a reference for the phase of clock CLK2, one cycle is 180 degrees at time t24 and 360 degrees at time t27. From the time t22 to t24 when the clock CLK2 is at the “H” level, the phase from 0 degrees to 180 degrees as indicated by the phase is the period output from the charge pump 20a side, and the time t24 at which the clock CLK2 is at the “L” level. From t to t27, the phase from 180 degrees to 380 degrees in terms of the phase is the period output from the charge pump 20b side. The boosting operation is repeated with the cycle corresponding to the clock CLK2.

  In addition, the waveform of the signal PUMPOUTb output to the terminal TB104 changes even during a period in which the clock CLK2 is at the “H” level. The period T1 (from time t23 to t24) until the clock CLK1 corresponding to the first half of the period in which the clock CLK2 indicates the “H” level becomes the “H” level, and the period T2 in which the clock CLK1 corresponding to the second half indicates the “H” level. It is shown that a voltage lower than the voltage (from time t23 to t24) is output.

Thus, even if the pulse booster circuit 200 is controlled by the continuous clocks CLK1 to CLK3, it is observed that the voltage fluctuation varies when the waveform of the signal PUMPOUTb output from the pulse booster circuit 200 is observed.
FIG. 14 is a diagram illustrating the operation of the pulse booster circuit 200, and shows a waveform obtained by observing a voltage change of the signal PUMPOUTb output from the terminal Tb104.
In the pulse booster circuit 200 shown in this figure, when the reference voltage is set to 7 V (volts) and it is determined that the voltage (VCPb) of the signal PUMPOUTb is lower than the reference voltage, the boosting operation is resumed. When it is determined by the boost operation that the reference voltage has been reached, the clocks CLK1 to CLK3 for performing the boost operation are controlled to stop the boost operation of the voltage converter 20. For this reason, when the boosting operation is stopped, the charge accumulated in the capacitor is discharged from the output voltage, and a state in which the voltage gradually decreases accordingly (triangular wave descending to the right) can be observed. Here, comparing the voltage fluctuations at time t43 and time t53, it is 0.14 V (volt) at time t43, whereas it is 0.49 V (volt) at time t53, and 0.35 V (volt). Variation was detected.

  The present invention has been made to solve the above problems, and an object of the present invention is to provide a pulse booster circuit and an output voltage control circuit that suppress fluctuations in the amplitude of the output voltage without degrading the efficiency of the pulse booster circuit. is there.

  In order to solve the above problems, the present invention is a pulse booster circuit that includes a first charge pump unit that boosts an input clock signal, and further boosts and outputs an output voltage of the first charge pump unit. And connected to a subsequent stage of the first charge pump unit, and in synchronization with the clock signal, a second phase delayed by a predetermined phase from the first phase at which the first charge pump unit should start the boosting operation. A second charge pump unit that starts a step-up operation in phase, wherein the first and second charge pump units are controlled in phase for performing the step-up operation in accordance with an output voltage of the second charge pump unit; In the pulse booster circuit, the boosting operation is restarted in a period from the first phase to the second phase.

  According to the present invention, in the above-described invention, a determination unit that determines an output voltage boosted by the second charge pump unit with respect to a predetermined reference voltage, and a determination signal output by the determination unit And a phase adjusting unit that outputs a boost operation control signal for controlling the boost operation of the first and second charge pump units in synchronization with the clock signal, and the first and second charge The pump unit is characterized in that the boosting operation is controlled based on the input boosting operation control signal.

  Further, the present invention is the above-described invention, wherein the phase adjustment unit includes a state holding unit that holds a state based on the determination signal, and the state holding unit transitions a state in synchronization with the clock signal. It is characterized by making it.

  Further, the present invention is connected to a first charge pump unit that boosts an input clock signal and a subsequent stage of the first charge pump unit, and the first charge pump is synchronized with the clock signal. A second charge pump unit that starts the boosting operation in a second phase delayed by a predetermined phase from the first phase in which the boosting operation should start, and further boosts the output voltage of the first charge pump unit An output voltage control circuit for controlling an output voltage in a pulse booster circuit for outputting, wherein the pulse booster circuit is configured such that the boosting operation of the first and second charge pump units becomes the output voltage of the second charge pump unit Accordingly, the output voltage control circuit is controlled to resume the boosting operation in a period from the first phase to the second phase.

  According to the present invention, in the above-described invention, a determination unit that determines an output voltage boosted by the second charge pump unit with respect to a predetermined reference voltage, and a determination signal output by the determination unit And a phase adjustment unit that outputs a boost operation control signal for controlling the boost operation of the first and second charge pump units in synchronization with the clock signal, and the pulse boost circuit is input The boosting operation is controlled based on the boosting operation control signal.

(1) According to the present invention, the pulse booster circuit includes the first charge pump unit that boosts the input clock signal, and further boosts and outputs the output voltage of the first charge pump unit. The second charge pump unit is connected to the subsequent stage of the first charge pump unit, and in synchronization with the clock signal, after the first phase at which the first charge pump unit should start the boost operation, the first phase The step-up operation is started in the second phase delayed by a predetermined phase. The first and second charge pump units control the output of the boosted voltage according to the output voltage of the second charge pump unit, and output the boosted voltage during the period from the first phase to the second phase. Will be resumed.
As a result, the first charge pump unit starts a boost operation, the second charge pump unit selects a phase corresponding to a period during which the boost operation has not started yet, and a signal based on the input clock signal is sent to each charge pump. By supplying to the unit, the boosted voltage can be output.

(2) According to the present invention, in the above invention, the determination unit determines the output voltage boosted by the second charge pump unit with respect to the predetermined reference voltage. The phase adjustment unit outputs a boost operation control signal for controlling the output of the boosted voltage of the first and second charge pump units in synchronization with the clock signal based on the determination signal output from the determination unit. The first and second charge pump units are controlled to output a boosted voltage based on the input boost operation control signal.
Further, it is possible to specify the phase at which the boosting operation is started, and by specifying the charge pump unit corresponding to the phase, it is possible to reduce the variation in characteristics due to the difference in the circuits to be configured.

(3) According to the present invention, in the above invention, the state holding unit in the phase adjustment circuit holds the state based on the determination signal. The state holding unit transitions the state in synchronization with the clock signal.
Further, this makes it possible to synchronize the determination signal detected by the determination unit with the clock signal that operates the charge pump unit.

(4) According to the present invention, the output voltage control circuit includes a first charge pump unit that boosts an input clock signal, and a second charge connected to a subsequent stage of the first charge pump unit. A pulse boosting circuit that includes a pump unit and further boosts and outputs the output voltage of the first charge pump unit is controlled. The second charge pump unit starts the boost operation in a second phase that is delayed by a predetermined phase from the first phase in which the first charge pump unit should start the boost operation in synchronization with the clock signal. The pulse booster circuit controls the output of the boosted voltage of the first and second charge pump units according to the output voltage of the second charge pump unit, and boosts the voltage during the period from the first phase to the second phase. It is assumed that the output of the selected voltage is resumed.
As a result, the first charge pump unit starts a boost operation, the second charge pump unit selects a phase corresponding to a period during which the boost operation has not started yet, and a signal based on the input clock signal is sent to each charge pump. By supplying to the unit, the boosted voltage can be output.

(5) According to the present invention, in the above invention, the determination unit determines an output voltage boosted by the second charge pump unit with respect to a predetermined reference voltage. The phase adjustment unit outputs a boost operation control signal for controlling the output of the boosted voltage of the first and second charge pump units in synchronization with the clock signal based on the determination signal output from the determination unit. The pulse booster circuit controls the output of the boosted voltage based on the input boost operation control signal.
This also allows the output voltage control circuit to identify the phase at which the boost operation starts, and to reduce the variation in characteristics due to circuit differences by identifying the charge pump unit corresponding to that phase. it can.

It is a block diagram which shows the pulse booster circuit by this embodiment. It is a block diagram which shows the state holding part applied to the pulse booster circuit in the same embodiment. It is a block diagram which shows the flip-flop applied to the pulse booster circuit in the same embodiment. It is FIG. (1) which shows operation | movement of the pulse booster circuit in conventional embodiment. It is FIG. (2) which shows operation | movement of the pulse booster circuit in conventional embodiment. 3 is a timing chart (part 1) illustrating an operation of the pulse booster circuit according to the embodiment. 4 is a timing chart (part 2) illustrating the operation of the pulse booster circuit according to the embodiment. It is a schematic block diagram (the 1) which shows the structural example of the pulse booster circuit in conventional embodiment. It is a schematic block diagram (the 2) which shows the structural example of the pulse booster circuit in conventional embodiment. It is a block diagram which shows the structural example of the pulse booster circuit in the conventional embodiment. It is a block diagram which shows the example of the charge pump circuit applied to the pulse booster circuit in the conventional embodiment. It is a block diagram which shows the example of the voltage doubler circuit applied to the pulse booster circuit in the conventional embodiment. It is a timing chart which shows operation | movement of the pulse booster circuit in conventional embodiment. It is a figure which shows operation | movement of the pulse booster circuit in conventional embodiment.

Hereinafter, a pulse booster circuit and an output voltage control circuit according to an embodiment of the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram showing the pulse booster circuit according to the present embodiment.
This figure shows a pulse booster circuit 100 that outputs a signal PUMPOUT having a boosted voltage by performing a boosting operation based on input clocks CLK1 to CLK3.
The pulse booster circuit 100 includes a clock signal control unit 10, a voltage conversion unit 20, a determination unit 40, and a state holding unit 50.

The clock signal control unit 10 in the pulse booster circuit 100 controls whether or not each of the input clocks CLK1 to CLK3 is output based on the control signal PUMPOUTFF. Further, the clock signal control unit 10 generates and outputs an inverted signal clock CLK02B corresponding to the clock CLK2. The clock signal control unit 10 outputs each clock when the control signal PUMPOUTFF is at “H (high)” level.
The voltage converter 20 outputs a boosted voltage based on the input clock. The voltage conversion unit 20 includes a voltage conversion unit 20a and a voltage conversion unit 20b having the same circuit configuration, and in accordance with the clock CLK2, the step-up operation repeatedly performed and the charge operation to the capacitor are inverted by 180 degrees from each other, thereby having opposite phases. To do. A configuration example of the voltage conversion unit 20 refers to FIG. 11 as in the conventional technique.

The voltage conversion unit 20 illustrated in FIG. 11 includes a voltage conversion unit 20b having the same configuration as the voltage conversion unit 20a. A configuration example of the voltage conversion units 20a and 20b will be described on behalf of the voltage conversion unit 20a.
The voltage converter 20a includes a clock buffer 22, a field effect transistor (FET) 28, and charge pumps 31 and 32.
The clock buffer 22 in the voltage conversion unit 20a outputs an inverted clock of the input clock CLK02. The FET 28 functions as a diode connected to the power supply VDD and supplies power to the charge pump 31.
The charge pump 31 includes a voltage doubler circuit 21, an FET 24, an FET 29, and a capacitor 26.
The voltage doubler circuit 21 in the charge pump 31 outputs a voltage (referred to as “voltage 2VDD”) approximately twice the power supply voltage based on the input clock. The voltage doubler circuit 21 charges the capacitor 26 with the voltage 2VDD output in accordance with the input clock. The FET 24 charges the capacitor 26 with the power supply voltage VDD when the voltage output from the voltage doubler circuit 21 is not output depending on the phase of the input clock. Thus, the voltage 2VDD and the power supply voltage VDD are switched according to the phase of the input clock, thereby repeating the boosting operation, and the boosted voltage is output via the FET 29.

The charge pump 32 includes a voltage doubler circuit 23, an FET 25, an FET 30, and a capacitor 27.
The voltage doubler circuit 23 in the charge pump 32 outputs a voltage (referred to as “voltage 2VDD”) approximately twice the power supply voltage based on the input clock. The voltage doubler circuit 23 charges the capacitor 27 with the voltage 2VDD output in accordance with the input clock. The FET 25 charges the capacitor 27 with the power supply voltage VDD when the voltage output from the voltage doubler circuit 23 is not output depending on the phase of the input clock. Thus, the voltage 2VDD and the power supply voltage VDD are switched according to the phase of the input clock, thereby repeating the boosting operation, and the boosted voltage is output via the FET 30.
The charge pump 32 is connected to the subsequent stage of the charge pump 31 described above, and is boosted by the charge pump 31. The charge pump 32 further adds a voltage boosted by the charge pump 32 itself to the output voltage.

  When the voltage doubler circuit 21 shown in FIG. 12 is applied to the voltage doubler circuit 21 (and 23), a voltage difference is provided by providing a phase difference between the clock CK1 input to the terminal TB221 and the clock CK2 input to the terminal TB222. When switching between 2VDD and the ground potential, it is possible to avoid the timing at which the boosted charge leaks through the FET 213 and FET 214 can be switched, so that the charged charge is effectively output to a circuit connected to the subsequent stage. It becomes possible. This can be realized by securing the time required for the switching and delaying and switching the clocks CLK1 and CLK3 (FIG. 1) with respect to the clock CLK2 (FIG. 1).

  The clock CLK01 synchronized with the clock CLK1 (FIG. 1) is input to the TB 201a of the voltage conversion circuit 20a and the TB 203b of the voltage conversion circuit 20b, and the TB202a of the voltage conversion circuit 20a is in phase with the clock CLK2 (FIG. 1). The clock CLK02 (inverted from the clock CLK2 (FIG. 1) is input to the TB 202b of the voltage conversion circuit 20b, and the clock CLK3 ( A clock CLK03 synchronized with FIG. 1) is input. As a result, it is possible to easily switch charging and output of the boosted voltage according to the respective phases in combination.

  The determination unit 40 operates as a hysteresis type comparator in which the voltage of the signal PUMPOUT output from the voltage conversion unit 20 is input to the terminal TB401, the voltage is divided, and the determination is performed based on a predetermined comparison voltage. The determination unit 40 outputs the “L (low)” level to the terminal TB402 when the voltage of the input signal is lower than the reference, and the “H (high)” level when it is higher. A signal output to the terminal TB402 is defined as a control signal PUMPE.

The state holding unit 50 holds the state of the control signal PUMPE input to the terminal TB501 using the clock CLK2 input to the terminal TB503 as a trigger, and outputs the control signal PUMPOUTFF indicating the held state to the terminal TB505. In addition, it has a so-called reset function that initializes the state held in response to the control signal PUMPE input to the terminal TB502.
FIG. 2 is a block diagram showing a state holding unit applied to the pulse booster circuit.
The state holding unit 50 shown in this figure corresponds to a D-type flip-flop with a reset control function. One embodiment of the state holding | maintenance part 50 is shown.
The state holding unit 50 includes buffers 51 and 53, a NOR gate 52, latch circuits 54 and 55, and an RS flip-flop (RSFF) 56.
A state in which a signal input to the terminal TB501 is stored in synchronization with a clock input to the terminal TB503 in a multistage configuration of a latch 54, a latch 55, and an RSFF 56 connected in series.
The state holding unit 50 detects the change in the state of the signal input to the terminal TB 501 from the “L” level to the “H” level, and updates the information held in the circuit. And output to the terminal TB505 (TB565). When the signal input to the terminal TB502 is “L” level, the information stored therein is returned to the reset state, and the “L” level is output from the terminal TB505 (TB565).

FIG. 3 is a block diagram showing a flip-flop applied to the pulse booster circuit.
The RS flip-flop (RSFF) 56 shown in this figure corresponds to an RS flip-flop with a reset control function. One embodiment of an RS flip-flop (RSFF) 56 is shown.
The RSFF 56 includes a NOR gate 56a, a NAND gate 56b, and buffers 56c and 56d.
The RSFF 56 forms a flip-flop by combining the NOR gate 56a and the NAND gate 56b and connecting the input and output to each other via buffers 56c and 56d connected to the outputs. In the RSFF 56, the state held by this circuit is updated according to the state of the signal input from the terminal TB561 to the TB563 and output to the terminal TB565.
When the signal input to the terminal TB562 or TB563 is at the “L” level, this circuit is initialized, and the “L” level is output to the terminal TB565. For example, TB563 can be used as a reset input terminal.

Before describing the operation of the pulse booster circuit 100, the problems of the conventional pulse booster circuit 200 will be summarized.
As shown in the timing chart shown in FIG. 14, the fluctuation range of the voltage fluctuation greatly changes depending on the timing. A comparison is made between time t43 showing a small fluctuation range and time t53 showing a large fluctuation range.

FIG. 4 is an enlarged view of the state near time t43 in FIG.
This figure shows a voltage (VCPb) of the signal PUMPOUTb, clocks CLK1 to CLK3, a control signal PUMPEb, and clocks CKOUT1 and 2. The clocks CKOUT1 and 2 are voltages that are output from the voltage doubler circuit 21 and the voltage doubler circuit 23 (FIG. 11), respectively, and charge the capacitors 26 and 27 of the charge pump units 31 and 32. In FIG. It shows.

At time t <b> 22, the clock CLK <b> 2 transitions to the “H” level, and switches to the boost operation timing of the charge pump unit 31.
At time t41, the control signal PUMPEb signal transitions to the “H” level, and the boosting operation of the charge pump unit 31 starts. In this boosting operation, the capacitor 26 is charged with 3.43 V (volts) by the clock CKOUT1 generated by the voltage doubler circuit 21. Further, this boosting operation was completed by time t45 and was completed in the first boosting period. The voltage fluctuation due to this boosting operation is 0.14V.

FIG. 5 is an enlarged view of the state near time t53 in FIG.
This figure shows a voltage (VCPb) of the signal PUMPOUTb, clocks CLK1 to CLK3, a control signal PUMPEb, and clocks CKOUT1 and 2. The clocks CKOUT1 and 2 are voltages that are output from the voltage doubler circuit 21 and the voltage doubler circuit 23 (FIG. 11), respectively, and charge the capacitors 26 and 27 of the charge pump units 31 and 32. In FIG. It shows.

At time t <b> 27, the clock CLK <b> 2 transits to “H” level, and switches to the boost operation timing of the charge pump unit 31. At time t <b> 28, the clock CLK <b> 1 transitions to the “H” level, and switches to the boost operation timing of the charge pump unit 32.
At time t51, the control signal PUMPEb signal transitions to the “H” level, and the boosting operation of the charge pump unit 32 starts. With this boosting operation, the capacitor 27 is charged with 4.65 V (volts) by the clock CKOUT2 generated by the voltage doubler circuit 23. Further, this boosting operation was completed by time t55 and was completed in the second boosting period. The voltage fluctuation due to this boosting operation is 0.49V.

As can be seen from the above comparison, at time t43 when a small voltage fluctuation is observed, the charge pump unit 31 having a small output capability is operating. At time t53 when a large voltage fluctuation is observed, the charge pump unit 32 having a large output capability is operating.
Although the time from the start of the boosting operation until the comparison voltage detected by the determination unit 40 is exceeded is short, there is a difference in the amplitude of the voltage that varies until the determination unit 40 detects due to the difference in output capability of the charge pump unit. It is shown to occur.

Therefore, voltage fluctuations are suppressed by controlling as follows.
First, the timing for starting the boosting operation starts during the period of the first boosting operation by the charge pump unit 31. As a result, the voltage fluctuation is smaller than when the boosting operation is started by the charge pump unit 32 having a large output capability.
Further, the charge pump unit that starts the boosting operation is specified. For example, it is assumed that the voltage conversion unit 20a starts in the period of the first step-up operation by the charge pump unit 31. Thereby, it is possible to avoid the influence that the output capability varies due to the difference in the circuit.
Further, if the length of time for which the first step-up operation is continued is shortened, the timing for switching to the second step-up operation is maintained while sufficient charging cannot be performed by the first step-up operation described above. It is desirable to advance the time for starting the first-stage boosting operation and to switch to the second-stage boosting operation while securing the necessary time according to the circuit capability of the charge pump unit. The above delay time can be set as a phase difference if converted into a clock cycle.

The operation in this embodiment will be described with reference to the drawings.
FIG. 6 is a timing chart showing the operation of the pulse booster circuit 100.
This figure shows waveforms of the input clocks CLK1 to CLK3, the control signal PUMPE output based on the determination result of the determination unit 40, and the PUMPOUTFF output from the state holding unit 50.

The control signal PUMPE is determined based on the signal PUMPOUT output from the voltage conversion unit 20, and as a result, when the voltage of the signal PUMPOUT is lower than a predetermined voltage, the output voltage is a reference. It detects that the voltage has dropped below the voltage, and outputs an “H” level indicating a state where a boosting operation is necessary.
The control signal PUMPOUTFF determines the state of the control signal PUMPE in synchronization with the rise of the clock CLK2, and transitions from the initial state “L” level to the “H” level when the control signal PUMPE is in the “H” level state. . Further, the control signal PUMPOUTFF changes from the “H” level to the “L” level when the control signal PUMPE changes to the “L” level state.

The above operation will be described with time.
At time t1, the control signal PUMPE transitioned to the “H” level, and a state requiring boosting was detected.
At time t2, the clock signal CLK2 transits to the “H” level, so that the control signal PUMPOUTFF transits to the “H” level. After the control signal PUMPE transitions to the “H” level, the control signal PUMPOUTFF is activated with a delay of time td1a, and the voltage converter 20 starts the boosting operation. Further, since the clock CLK1 is at the “L” level and the clock CLK2 is at the “H” level, the charge pump unit 31 in the voltage conversion unit 20a is activated, and a boosted voltage is output to its output (1 The boosted state of the stage).

  At time t3, when the clock CLK1 transits to the “H” level, the charge pump unit 32 in the voltage conversion unit 20a is also activated, and a boosted voltage is output to its output (second boosting step). State).

At time t4, the control signal PUMPE transitions to the “L” level, and a state in which boosting is unnecessary is detected. In accordance with the transition of the control signal PUMPE to the “L” level, the control signal PUMPOUTFF transitions to the “L” level. Thereby, the boosting operation in the voltage conversion unit 20a is interrupted.
At time t5, the clocks CLK1 and CLK2 transition to the “L” level, whereby the period of the boosting operation in the voltage conversion unit 20a ends, and the period of the boosting operation in the voltage conversion unit 20b is changed. Here, at time t4, the control signal PUMPOUTFF remains in the “L” level state, and the voltage converter 20b is not boosted.
Until the time t12, the clocks CLK1 to CLK3 are periodically input, but the voltage converters 20a and 20b continue to be stopped.

Here, at time t <b> 9, the control signal PUMPE transitions to the “H” level again, and a state requiring boosting is detected, but the control signal PUMPOUTFF continues to be in the “L” level. Here, the voltage conversion unit 20a reaches time t10 without starting the boosting operation.
After this time 9, there is no state transition in which the clock CLK2 becomes “H” level by time t12, and the clock signal CLK2 transits to “H” level at time t12, so that the control signal PUMPOUTFF transits to “H” level. To do. After the control signal PUMPE transitions to the “H” level (time t10), the control signal PUMPOUTFF is activated with a delay of time td1b, and the voltage converter 20 starts the boosting operation. Further, since the clock CLK1 is at the “L” level and the clock CLK2 is at the “H” level, the charge pump unit 31 in the voltage conversion unit 20a is activated, and a boosted voltage is output to its output (1 The boosted state of the stage).

At time t13, when the clock CLK1 transits to the “H” level, the charge pump unit 32 in the voltage conversion unit 20a is also activated, and a boosted voltage is output to its output (second boosting step). State).
At time t14, the control signal PUMPE transitions to the “L” level, and a state in which boosting is unnecessary is detected. In accordance with the transition of the control signal PUMPE to the “L” level, the control signal PUMPOUTFF transitions to the “L” level. Thereby, the boosting operation in the voltage conversion unit 20a stops the boosting (second boosting state) of the charge pump unit 32.
Thereafter, the clocks CLK1 to CLK3 are periodically input, but since the voltage output from the voltage converter 20 is sufficiently higher than the reference value, the boost operation of the voltage converter 20 remains stopped. It will continue.

FIG. 7 is an enlarged view of the timing chart showing the operation of the pulse booster circuit shown in FIG. 4 in the time direction.
In this figure, the same reference numerals are assigned to the same times as in FIG. 4, and the waveform (VCP) of the voltage output from the power converter 20 is also shown.
At time t12, the clock CLK2 transitions to the “H” level, and the boosting starts during the boosting period of the first-stage charge pump unit 31, and the voltage of the waveform VCP starts to rise gently.
At time t13, the clock CLK1 transitions to the “H” level, and the voltage of the waveform VCP suddenly increases during the boosting period of the second-stage charge pump unit 32.
At time t14, as a result of the determination by the comparison unit 40, the control signal PUMPOUTFF is set to the “L” level to stop the boosting operation of the charge pump unit 32, thereby stopping the increase in the voltage of the waveform VCP.

In the pulse booster circuit 100 shown in the present embodiment, the amplitude of the voltage fluctuation superimposed on the boosted output voltage falls within the range from the minimum voltage 0.19 V to the maximum voltage 0.37 V, and the fluctuation range (maximum voltage-minimum). Voltage) became 0.18V.
In the conventional pulse booster circuit 200, the amplitude of the voltage fluctuation superimposed on the boosted output voltage varies from the minimum voltage 0.14V to the maximum voltage 0.49V, and the fluctuation width (maximum voltage-minimum voltage) is It was 0.35V.
In comparison, the maximum voltage was improved by about 25%, and the fluctuation range was improved by about 45%.

With the configuration described above, the charge pump unit 31 starts a boost operation, the charge pump unit 32 selects a phase corresponding to a period in which the boost operation has not started yet, and a signal based on the input clock signal is sent to each charge pump. By supplying the voltage to the unit, it is possible to output a boosted voltage.
In addition, the phase at which the boosting operation is started can be specified, and by specifying the charge pump unit 31 corresponding to the phase, variation in characteristics due to the difference in the circuits to be configured can be reduced.
Further, the determination signal detected by the determination unit 40 can be synchronized with the clock signal for operating the charge pump units 31 and 32.

The field effect transistors (FETs) 24, 25, 28, 29, 30, and 212 shown in the present embodiment are desirably I-type (intrinsic-type) transistors whose thresholds are set to approximately 0V. . Thereby, the loss by the threshold voltage which each FET has can be reduced.
Further, when the amplitude of the output voltage is increased, problems such as a violation of the breakdown voltage of the subsequent circuit occur. Therefore, in order to suppress the amplitude of the output voltage, it is effective to perform from the charge pump unit 31 in the previous stage.
In addition, by reducing variations in power supply voltage fluctuations (ripple voltage amplitude fluctuations), even in a block (load circuit) where accuracy of the amplitude of the pulse output voltage is required, pulses are not limited by voltage fluctuation conditions. A booster circuit can be applied.

The present invention is not limited to the above embodiments, and can be modified without departing from the spirit of the present invention. In the pulse booster circuit of the present invention, any pulse booster circuit and output voltage control for performing boost operation in at least two stages and at least two stages without being limited by the configuration of the charge pump unit or the number of stages. It can be applied to a circuit.
In addition, the clock input to the voltage doubler circuit and the charge-pump pump unit is a phase control that switches and operates the charge pump unit that is cascade-connected in at least two stages, or a delay that delays for a predetermined time with respect to the reference clock. Any signal can be used as long as it can be controlled in time.

  Note that the first charge pump unit of the present invention corresponds to the charge pump unit 31. The pulse booster circuit of the present invention corresponds to the pulse booster circuit 100. The second charge pump unit of the present invention corresponds to the charge pump unit 32. The determination unit of the present invention corresponds to the determination unit 40. The phase adjustment unit of the present invention corresponds to the state holding unit 50. The state holding unit of the present invention corresponds to the state holding unit 50. The output voltage control circuit of the present invention corresponds to the pulse booster circuit 100.

DESCRIPTION OF SYMBOLS 100 Pulse booster circuit 10 Clock signal control part 11, 12, 13, 14 NAND gate 15, 16, 17, 18 Buffer 19 Capacitor 20, 20a, 20b Voltage conversion part 31, 32 Charge pump part 40 Determination part 50 State holding part

Claims (5)

A pulse booster circuit that includes a first charge pump unit that boosts an input clock signal, and further boosts and outputs an output voltage of the first charge pump unit;
Connected to the subsequent stage of the first charge pump unit and in synchronization with the clock signal, the first charge pump unit boosts to a second phase delayed by a predetermined phase from the first phase at which the boost operation should be started. A second charge pump unit for starting operation,
The first and second charge pump units are
A pulse boosting circuit, wherein a phase for performing a boosting operation is controlled according to an output voltage of the second charge pump unit, and the boosting operation is restarted in a period from the first phase to the second phase. . A determination unit that determines an output voltage boosted by the second charge pump unit with respect to a predetermined reference voltage;
A phase adjustment unit that outputs a boost operation control signal for controlling a phase of performing the boost operation of the first and second charge pump units in synchronization with the clock signal based on a determination signal output by the determination unit;
With
The first and second charge pump units are
The pulse booster circuit according to claim 1, wherein a phase for performing a boost operation is controlled based on the input boost operation control signal. The phase adjusting unit is
A state holding unit for holding a state based on the determination signal;
The pulse booster circuit according to claim 2, wherein the state holding unit changes the state in synchronization with the clock signal. A first charge pump unit that boosts an input clock signal and a subsequent stage of the first charge pump unit, and the first charge pump unit starts a boost operation in synchronization with the clock signal. A pulse booster circuit including a second charge pump unit that starts a boost operation in a second phase delayed by a predetermined phase from the first power phase, and further boosts and outputs the output voltage of the first charge pump unit An output voltage control circuit for controlling the output voltage,
The pulse booster circuit includes:
The phase for performing the boosting operation of the first and second charge pump units is controlled according to the output voltage of the second charge pump unit, and the boosting operation is performed during the period from the first phase to the second phase. The output voltage control circuit is controlled so as to resume. A determination unit that determines an output voltage boosted by the second charge pump unit with respect to a predetermined reference voltage;
A phase adjustment unit that outputs a boost operation control signal for controlling a phase of performing the boost operation of the first and second charge pump units in synchronization with the clock signal based on a determination signal output by the determination unit;
With
The pulse booster circuit includes:
5. The output voltage control circuit according to claim 4, wherein a phase for performing the boosting operation is controlled based on the input boosting operation control signal.

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