JP5341324B2 - Capacitor, manufacturing method thereof, and SOI substrate including capacitor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technology where heavy metal gettering scarcely occurs in a semiconductor region which is covered with an insulating film for determining the withstand voltage of the capacitor and contains a high concentration of impurity. <P>SOLUTION: The capacitor 100 includes a first semiconductor region 12 containing a low concentration of impurity, a second semiconductor region 8 formed in the area facing the surface of the first semiconductor region 12 and containing a high concentration of impurity, an insulating film 22 covering a predetermined area of the surface of the second semiconductor region 8, a first electrode 28 electrically connected to the second semiconductor region 8, a second electrode 24 formed on the surface of the insulating film 22 and opposed to the second semiconductor region 8 via the insulating film 22, and a third semiconductor region 14 formed in the first semiconductor region 12 and having a gettering capability higher than that of the second semiconductor region 8. <P>COPYRIGHT: (C)2009,JPO&amp;INPIT

Description

  The present invention relates to a capacitor. In particular, the present invention relates to a technique for taking measures against a decrease in breakdown voltage of a capacitor built in a semiconductor substrate due to mixing of heavy metal or the like. The present invention also relates to a method for manufacturing the capacitor. The present invention further relates to an SOI substrate comprising the capacitor.

A technique for forming a capacitor in a part of a semiconductor substrate is known. For example, a first semiconductor region containing a low concentration of impurities, a second semiconductor region formed in a range facing the surface of the first semiconductor region and containing a high concentration of impurities, and the second semiconductor An insulating film covering a predetermined region of the surface of the region; a first electrode electrically connected to the second semiconductor region; and a first electrode formed on the surface of the insulating film and through the insulating film 2. Description of the Related Art A capacitor having a second electrode facing two semiconductor regions is known.
Heavy metals are easily gettered (trapped) in a region containing impurities at a high concentration. In the conventional capacitor, heavy metals mixed during the manufacturing process are easily gettered to the second semiconductor region. The heavy metal gettered to the second semiconductor region acts on the insulating film covering the surface of the second semiconductor region, thereby reducing the breakdown voltage of the insulating film (decreasing the breakdown voltage of the capacitor).
Patent Document 1 discloses a technique of ion-implanting phosphorus (P) and arsenic (As) in order to form a second semiconductor region in the first semiconductor region. Ions are implanted so that the relationship between the dose x of phosphorus and the dose y of arsenic when ion implantation satisfies y + 0.5x ≧ 4 × 10 ¹⁵ . By performing heat treatment after the ion implantation, a semiconductor region mainly containing arsenic at a high concentration is formed in a range facing the surface of the first semiconductor region. A semiconductor region mainly containing high concentration of phosphorus is formed on the lower layer side of the semiconductor region containing high concentration of arsenic. Phosphorus is easy to getter heavy metals. With the technique of Patent Document 1, it is possible to suppress phosphorus from being contained at a high concentration in a range facing the surface of the first semiconductor region. Since it is possible to suppress direct contact between the semiconductor region containing phosphorus at a high concentration and the insulating film, it is possible to suppress a decrease in the withstand voltage of the insulating film.

JP 2002-26261 A

Using the technique of Patent Document 1, it is possible to prevent phosphorus that is easy to getter heavy metals from being contained in a high concentration in the range facing the surface of the first semiconductor region. For this reason, it is expected that the breakdown voltage of the insulating film can be suppressed from being lowered by the action of the heavy metal. However, in the range facing the surface of the first semiconductor region, although arsenic is mainly contained, phosphorus is not completely eliminated. Arsenic also has the ability to getter heavy metals. Therefore, it is inevitable that the heavy metal is gettered in a range facing the surface of the first semiconductor region (a range in contact with the insulating film). In other words, in the prior art, it is inevitable that the breakdown voltage of the insulating film is reduced by heavy metal. Alternatively, the breakdown voltage of the insulating film cannot be stabilized for each production. As a result, a capacitor having a high breakdown voltage cannot be manufactured stably.
The present invention provides a technique in which a heavy metal is not easily gettered in a semiconductor region that is covered with an insulating film that determines the withstand voltage of the capacitor and contains a high concentration of impurities in a capacitor formed on a semiconductor substrate. As a result, a technology for mass-producing capacitors having high withstand voltage and suppressed variation in withstand voltage is provided.

  The capacitor of the present invention has a first semiconductor region containing impurities at a low concentration, covered with an insulating film for determining the breakdown voltage of the capacitor, and a getter for a second semiconductor region containing impurities at a high concentration. A third semiconductor region having a gettering capability higher than the ring capability is formed. Since the heavy metal mixed in the capacitor is preferentially gettered to the third semiconductor region, it is possible to prevent the heavy metal from being gettered to the second semiconductor region.

The capacitor of the present invention includes a first semiconductor region containing impurities at a low concentration, a second semiconductor region formed in a range facing the surface of the first semiconductor region, and containing impurities at a high concentration, An insulating film covering a predetermined range of the surface of the second semiconductor region, a first electrode electrically connected to the second semiconductor region, and formed on the surface of the insulating film and through the insulating film A second electrode facing the second semiconductor region, and a third semiconductor region formed in the first semiconductor region and having a gettering capability higher than that of the second semiconductor region. I have.
Here, “impurities contained in the second semiconductor region” refer to impurities having an effect of increasing the conductivity of the second semiconductor region by being contained in the second semiconductor region. When the conductivity type of the second semiconductor region is n-type, phosphorus, arsenic, antimony (Sb), or the like can be given. When the conductivity type of the second semiconductor region is p-type, examples include boron (B) and indium (In).
By including an impurity of a different type from that of the second semiconductor region in the third semiconductor region, the gettering capability of the third semiconductor region can be made higher than that of the second semiconductor region. The impurities contained in the third semiconductor region are preferably those that cause crystal defects in the third semiconductor region. Typical impurities include carbon (C) and oxygen (O).

  According to the capacitor described above, heavy metal mixed in the semiconductor region during the manufacturing process of the capacitor or during the manufacturing process of the composite semiconductor device including the capacitor is preferentially gettered by the third semiconductor region. The second semiconductor region containing a high concentration of impurities also has the ability to getter heavy metals. However, since the heavy metal is more strongly gettered by the third semiconductor region, at least the amount of heavy metal gettered to the second semiconductor region is significantly suppressed. As a result, it is possible to prevent heavy metal from being mixed into the insulating film covering the surface of the second semiconductor region. Since mixing of heavy metals into the insulating film is suppressed, the breakdown voltage of the capacitor can be increased and the breakdown voltage can be prevented from varying.

The capacitor of the present invention, the third semiconductor region, that contains 1 × ¹⁰ 18 atoms / cm ³ or more carbon atoms.
As described above, the second semiconductor region also has the ability to getter heavy metals. In order to suppress the gettering of heavy metal in the second semiconductor region, it is preferable that the gettering capability of the third semiconductor region is significantly higher than the gettering capability of the second semiconductor region. When the third semiconductor region contains 1 × 10 ¹⁸ atoms / cm ³ or more of carbon, the gettering ability of the second semiconductor region is significantly higher regardless of the type and concentration of impurities contained in the second semiconductor region. Can have gettering ability.

The technique of the present invention is particularly useful when a capacitor is manufactured in an active layer of an SOI substrate in which a substrate, a buried insulating film, and an active layer are sequentially stacked. That is, in the capacitor of the present invention, the first semiconductor region, the second semiconductor region, and the third semiconductor region are formed in the active layer of the SOI substrate in which the substrate, the buried insulating film, and the active layer are sequentially stacked. It is preferable.
When a capacitor structure is manufactured in an active layer of an SOI substrate, heavy metal is difficult to pass through the buried insulating film, so that heavy metal mixed in the active layer remains in the active layer. If the first semiconductor region, the second semiconductor region, and the third semiconductor region are formed in the active layer of the SOI substrate, heavy metal mixed in the active layer can be preferentially gettered into the third semiconductor region. it can.

When a capacitor is manufactured in the active layer of the SOI substrate, it is preferable that the third semiconductor region is formed in a range facing the bottom surface of the active layer in contact with the buried insulating film.
When manufacturing a capacitor in the active layer of the SOI substrate, the second semiconductor region is formed in a range facing the surface of the active layer. Therefore, if the third semiconductor region is formed in a range facing the surface of the active layer, a space for forming a capacitor becomes large when the SOI substrate is observed from the active layer side. On the other hand, when the third semiconductor region is formed in a range facing the bottom surface of the active layer, the second semiconductor region and the third semiconductor region are formed so that the positions overlap when the SOI substrate is observed from the active layer side. Can do. A space for forming the capacitor can be reduced.

The present invention also provides an SOI substrate on which a novel semiconductor structure is formed. In the SOI substrate, a substrate, a buried insulating film, and an active layer are sequentially laminated, and the active layer is divided into a plurality of partitions by an insulating wall that reaches the buried insulating film from the surface of the active layer. In the SOI substrate, a section where a capacitor is formed and a section where a capacitor is not formed are mixed. The section in which the capacitor is formed is in contact with the insulating film formed on the surface of the active layer and includes a second semiconductor region containing a high concentration of impurities, and surrounds the second semiconductor region and reduces the impurities. A first semiconductor region included in the concentration is provided. In the section where the capacitor is formed, the third semiconductor region having a gettering capability higher than the gettering capability of the second semiconductor region and containing carbon of 1 × 10 ¹⁸ atoms / cm ³ or more is the first. It is formed in the semiconductor region. In the section where the capacitor is not formed, the third semiconductor region is not formed.

  When the SOI substrate is used, a composite semiconductor device including a capacitor with high withstand voltage and little variation can be manufactured. A switching element, a light emitting element, or the like can be formed in a section where the third semiconductor region is not formed. The third semiconductor region has crystal defects formed by impurities that getter heavy metals. If the third semiconductor region is formed in a section where a switching element, a light emitting element or the like is formed, crystal defects may adversely affect the operation of those elements. In the SOI substrate, heavy metal is easily gettered in the third semiconductor region in the section where the capacitor is formed, and in the section where the switching element, the light emitting element, or the like is formed, the element characteristics are deteriorated due to crystal defects for gettering. There is no deterioration. Note that many switching elements and light-emitting elements do not use an insulating film whose breakdown voltage is reduced by heavy metal, so that a problem caused by not forming the third semiconductor region does not become obvious.

The present invention also provides a method for manufacturing a capacitor. The manufacturing method includes a step of forming a second semiconductor region, a step of forming a third semiconductor region, a step of forming an insulating film, a step of forming a first electrode, and a step of forming a second electrode. I have. In the step of forming the second semiconductor region, the impurity is implanted from the surface of the first semiconductor region containing the impurity at a low concentration. A second semiconductor region containing impurities at a high concentration is formed in a range facing the surface of the first semiconductor region. In the step of forming the third semiconductor region, the third semiconductor region is formed in a range facing the back surface of the first semiconductor region. A range facing the rear surface of the first semiconductor region, third semiconductor region containing 1 × 10 18 ^atoms / cm ³ or more carbon as well as have a high gettering capability than the gettering capability of the second semiconductor region is formed The Note that the step of forming the second semiconductor region and the step of forming the third semiconductor region may be performed earlier or simultaneously.
In the step of forming the insulating film, the insulating film is formed on at least a part of the surface of the second semiconductor region. In the step of forming the first electrode, the first electrode is formed so as to be electrically connected to the second semiconductor region. In the step of forming the second electrode, the second electrode is formed on at least a part of the surface of the insulating film. Note that either the step of forming the first electrode or the step of forming the second electrode may be performed first. Further, after forming the first electrode, an insulating film may be formed, and then the second electrode may be formed.

  According to the above manufacturing method, it is possible to manufacture a capacitor in which heavy metal is prevented from being mixed into the insulating film. Capacitors having a high withstand voltage and suppressed variations in the withstand voltage can be mass-produced.

  According to the present invention, it is possible to realize a capacitor that is hard to getter heavy metals in a semiconductor region that is covered with an insulating film that determines the breakdown voltage of the capacitor and that contains impurities at a high concentration. A capacitor having a high withstand voltage and a suppressed variation in the withstand voltage can be realized.

The main features of the examples are listed.
(Feature 1) A low-resistance polysilicon film is formed on the surface of the insulating film, and the polysilicon film is used as a part of the second electrode.
(Feature 2) A semiconductor layer having a third semiconductor region formed on the back surface and a semiconductor layer having an oxide film formed on the front surface are prepared, and an SOI substrate is formed by bonding them together.

Embodiments will be described in detail below with reference to the drawings.
(First embodiment)
FIG. 1 shows a cross-sectional view of the composite semiconductor device 100. In FIG. 1, only a portion where the capacitor 31 is formed on the active layer 19 of the SOI substrate 21 is illustrated in detail. Actually, in addition to the capacitor 31, a switching element, a light emitting element, and the like are formed in the active layer 19. In FIG. 1, illustration of a switching element, a light emitting element, and the like is omitted.
A substrate 16, a buried insulating film 18, and an active layer 19 are sequentially stacked to form an SOI substrate 21. The main material of the substrate 16 is silicon, which contains p-type impurities. A buried insulating film 18 is formed on the surface of the substrate 16. The main material of the buried insulating film 18 is silicon oxide (SiO ₂ ). An active layer 19 is formed on the surface of the buried insulating film 18. The active layer 19 is single crystal silicon containing n-type impurities. The active layer 19 is divided by the insulating wall 10 into a plurality of sections A1, A2, A3. The insulating wall 10 reaches the buried insulating film 18 from the surface of the active layer 19. A capacitor 31 is formed in the section A2. The capacitors 31 are not formed in the sections A1 and A3, and a switching element, a light emitting element, and the like are formed.

In the active layer 19 of the section A2, the first semiconductor region 12, the second semiconductor region 8, and the third semiconductor region 14 are formed. Further, the partition A 2 includes an insulating film 22, a polysilicon film 20, a first electrode 28, and a second electrode 24 in addition to the first semiconductor region 12, the second semiconductor region 8, and the third semiconductor region 14. The capacitor 31 is formed by the first electrode 28, the second semiconductor region 8, the insulating film 22, the polysilicon film 20, and the second electrode 24. The main material of the first semiconductor region 12 is single crystal silicon, and contains n-type impurities at a low concentration. The impurity concentration of the first semiconductor region 12 is preferably 5 × 10 ^{14 to} 5 × 10 ¹⁵ atoms / cm ³ , and is adjusted to approximately 1 × 10 ¹⁵ atoms / cm ³ in this embodiment. The main material of the second semiconductor region 8 is also single crystal silicon, and contains phosphorus (n-type impurity) at a high concentration. The impurity concentration of the second semiconductor region 8 is preferably 1 × 10 ¹⁸ atoms / cm ³ or more, and is adjusted to about 1 × 10 ¹⁹ atoms / cm ³ in this embodiment. The second semiconductor region 8 is formed in a range facing the surface of the first semiconductor region 12. As will be described later, the second semiconductor region 8 is formed by implanting impurities into the surface of the active layer 19. Therefore, the first semiconductor region 12 surrounds the second semiconductor region 8. The main material of the insulating film 22 is silicon oxide. The insulating film 22 covers a part of the surface of the second semiconductor region 8. In other words, the second semiconductor region 8 is in contact with the insulating film 22. The main material of the first electrode 28 is aluminum and is electrically connected to the second semiconductor region 8. The main material of the second electrode 24 is aluminum, and is formed on the surface of the insulating film 22 via the low-resistance polysilicon film 20. That is, the second electrode 24 is opposed to the second semiconductor region 8 with the polysilicon film 20 and the insulating film 22 interposed therebetween. The polysilicon film 20 is maintained at a low resistance because phosphorus is introduced at a high concentration. It can be said that the polysilicon film 20 constitutes a part of the second electrode 24.

The main material of the third semiconductor region 14 is single crystal silicon and contains carbon as an impurity. The concentration of carbon contained in the third semiconductor region 14 is approximately 1 × 10 ¹⁸ atoms / cm ³ . As will be described later, the third semiconductor region 14 is formed by introducing carbon into the back surface of the active layer 19. The remainder of the active layer 19 in which the second semiconductor region 8 and the third semiconductor region 14 are formed is the first semiconductor region 12. Therefore, it can be said that the third semiconductor region 14 is formed in the first semiconductor region 12. In the capacitor 31, the third semiconductor region 14 is formed in a range facing the back surface (bottom surface) of the active layer 19. The gettering capability of the third semiconductor region 14 is higher than the gettering capability of the second semiconductor region 8. Further, oxygen may be included as an impurity of the third semiconductor region 14. Even if the third semiconductor region 14 contains oxygen, the gettering capability of the third semiconductor region 14 can be made higher than the gettering capability of the second semiconductor region.

A field insulating film (LOCOS oxide film) 6 is dispersedly formed on the surfaces of the first semiconductor region 12 and the second semiconductor region 8 in the partition A2. The insulating film 22 is formed between the field insulating films 6 and 6. The field insulating film 6 is not formed in a range where the first electrode 28 is connected to the second semiconductor region 8.
An interlayer insulating film 4 is formed on the surface of the field insulating film 6, the polysilicon film 20, the second semiconductor region 8, and the insulating wall 10. The first electrode 28 passes through the interlayer insulating film 4 and is connected to the second semiconductor region 8. The second electrode 24 passes through the interlayer insulating film 4 and is connected to the polysilicon film 20. The interlayer insulating film 4 prevents the first electrode 28 and the second electrode 24 from being short-circuited. The protective film 2 is formed on the surfaces of the interlayer insulating film 4, the first electrode 28, and the second electrode 24.

As described above, the second semiconductor region 8 includes phosphorus as an impurity, and the third semiconductor region 14 includes carbon as an impurity. Carbon is easier to getter heavy metals than phosphorus. Therefore, the heavy metal mixed in the capacitor 31 is preferentially gettered by the third semiconductor region 14, and the amount of heavy metal mixed in the second semiconductor region 8 is suppressed. As a result, it is possible to prevent heavy metals from being mixed into the insulating film 22 formed on the surface of the second semiconductor region 8. As will be described later, the insulating film 22 is formed by oxidizing the surface layer of the second semiconductor region 8. Therefore, by suppressing the amount of heavy metal mixed in the second semiconductor region 8, it is possible to suppress the amount of heavy metal mixed in the insulating film 22 as a result. By suppressing the amount of heavy metal mixed in the insulating film 22, it is possible to suppress variation in the breakdown voltage of the capacitor 31 and realize a high breakdown voltage.
This embodiment shows an example of the concentration of the impurity (phosphorus) contained in the second semiconductor region 8 and the concentration of the impurity (carbon) contained in the third semiconductor region 14. , 14 can be changed as appropriate. What is important here is to select an impurity that is easier to getter heavy metals than the impurity contained in the second semiconductor region 8 as the impurity contained in the third semiconductor region 14.

(Manufacturing method of capacitor 31)
A method of manufacturing the capacitor 31 will be described with reference to FIGS. First, as shown in FIG. 2, carbon is introduced into a predetermined portion of the back surface (upper part of FIG. 2) of the semiconductor layer 19 containing n-type impurities at a low concentration to form the third semiconductor region 14. For introducing carbon, methods such as ion implantation, thermal diffusion, and coating can be employed.
Next, as shown in FIG. 3, a substrate 16 having an insulating film (oxide film) 18 formed on the surface is prepared. Next, bonding is performed so that the back surface of the semiconductor layer 19 and the surface of the substrate 18 are in contact. At this stage, the SOI substrate 21 in which the substrate 16, the buried insulating film 18, and the active layer (semiconductor layer) 19 are sequentially stacked is completed. At this stage, the third semiconductor region 14 is formed in a range facing the bottom surface of the active layer 19. Note that a thick substrate (not shown) and a thick semiconductor layer (not shown) may be prepared, and after the front surface of the substrate and the back surface of the semiconductor layer are bonded together, the substrate and / or the semiconductor layer may be polished to a desired thickness. . The remaining polished portion of the thick substrate becomes the substrate 16. The remaining polished portion of the thick semiconductor layer becomes the active layer 19.
Next, as shown in FIG. 4, a mask layer (not shown) having an opening on the surface of the active layer 19 is formed, and phosphorus is ion-implanted from the surface of the active layer 19 toward the mask layer. Thereafter, a mask layer (not shown) is formed over the entire surface of the active layer 19 and heat treatment is performed. By the heat treatment, the phosphorus implanted into the active layer 19 is activated. At this stage, the second semiconductor region 8 containing an n-type impurity at a high concentration is formed in a range facing the surface of the active layer 19. The second semiconductor region 8 is formed so that the positions of the second semiconductor region 8 and the third semiconductor region 14 overlap when the SOI substrate 21 is observed from the surface of the active layer 19. In addition, the range A4, the range a, the range b, and the range c in the drawing will be described later.
Next, as shown in FIG. 5, a field insulating film (oxide film) 6 is formed on a predetermined portion of the surface of the active layer 19 and the surface of the second semiconductor region 8 by using a LOCOS (Local Oxidation of Silicon) method. Form. The field insulating film 6 is formed in a dispersed manner so that the surface of the second semiconductor region 8 is exposed at two locations.

Next, as shown in FIG. 6, a mask layer (not shown) having openings on the surface of the field oxide film 6 and the second semiconductor region 8 is formed, and the surface of the field insulating film 6 is formed using a dry etching method. A trench 30 reaching the buried insulating film is formed. The trench 30 is formed so that the third semiconductor region 14 is formed only in the region where the capacitor 31 is formed (see FIG. 1), and the third semiconductor region 14 is not formed in the region where the capacitor is not formed. That is, the third semiconductor region 14 is disposed only in the section A2, and the third semiconductor region 14 is not disposed in the sections A1 and A3. The trench 30 goes around the third semiconductor region 14. At this stage, the active layer 19 in the section A2 becomes the first semiconductor region 12.
As described above, the remaining portion of the active layer 19 in which the second semiconductor region 8 and the third semiconductor region 14 are formed in the section A <b> 2 is the first semiconductor region 12. That is, in this manufacturing method, it can also be said that the second semiconductor region 8 is formed in the range facing the surface of the first semiconductor region 12 and the third semiconductor region 14 is formed in the range facing the back surface of the first semiconductor region 12. .

Next, as shown in FIG. 7, the sidewall of the trench 30 is thermally oxidized to form an oxide film (not shown). Thereafter, the trench 30 is filled with polysilicon using a CVD (Chemical Vapor Deposition) method. At this stage, the insulating wall 10 is completed. Note that the insulator filled in the trench 3 may not be polysilicon. Any material that can electrically insulate the section A2 and the sections A1 and A3 by the insulating wall 10 may be used.
Next, an insulating film is formed on the exposed surface of the second semiconductor region 8 by thermal oxidation, and a portion of the insulating film (not shown) where the first electrode 28 (see FIG. 1) is formed is etched. And remove. The remaining portion of the etched insulating film becomes the insulating film 22. As described above, since the third semiconductor region 14 preferentially getters heavy metal, the second semiconductor region 8 is prevented from being mixed with heavy metal. Therefore, the mixing of heavy metals into the insulating film 22 is also suppressed.

Next, as shown in FIG. 8, a polysilicon film 20 is formed on the surface of the insulating film 22 using the CVD method. Thereafter, phosphorus is introduced into the polysilicon film 22 using a thermal diffusion method or an ion implantation method to complete the low resistance polysilicon film 20. In the step of forming the polysilicon film 22, surplus polysilicon is formed in addition to the portion connected to the second electrode 24 (see FIG. 1). Excess polysilicon is removed by etching. Thereafter, the interlayer insulating film 4 is formed on the surface of the field insulating film 6, the insulating wall 10, the polysilicon film 20, and the second semiconductor region 8.
Next, an opening is formed in a predetermined portion of the interlayer insulating film 4 to expose a part of the second semiconductor region 8 and a part of the polysilicon film 20. Thereafter, the first electrode 28 is formed on the exposed surface of the second semiconductor region 8, and the second electrode 24 is formed on the exposed surface of the polysilicon film 20. Next, the protective film 2 is formed on the surfaces of the interlayer insulating film 4, the first electrode 28, and the second electrode 24, thereby completing the capacitor 100 shown in FIG.

(Experimental example 1: Gettering ability test of heavy metal)
After the SOI substrate 21 shown in FIG. 4 (Experimental Example 1) was completed, nickel (Ni) as a heavy metal was supplied to the surface thereof at 5.0 × 10 ¹² atoms / cm ² . Thereafter, the SOI substrate 21 was heated at 1000 ° C. for 1 hour to diffuse nickel into the active layer 19. After the SOI substrate 21 was cooled, the active layer 19 in the range A4 was divided into three groups, that is, the surface layer a, the intermediate layer b, and the back layer c. The concentration of nickel contained in each layer a, b, c was measured. Note that the surface layer a mainly includes the second semiconductor region 8. The intermediate layer b includes a second semiconductor region 8 and an active layer (later first semiconductor region 12) 19. The back layer c includes an active layer 19 and a third semiconductor region. The concentration of nickel contained in each of layers a, b, and c was measured using ICP-MS (Inductively Coupled Plasma Mass Spectrometer). The results are shown in FIG. In addition, an SOI substrate 21 (Comparative Example 1) in which phosphorus of the same concentration as that of the second semiconductor region 8 is introduced instead of carbon at the position of the third semiconductor region 14 is prepared. Nickel was diffused inside. The results are shown in FIG.
9 and 10 show the relationship between the positions of the layers a, b, and c in the active layer 19 in the range A4 and the concentration of nickel (heavy metal). The horizontal axis of the graph indicates the position in the active layer 19, and the vertical axis indicates the concentration of heavy metal (unit: atoms / cm ² ).

As is clear from FIG. 9, the SOI substrate 21 of Experimental Example 1 contains more nickel in the bottom layer c than in the surface layer a. This result indicates that the third semiconductor region 14 has higher heavy metal gettering capability than the second semiconductor region 8. That is, it shows that the gettering ability of heavy metals is higher in carbon than in high-concentration phosphorus (n-type impurities).
As is clear from FIG. 10, in the SOI substrate of Comparative Example 1, nickel is contained in the surface layer a and the bottom layer c in substantially the same degree. This result indicates that the gettering ability of heavy metal is approximately equal in the second semiconductor region and the third semiconductor region 14. That is, if the type and concentration of the impurity are the same, the gettering capability of heavy metal does not depend on the position of the active layer 19.
From the results of FIGS. 9 and 10, it was confirmed that in the SOI substrate 21 of Experimental Example 1, the third semiconductor region 14 can getter nickel preferentially. That is, it was confirmed that the amount of heavy metal contained in the second semiconductor region 8 can be suppressed by forming a region (third semiconductor region 14) into which carbon is introduced in the active layer 19. Although the experimental results are omitted, even if phosphorus is introduced into the third semiconductor region 14 at the same concentration as that of the second semiconductor region 8 and further carbon is introduced, the same result as that shown in FIG. 9 is obtained. Yes.
The capacitor 31 (see FIG. 1) of the first embodiment is manufactured using the SOI substrate 21 of Experimental Example 1. Therefore, the amount of heavy metal contained in the second semiconductor region 8 is suppressed. That is, the amount of heavy metal contained in the insulating film 22 is suppressed.
On the other hand, even if the capacitor 31 is manufactured using the SOI substrate 21 of Comparative Example 1, the amount of heavy metal contained in the insulating film 22 cannot be suppressed.

(Experimental example 2: Withstand voltage test of capacitor 31)
200 capacitors 31 of the first embodiment were manufactured, and the breakdown voltage of each capacitor 31 was measured. In this experiment, voltage was applied between the first electrode 28 and the second electrode 24 while increasing the voltage, and the voltage when the insulating film 22 was broken was taken as the breakdown voltage. The results are shown in FIG. In addition, 200 capacitors 31 (Comparative Example 2) in which phosphorus of the same concentration as that of the second semiconductor region 8 was introduced instead of carbon at the position of the third semiconductor region 14 were manufactured, and the breakdown voltage of each capacitor 31 was measured. . The results are shown in FIG.
11 and 12 show the relationship between the breakdown voltage of the capacitor 31 and the frequency. The horizontal axis of the graph indicates the breakdown voltage (unit: MV / cm) of the capacitor 31, and the vertical axis indicates the frequency (%).

As is clear from FIG. 11, the capacitor 31 of the first embodiment has a small withstand voltage variation and exhibits a high withstand voltage. On the other hand, the capacitor 31 of Comparative Example 2 has a large variation in breakdown voltage and exhibits a low breakdown voltage.
As described in Experimental Example 1, in the capacitor 31 of the first example, the amount (concentration) of heavy metal contained in the insulating film 22 is suppressed. Therefore, it is suppressed that a heavy metal acts on the insulating film 22 and the breakdown voltage of the insulating film 22 is reduced.
On the other hand, the capacitor 31 of Comparative Example 2 contains a large amount of heavy metal in the insulating film 22. Heavy metal acts on the insulating film 22 to reduce the withstand voltage of the insulating film 22.
It was confirmed that the capacitor 31 of this example had a high breakdown voltage and a small variation in the breakdown voltage.

Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.
For example, in the above embodiment, the third semiconductor region is formed on the bottom surface of the active layer in contact with the buried insulating film. The position where the third semiconductor region is formed is not limited to the above position. The third semiconductor region only needs to be formed in the partition A2 and at a position separated from the insulating film interposed between the second electrode and the second semiconductor region.
In the above embodiment, the third semiconductor region contains approximately 1 × 10 ¹⁸ atoms / cm ³ of carbon as an impurity. However, the carbon concentration can be appropriately changed according to the concentration of impurities contained in the second semiconductor region.
The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings can achieve a plurality of objects at the same time, and has technical usefulness by achieving one of the objects.

Sectional drawing of the capacitor of 1st Example is shown. The manufacturing process of the capacitor of 1st Example is shown. The manufacturing process of the capacitor of 1st Example is shown. The manufacturing process of the capacitor of 1st Example is shown. The manufacturing process of the capacitor of 1st Example is shown. The manufacturing process of the capacitor of 1st Example is shown. The manufacturing process of the capacitor of 1st Example is shown. The manufacturing process of the capacitor of 1st Example is shown. The result of the gettering ability test of the heavy metal of the SOI substrate of Experimental Example 1 is shown. The result of the gettering ability test of the heavy metal of the SOI substrate of the comparative example 1 is shown. The result of the pressure | voltage resistant test of the capacitor of 1st Example is shown. The result of the pressure | voltage resistant test of the capacitor of the comparative example 2 is shown.

Explanation of symbols

8: second semiconductor region 10: insulating wall 12: first semiconductor region 14: third semiconductor region 16: substrate 18: buried insulating film 19: active layer 21: SOI substrate 22: insulating film 24: first electrode 28: first 2 electrode 31: capacitor 100: composite semiconductor device

Claims (5)

A first semiconductor region containing a low concentration of impurities;
A second semiconductor region formed in a range facing the surface of the first semiconductor region and containing a high concentration of impurities;
An insulating film covering a predetermined range of the surface of the second semiconductor region;
A first electrode electrically connected to the second semiconductor region;
A second electrode formed on the surface of the insulating film and opposed to the second semiconductor region via the insulating film;
A third semiconductor region formed in the first semiconductor region and having a gettering capability higher than the gettering capability of the second semiconductor region ,
The capacitor, wherein the third semiconductor region contains 1 × 10 ¹⁸ atoms / cm ³ or more of carbon . The first semiconductor region, the second semiconductor region, and the third semiconductor region are formed in the active layer of an SOI substrate in which a substrate, a buried insulating film, and an active layer are sequentially stacked. 1 capacitor. 3. The capacitor according to claim 2 , wherein the third semiconductor region is formed in a range facing the bottom surface of the active layer in contact with the buried insulating film. An active layer of an SOI substrate in which a substrate, a buried insulating film, and an active layer are sequentially stacked is divided into a plurality of sections by an insulating wall that reaches the buried insulating film from the surface of the active layer,
A second semiconductor region that is in contact with the insulating film formed on the surface of the active layer and contains impurities at a high concentration, and a first semiconductor that surrounds the second semiconductor region and contains impurities at a low concentration In the section in which the capacitor including the region is formed, the first semiconductor region has a gettering capability higher than that of the second semiconductor region and includes carbon of 1 × 10 ¹⁸ atoms / cm ³ or more. third semiconductor regions where de is formed,
The SOI substrate, wherein the third semiconductor region is not formed in a section where the capacitor is not formed. Injecting impurities from the surface of the first semiconductor region containing impurities at a low concentration to form a second semiconductor region containing impurities at a high concentration in a range facing the surface of the first semiconductor region;
Contains 1 × 10 18 ^atoms / cm ³ or more carbon as well as have a high gettering capability than the gettering capability of the second semiconductor region in the range facing the rear surface of the first semiconductor region containing an impurity at a low concentration Forming a third semiconductor region comprising:
Forming an insulating film on at least a portion of the surface of the second semiconductor region;
Forming a first electrode electrically connected to the second semiconductor region;
Forming a second electrode on at least a portion of the surface of the insulating film;
A method for producing a capacitor, comprising:

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