JP5344634B2 - Semiconductor memory device and control method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory device capable of improving reliability of data without spoiling program processing performance. <P>SOLUTION: A semiconductor memory device of the invention comprises: a memory cell 2 for executing a data reading/writing operation in accordance with an address; detection means 15 for detecting that the same address has been used for reading in two or more cycles in the memory cell 2; error correction means 3 for correcting an error of data read from the memory cell 2; and data holding means 6 for holding the data having been corrected in error. The memory cell 2 writes, in accordance with a detection result obtained by the detection means 15, data held by the data holding means 6 correspondingly to the address. The data holding means 6 outputs the data held therein as read data corresponding to the address. <P>COPYRIGHT: (C)2012,JPO&amp;INPIT

Description

  The present invention relates to a semiconductor memory device and a control method thereof, and more particularly to a semiconductor memory device including an error correction circuit and a control method thereof.

  In general, a circuit including a semiconductor memory such as a DRAM (Dynamic Random Access Memory) is affected by a soft error caused by α rays or neutron rays. In order to reduce the influence of this soft error, an ECC (Error Checking & Correction) circuit having a function of 1-bit error correction and 2-bit error detection is provided. Further, when a 1-bit error occurs when reading data from the memory, the data is read from the memory by correcting the data by the ECC circuit and writing the corrected data to the same address (rewrite operation). Can improve the reliability. Such a rewriting operation is also called a patrol method, and the techniques are disclosed in Patent Documents 1 to 3.

  Also in SRAM (Static Random Access Memory), the influence of soft errors cannot be ignored with the miniaturization of the semiconductor element structure and the increase in storage capacity. Patent Document 4 discloses a technique for reducing the influence of this soft error. The semiconductor memory disclosed in Patent Document 4 realizes a series of operations such as reading data from a memory cell, error correction, and writing back to the memory cell in one clock cycle. Patent Document 5 discloses a technique for reducing the probability that a system error is caused by a soft error of a ferroelectric memory.

JP 59-53949 A JP-A-2-103652 JP-A-4-23295 JP 2006-114141 A Japanese Patent Laid-Open No. 2004-199713

  As described in the background art, in the semiconductor memory device (for example, DRAM) using the patrol method, the rate of occurrence of 1-bit error or 2-bit error can be reduced, so that the reliability of the semiconductor memory device is improved. Can be improved. However, the semiconductor memory device using the patrol method has a problem of deteriorating the program processing performance because a memory access for processing a program is awaited while the patrol process is being executed.

  In view of the above problems, an object of the present invention is to provide a semiconductor memory device and a control method therefor capable of improving data reliability without impairing program processing performance.

  A semiconductor memory device according to the present invention includes a memory cell that reads or writes data according to an address, and a detecting unit that detects that the memory cell is read at the same address for two cycles or more, An error correction unit that corrects an error in data read from the memory cell; and a data holding unit that holds the data after the error correction. The memory cell corresponds to a detection result of the detection unit. The data held in the data holding unit is written in association with the address, and the data holding unit outputs the data held in the data holding unit as read data corresponding to the address.

  According to the present invention, a memory cell that reads or writes data according to an address, a detecting unit that detects that data is being read from the memory cell at the same address for two cycles or more, and the memory cell A control method of a semiconductor memory device comprising: an error correction unit that corrects an error in the read data; and a data holding unit that holds the data after the error correction, wherein the memory cell has a detection result of the detection unit In response, the data held in the data holding unit is written in association with the address, and the data holding unit writes the data held in the data holding unit as read data corresponding to the address. Output.

  According to the present invention, it is possible to provide a semiconductor memory device and a control method therefor capable of improving data reliability without impairing program processing performance.

1 is a diagram illustrating a semiconductor memory device according to a first embodiment; 3 is a timing chart for explaining an operation of the semiconductor memory device according to the first exemplary embodiment; FIG. 3 is a diagram illustrating a semiconductor memory device according to a second embodiment; 6 is a timing chart for explaining an operation of the semiconductor memory device according to the second embodiment;

Embodiment 1
Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a diagram illustrating a semiconductor memory device according to a first embodiment of the present invention.
The semiconductor memory device 1 according to the present embodiment detects that the memory cell 2 that reads or writes data according to the address and that the memory cell 2 is being read at the same address for two cycles or more. A detection unit 15; an error correction unit (ECC circuit) 3 that corrects an error in data read from the memory cell 2; and a data holding unit (register (REWR)) 6 that holds data after error correction. Prepare. The memory cell 2 writes the data held in the data holding unit 6 in association with the address according to the detection result of the detection unit 15. The data holding unit 6 outputs data held in the data holding unit 6 as read data corresponding to the address. Hereinafter, the semiconductor memory device according to this embodiment will be described in detail.

  The semiconductor memory device shown in FIG. 1 is a type of RAM called a 1-port RAM (also called a 1RW RAM) that can execute only one of reading and writing in one cycle. In the semiconductor memory device shown in FIG. 1, when there is no change in the read address for two cycles or more, the read data can be rewritten to the memory cell 2 after being corrected by the ECC circuit.

  The semiconductor memory device 1 shown in FIG. 1 includes a memory cell 2, an ECC circuit 3, registers 4 to 6, a comparator 7, AND gates 8 and 9, selectors 10, 13, and 14, an inverter 11, and an OR gate 12. Here, the registers 4 and 5, the comparator 7, and the AND gates 8 and 9 constitute detection means 15. An address signal (ADIN), a write enable signal (WEIN), and write data (WDIN) are input to the semiconductor memory device 1. Further, the semiconductor memory device 1 outputs read data (RDOUT) corresponding to the address signal (ADIN). Note that it is possible to arbitrarily set whether writing is performed when the write enable signal (WEIN) is “1” or when it is “0”, but in this embodiment, the write enable signal (WEIN) is set. ) Shall be written when "1".

  The register (ADR) 4 is a register that holds an address signal (ADIN) supplied from the terminal ADIN. The comparator 7 is supplied with the address signal (ADIN) supplied from the terminal ADIN at one input, supplied with the output of the register 4 at the other input, and outputs the comparison result to the AND gate 9. That is, the comparator 7 compares the address signal (ADIN) supplied from the terminal ADIN with the address signal one cycle before held in the register 4 and determines whether or not the address signal has changed for two cycles or more. To check. The comparator 7 outputs a high-level signal (“1”) when the address signal (ADIN) supplied from the terminal ADIN and the address signal one cycle before held in the register 4 are the same.

  The register (WER) 5 is a register that holds a signal obtained by inverting the write enable signal (WEIN) supplied from the terminal WEIN by the inverter 11. The AND gate (first AND gate) 8 is supplied with a signal obtained by inverting the write enable signal (WEIN) supplied from the terminal WEIN at the inverter 11 at one input and the output of the register 5 at the other input. These logical products are output to the AND gate 9. That is, the AND gate 8 receives the signal obtained by inverting the write enable signal (WEIN) supplied from the terminal WEIN by the inverter 11 and the inverted write enable signal (WEIN) held in the register 5 one cycle before. In comparison, it is checked that there is no writing for two cycles or more (that is, the write enable signal (WEIN) is “0” for two cycles or more).

  The AND gate (second AND gate) 9 is supplied with the output of the comparator 7 at one input and the output of the AND gate 8 at the other input, and outputs a logical product of these. That is, the AND gate 9 detects that reading is performed at the same address for two cycles or more. When the semiconductor memory device 1 performs reading at the same address for two cycles or more, the AND gate 9 outputs a high level signal (“1”).

  The OR gate 12 inputs the write enable signal (WEIN) supplied from the terminal WEIN and the output of the AND gate 9 and outputs a logical sum. Here, the output of the AND gate 9 becomes a write enable signal at the time of rewriting to the memory cell 2. Therefore, the OR gate 12 sets the write enable (WE) of the memory cell 2, the write enable signal (output of the AND gate 9) that means rewriting to the memory cell 2, or the write enable that means writing to the memory cell 2. A signal (WEIN) is output.

  The memory cell 2 holds write data (WD) corresponding to the address (AD) when the write enable (WE) is at a high level. Further, when the write enable (WE) is at a low level, read data (RD) corresponding to the address (AD) is output.

  The ECC circuit 3 inputs read data (RD) of the memory cell 2 and corrects the data when there is an error in the data. The register (REWR) 6 holds the corrected data in order to write the data corrected by the ECC circuit 3 back to the memory cell 2.

  The selector 14 selects the data corrected by the ECC circuit 3 or the data held in the register 6 according to the output of the AND gate 9 and outputs the selected data to the register 6. That is, when the address signal (ADIN) supplied from the terminal ADIN is different every cycle (in this case, the AND gate 9 is at a low level and rewriting to the memory cell 2 is not performed), the selector 14 performs the ECC circuit 3 Select the corrected data. Further, the selector 14 is in the case where the address signal (ADIN) supplied from the terminal ADIN is the same for two cycles or more and reading is performed (in this case, the AND gate 9 is at the high level and rewriting to the memory cell 2 is performed) The data in the register 6 is held.

  The selector (first selector) 13 selects write data (WDIN) or data held in the register 6 according to the output of the AND gate 9 and outputs the selected data to the memory cell 2. That is, when the address signal (ADIN) supplied from the terminal ADIN is different every cycle or the selector 13 is supplied with a write enable signal (WEIN) instructing writing to the memory cell 2 (in this case, the AND gate 9). Is low level and rewriting to the memory cell 2 is not performed), and write data (WDIN) is selected. Further, the selector 13 is in the case where the address signal (ADIN) supplied from the terminal ADIN is the same for two cycles or more and reading is performed (in this case, the AND gate 9 is at the high level and rewriting to the memory cell 2 is performed) The data held in the register 6 is selected.

  The selector 10 selects the data corrected by the ECC circuit 3 or the data held in the register 6 according to the output of the AND gate 9 and outputs it as read data (RDOUT) of the semiconductor memory device 1. That is, when the address signal (ADIN) supplied from the terminal ADIN is different every cycle (in this case, the AND gate 9 is at the low level and rewriting to the memory cell 2 is not performed), the selector 10 performs the ECC circuit 3 Select the corrected data. Further, the selector 10 is in the case where the address signal (ADIN) supplied from the terminal ADIN is the same for two cycles or more and reading is performed (in this case, the AND gate 9 is at the high level and rewriting to the memory cell 2 is performed) The data held in the register 6 is selected.

  Next, the operation of the semiconductor memory device according to the present embodiment will be described with reference to the timing chart shown in FIG. In the timing chart shown in FIG. 2, when the address signal (ADIN) supplied from the terminal ADIN is “2”, the same address is read for two cycles. In addition, when the address signal (ADIN) is “5”, the same address continues for three cycles, but writing to the address “5” is performed (that is, WEIN becomes high level) in the first cycle. When the address signal (ADIN) is “6”, the same address is read for 3 cycles. As shown in the timing chart of FIG. 2, in the semiconductor memory device according to the present embodiment, after the address signal (ADIN) is input, the register corresponding to each address signal (ADIN) is delayed by one cycle. Data is held and read data (RDOUT) is output.

  First, when “0” is supplied to the semiconductor memory device 1 as the address signal (ADIN), the register (ADR) 4 holds ADR = “0”. At this time, since the write enable signal (WEIN) is at the low level (“0”), the register (WER) 5 holds WER = “1”. The output of the AND gate 9 becomes low level. Since both the write enable signal (WEIN) and the output of the AND gate 9 are at the low level, the write enable (WE) of the memory cell 2 is at the low level. An address signal (ADIN) “0” is supplied to the address (AD) of the memory cell 2. At this time, the memory cell 2 outputs read data (RD = “D0”) corresponding to AD = “0” to the ECC circuit 3. The selector 14 selects the output of the ECC circuit 3 because the output of the AND gate 9 is at a low level. The register (REWR) 6 holds the output “D0” of the ECC circuit 3. The selector 10 selects the output of the ECC circuit 3 because the output of the AND gate 9 is at a low level. Therefore, “D0” is output as the output (RDOUT) of the semiconductor memory device 1. Thereafter, the same operation is performed when the address signal (ADIN) is “1” and the first “2”.

  When the second “2” is supplied as the address signal (ADIN) to the semiconductor memory device 1, the comparator 7 determines that the supplied address signal (ADIN) and the value held in the register (ADR) 4 are the same. Since both are “2”, a high level signal is output to the AND gate 9. The AND gate 8 outputs a high level signal to the AND gate 9 because the inverted signal of the supplied write enable signal (WEIN) and the value held in the register (WER) 5 are both at a high level. To do. Therefore, the output of the AND gate 9 becomes high level.

  Since the output of the AND gate 9 is at a high level, the OR gate 12 outputs a high level signal to the write enable (WE) of the memory cell 2. An address signal (ADIN) “2” is supplied to the address (AD) of the memory cell 2. The selector 14 holds the value of the register (REWR) 6 because the output of the AND gate 9 is at a high level. Since the output of the AND gate 9 is at a high level, the selector 13 supplies REWR = “D2”, which is the value of the register (REWR) 6, as the write data (WD) of the memory cell 2. At this time, since the write enable (WE) of the memory cell 2 is at the high level, the write data WD = "D2" corresponding to the address (AD = "2") is rewritten to the memory cell 2. On the other hand, the selector 10 selects the data “D2” held in the register (REWR) 6 because the output of the AND gate 9 is at a high level. Therefore, “D2” is output as the output (RDOUT) of the semiconductor memory device 1.

  The operation when “3” and “4” are supplied as the address signal (ADIN) is the same as the operation when “0” is supplied as the address signal (ADIN) described above.

  Next, a case where “5” is supplied as an address signal (ADIN) for three cycles will be described. In this case, in the first cycle, writing to the address “5” (that is, WEIN is high level) is performed. When the first address signal ADIN = “5” is supplied as the address signal (ADIN), the comparator 7 receives the ADR = “4” held in the register 4 and the supplied address signal ADIN = “5”. Therefore, a low level signal is output to the AND gate 9. Therefore, the output of the AND gate 9 becomes a low level.

  When a high level write enable signal (WEIN) is supplied from the terminal WEIN, the OR gate 12 outputs a high level signal to the write enable (WE) of the memory cell 2. At this time, since the output of the AND gate 9 is at the low level, the selector 13 outputs the write data WDIN = “D5” supplied from the terminal WDIN as the write data (WD) of the memory cell 2. Since the write enable (WE) of the memory cell 2 is at a high level, write data (WD = “D5”) corresponding to the address (AD = “5”) is written into the memory cell 2.

  In this case, since the output of the AND gate 9 is at a low level, the selectors 10 and 14 select the output of the ECC circuit 3. However, since the read data (RD) is not output from the memory cell 2, the data output (RDOUT) of the semiconductor memory device 1 and the value of the register (REWR) 6 become “undefined”.

  Next, the second ADIN = “5” and the third ADIN = “5” are sequentially supplied as the address signal (ADIN). Since the operation at this time is the same as the operation when the first ADIN = “2” and the second ADIN = “2” described above are supplied, the redundant description is omitted.

  Next, ADIN = “6” is supplied for three cycles as the address signal (ADIN). The operation when the first ADIN = “6” and the second ADIN = “6” are supplied as the address signal (ADIN) is the same as the first ADIN = “2” and 2 described above. Since the operation is the same as that when the first ADIN = “2” is supplied, redundant description is omitted.

  After the second ADIN = “6” is supplied, the third ADIN = “6” is supplied as the address signal (ADIN). At this time, the comparator 7 outputs a high-level signal to the AND gate 9 because both the supplied address signal (ADIN) and the value held in the register (ADR) 4 are “6”. The AND 8 outputs a high level signal to the AND gate 9 because both the inverted signal of the supplied write enable signal (WEIN) and the value held in the register (WER) 5 are at a high level. Therefore, the output of the AND gate 9 becomes high level.

  Since the output of the AND gate 9 is at a high level, the OR gate 12 outputs a high level signal to the write enable (WE) of the memory cell 2. An address signal (ADIN) “6” is supplied to the address (AD) of the memory cell 2. The selector 14 holds the value of the register (REWR) 6 because the output of the AND gate 9 is at a high level. Since the output of the AND gate 9 is at a high level, the selector 13 supplies REWR = “D6”, which is the value of the register (REWR) 6, as the write data (WD) of the memory cell 2. At this time, since the write enable (WE) of the memory cell 2 is at the high level, the write data (WD = “D6”) corresponding to the address (AD = “6”) is rewritten to the memory cell 2. On the other hand, since the output of the AND gate 9 is at the high level, the selector 10 selects the error-corrected data “D6” by the ECC circuit 3 held in the register (REWR) 6. Therefore, “D6” is output as the output (RDOUT) of the semiconductor memory device 1.

The operation of the semiconductor memory device according to the present embodiment is summarized as follows.
(1) Timing corresponding to the first cycle in which the same address n (n is an arbitrary integer) is input.
The output of the AND gate 9 becomes low level. The memory cell 2 outputs read data (RD) corresponding to the address n. The register (REWR) 6 holds data after error correction corresponding to the address n. Further, the selector 10 outputs data after error correction corresponding to the address n output from the ECC circuit 3 as an output (RDOUT) of the semiconductor memory device.

(2) Timing corresponding to the second cycle in which the same address n is input.
The output of the AND gate 9 becomes high level. The memory cell 2 writes the data held in the register (REWR) 6 in association with the address n (rewriting). The register (REWR) 6 outputs data held in the register (REWR) 6 as read data corresponding to the address n as a data output (RDOUT) of the semiconductor memory device 1.

  As described in the background art, in a semiconductor memory device (for example, a DRAM) using a patrol system, memory access for processing a program is awaited while the patrol process is being performed, so that the program processing performance is impaired. There was a problem. That is, when the memory address or bank being executed for patrol overlaps with the memory access by the normal instruction for processing the program, the normal memory access is waited until the address at which the patrol process is executed transitions to a different address. was there.

 Further, in a semiconductor memory device (for example, SRAM) used for a cache memory or the like, the clock frequency of an information processing device that processes a program at a high speed is high, so that the technology disclosed in Patent Document 4 has a delay. There was a problem that it was difficult to satisfy the constraints.

  On the other hand, in the semiconductor memory device 1 according to the present embodiment, when reading is performed at the same address for two cycles or more, the data of the previous cycle held in the register (REWR) 6 is stored in the memory cell 2. At the same time, the held data is output as the output (RDOUT) of the semiconductor memory device 1. Therefore, even when the memory cell 2 can execute only one of reading and writing in one cycle, rewriting data to the memory cell 2 and outputting data from the semiconductor memory device 1 (reading data) Can be performed simultaneously in one cycle. Therefore, it is not necessary to change the memory access timing, and the delay constraint can be satisfied even when the clock frequency is high.

  Therefore, the invention according to the present embodiment can provide a semiconductor memory device and a control method thereof that can improve data reliability without deteriorating program processing performance.

Embodiment 2
Next, a second embodiment of the present invention will be described. FIG. 3 is a diagram of the semiconductor memory device according to the second embodiment. In the semiconductor memory device according to the present embodiment, a cyclic function is added for the rewrite operation. The other configuration is basically the same as that of the semiconductor memory device described in the first embodiment. Here, the cyclic function means that when there is no change in the read address for 4 cycles or more in the 1-port RAM, the address is changed at a rate of once every 2 cycles with the changed address as the start address. This is a function for sequentially repeating reading data in the second cycle after the read data is corrected by the ECC circuit.

  3 includes a memory cell 21, an ECC circuit 22, registers 23 to 28, a comparator 29, AND gates 30 and 31, selectors 32, 34 to 37, and 40, inverters 33 and 38, and an OR gate. 39. Here, the registers 23 and 24, the comparator 29, and the AND gates 30 and 31 constitute a detection unit 45. Further, the register 28, the selector 32, and the inverter 33 constitute a switching unit 46 that alternately switches the reading of data from the memory cell 21 or the writing of data to the memory cell 21 every cycle. The register 25 and the selectors 34 and 35 constitute address generating means 47 that increments the address once every two cycles. Further, in the present embodiment, the data holding means 48 is a first data holding means (register (REWR)) 27 that holds data after error correction, and holds data after error correction and detects the data. Second data holding means (register (HLDR)) 26 capable of holding according to 45 detection results.

  The semiconductor memory device 20 receives an address signal (ADIN), a write enable signal (WEIN), and write data (WDIN). Further, the semiconductor memory device 20 outputs read data (RDOUT) corresponding to the address signal (ADIN). Note that it is possible to arbitrarily set whether the write is performed when the write enable signal (WEIN) is “1” or when the write enable signal (WEIN) is “0”, but in this embodiment, the write enable signal (WEIN) is set. ) Shall be written when "1".

  The register (ADR) 23 is a register that holds an address signal (ADIN) supplied from the terminal ADIN. The comparator 29 receives the address signal (ADIN) supplied from the terminal ADIN and the output of the register 23 and outputs the comparison result to the AND gate 31. That is, the comparator 29 compares the address signal (ADIN) supplied from the terminal ADIN with the address signal one cycle before held in the register 23 and determines whether or not the address signal has changed for two cycles or more. To check. The comparator 29 outputs a high-level signal when the address signal (ADIN) supplied from the terminal ADIN and the address signal one cycle before held in the register 23 are the same.

  The register (WER) 24 is a register that holds a signal obtained by inverting the write enable signal (WEIN) supplied from the terminal WEIN by the inverter 38. The AND gate 30 inputs a signal obtained by inverting the write enable signal (WEIN) supplied from the terminal WEIN by the inverter 38 and the output of the register 24, and outputs a logical product of these signals to the AND gate 31. That is, the AND gate 30 receives the signal obtained by inverting the write enable signal (WEIN) supplied from the terminal WEIN by the inverter 38 and the inverted write enable signal (WEIN) held in the register 24 one cycle before. In comparison, it is checked that there is no writing for two cycles or more (that is, the write enable signal (WEIN) is “0” for two cycles or more).

  The AND gate 31 inputs the output of the comparator 29 and the output of the AND gate 30, and outputs a logical product of these. That is, the AND gate 31 detects that reading is performed at the same address for two cycles or more. When the semiconductor memory device 20 performs reading at the same address for two cycles or more, the AND gate 31 outputs a high level signal (“1”). In the present embodiment, the state in which the semiconductor memory device 20 performs reading at the same address for two cycles or more, that is, the state in which the AND gate 31 outputs a high level signal is referred to as “RAM circulating” for convenience. Express.

  When the AND gate 31 outputs a high level signal, the selector 32 selects a signal obtained by inverting the value held in the register (TMGR) 28 by the inverter 33, and the AND gate 31 is at a low level. If a signal is being output, “0” is selected. The register (TMGR) 28 holds the output of the selector 32. That is, while the AND gate 31 continues to output a high level signal for two cycles or more, the selector 32 alternately outputs “0” and “1” every cycle.

  When the AND gate 31 outputs a low level signal, the selector 34 selects the address signal (ADIN) supplied from the terminal ADIN (“0X”). The selector 34 selects a value held in the register (patrol register: PATR) 25 when the AND gate 31 outputs a high level signal and the output of the selector 32 is at a low level. ("10"). Further, when the AND gate 31 outputs a high level signal and the output of the selector 32 is at a high level, the selector 34 selects a value obtained by incrementing the value held in the register 25 ( “11”). A register (PATR) 25 holds the output of the selector 34.

  That is, when the AND gate 31 continues to output a high level signal, the selector 34 outputs a value counted up once every two cycles as an address. Thereby, the read operation and the rewrite operation can be alternately repeated during the circulation of the RAM.

  The selector 35 selects the address signal (ADIN) supplied from the terminal ADIN when the AND gate 31 outputs a low level signal. The selector 34 selects a value held in the register (PATR) 25 when the AND gate 31 outputs a high level signal. The output of the selector 35 is an address (AD) for the memory cell 21.

  The OR gate 39 inputs the write enable signal (WEIN) supplied from the terminal WEIN and the output of the selector 32, and outputs a logical sum. Here, the output of the selector 32 becomes a write enable signal at the time of rewriting to the memory cell 21. Therefore, the OR gate 39 sets the write enable (WE) of the memory cell 21 to the write enable signal (output of the selector 32) that means rewriting to the memory cell 21 or the write enable signal that means writing to the memory cell 21. (WEIN) is output.

  The memory cell 21 holds write data (WD) corresponding to the address (AD) when the write enable (WE) is at a high level. Further, when the write enable (WE) is at a low level, read data (RD) corresponding to the address (AD) is output. That is, the memory cell 21 reads data corresponding to the address generated by the address generating means 47 or writes data held in the register 27 associated with the address in response to a signal from the switching means 46. To implement.

  The ECC circuit 22 inputs read data (RD) of the memory cell 21 and corrects the data when there is an error in the data. The register (REWR: first register) 27 holds the corrected data in order to write the data corrected by the ECC circuit 22 back to the memory cell 21.

  The selector (second selector) 40 selects write data (WDIN) or data held in the register 27 according to the output of the AND gate 31 and outputs the selected data to the memory cell 21. That is, the selector 40 supplies the data held in the register (REWR) 27 when the output of the AND gate 31 is at a high level, and supplies the data to the terminal WDIN when the output of the AND gate 31 is at a low level. Write data (WDIN) is supplied to each memory cell 21.

  The selector 36 selects the data corrected by the ECC circuit 22 or the data held in the register (HLDR: second register) 26 according to the output of the AND gate 31 and outputs the selected data to the register 26. That is, the selector 36 selects the data corrected by the ECC circuit 22 when the output of the AND gate 31 is at a low level. The selector 36 holds the data in the register 26 when the output of the AND gate 31 is at a high level.

  The selector 37 selects the data corrected by the ECC circuit 22 or the data held in the register 26 according to the output of the AND gate 31 and outputs the selected data as read data (RDOUT) of the semiconductor memory device 20. That is, the selector 37 selects the data corrected by the ECC circuit 22 when the output of the AND gate 31 is at a low level. The selector 37 selects the data held in the register 26 when the output of the AND gate 31 is at a high level.

  Next, the operation of the semiconductor memory device according to the present embodiment will be described with reference to the timing chart shown in FIG. In the timing chart shown in FIG. 4, when the address signal (ADIN) supplied from the terminal ADIN is “2”, the same address is read for two cycles. Further, the same address continues after the address signal (ADIN) is “5”, but writing to the address “5” (that is, WEIN becomes high level) is performed in the first cycle. As shown in the timing chart of FIG. 4, in the semiconductor memory device according to the present embodiment, after the address signal (ADIN) is input, the register corresponding to each address signal (ADIN) is delayed by one cycle. Data is held and read data (RDOUT) is output.

  First, when “0” is supplied to the semiconductor memory device 20 as the address signal (ADIN), the register (ADR) 23 holds ADR = “0”. At this time, since the write enable signal (WEIN) is at the low level (“0”), the register (WER) 24 holds WER = “1”. Since the output of the AND gate 31 is low level, the selector 32 outputs “0”. Since the write enable signal (WEIN) and the output of the selector 32 are both low level, the write enable (WE) of the memory cell 21 is low level.

  Since the output of the AND gate 31 is at a low level, the selector 35 outputs “0” which is an address signal (ADIN). Therefore, “0” that is the address signal (ADIN) is supplied to the address (AD) of the memory cell 21. At this time, the memory cell 21 outputs read data (RD = “D0”) corresponding to AD = “0” to the ECC circuit 22. The selector 36 selects the output of the ECC circuit 22 because the output of the AND gate 31 is at a low level. The register (HLDR) 26 holds the output “D0” of the ECC circuit 22. The register (REWR) 27 also holds the output “D0” of the ECC circuit 22. The selector 37 selects the output of the ECC circuit 22 because the output of the AND gate 31 is at a low level. Therefore, “D0” is output as the output (RDOUT) of the semiconductor memory device 20. Thereafter, the same operation is performed when the address signal (ADIN) is “1” and the first “2”.

  When the second “2” is supplied as the address signal (ADIN) to the semiconductor memory device 20, the comparator 29 receives the supplied address signal (ADIN) and the value held in the register (ADR) 23. Since both are “2”, a high level signal is output to the AND gate 31. The AND gate 30 outputs a high level signal to the AND gate 31 because the inverted signal of the supplied write enable signal (WEIN) and the value held in the register (WER) 24 are both high level. To do. Therefore, the output of the AND gate 31 is at a high level.

  The selector 32 selects the output of the inverter 33 because the output of the AND gate 31 is at a high level. Here, since the initial value of the register (TMGR) 28 is low level (“0”), a high level signal is output from the selector 32. Since both the output of the AND gate 31 and the output of the selector 32 are at the high level, the selector 34 outputs “3” obtained by adding 1 to the value “2” held in the register (PATR) 25. The register (PATR) 25 holds the output value “3” of the selector 34. On the other hand, since the output of the AND gate 31 is at the high level, the selector 35 selects the value already held in the register (PATR) 25 (that is, the value “2” before being selected by the selector 34).

  Since the output of the selector 32 is at a high level, the OR gate 39 outputs a high level signal to the write enable (WE) of the memory cell 21. The address (AD) of the memory cell 21 is supplied with “2” that is the output value of the selector 35. Since the output of the AND gate 31 is at a high level, the selector 40 supplies REWR = “D2”, which is the value of the register (REWR) 27, as write data (WD) of the memory cell 21. At this time, since the write enable (WE) of the memory cell 21 is at the high level, the write data (WD = “D2”) corresponding to the address (AD = “2”) is rewritten to the memory cell 21.

  The selector 36 holds the value of the register (HLDR) 26 because the output of the AND gate 31 is at a high level. On the other hand, since the output of the AND gate 31 is at a high level, the selector 37 selects the data “D2” that has been error-corrected by the ECC circuit 22 held in the register (HLDR) 26. Therefore, “D2” is output as the output (RDOUT) of the semiconductor memory device 20.

  The case where “3” and “4” are supplied as the address signal (ADIN) is the same as the case where “0” is supplied as the address signal (ADIN) described above.

  Next, a description will be given of a case where writing to the address “5” (ie, WEIN = “1”) is performed (indicated by reference numeral 50). When ADIN = “5” is supplied as the address signal (ADIN), the comparator 29 differs between ADR = “4” held in the register 23 and the supplied address signal ADIN = “5”. A low level signal is output to the AND gate 31. Therefore, the output of the AND gate 31 is at a low level. At this time, the output of the selector 32 is at a low level.

  On the other hand, since a high level write enable signal (WEIN) is supplied from the terminal WEIN, the OR gate 39 outputs a high level signal to the write enable (WE) of the memory cell 21. At this time, since the output of the AND gate 31 is at the low level, the selector 40 outputs the write data (WDIN = “D5”) supplied from the terminal WDIN as the write data (WD) of the memory cell 21. Since the output of the AND gate 31 is at a low level, the selector 35 outputs “5” which is an address signal (ADIN). Therefore, “5” which is the address signal (ADIN) is supplied to the address (AD) of the memory cell 21. Since the write enable (WE) of the memory cell 21 is at a high level, write data (WD = “D5”) corresponding to the address (AD = “5”) is written into the memory cell 21.

  In this case, since the output of the AND gate 31 is at a low level, the selectors 36 and 37 select the output of the ECC circuit 22. However, since the read data (RD) is not output from the memory cell 21, the values of the data output (RDOUT), the register (HLDR) 26, and the register (REWR) 27 of the semiconductor memory device 20 are “undefined”.

Next, a case where the same address “5” is supplied as an address signal (ADIN) for four cycles or more and reading is performed (indicated by reference numerals 51 to 54) will be described.
When the first “5” (indicated by reference numeral 51) is supplied as the address signal (ADIN) to the semiconductor memory device 20, the comparator 29 supplies the supplied address signal (ADIN) and the register (ADR) 23. Since the held values are both “5”, a high level signal is output to the AND gate 31. On the other hand, since the AND gate 30 has a signal (high level) obtained by inverting the supplied write enable signal (WEIN) and a value (low level) held in the register (WER) 24, the AND gate 31 has a low level. Output a signal. Therefore, the output of the AND gate 31 is at a low level.

  Since the output of the AND gate 31 is at a low level, the selector 32 outputs “0”. Since the write enable signal (WEIN) and the output of the selector 32 are both at the low level, the OR gate 39 outputs a low level signal to the write enable (WE) of the memory cell 21.

  Since the output of the AND gate 31 is at a low level, the selector 34 holds “5” as the address signal (ADIN) in the register (PATR) 25. Since the output of the AND gate 31 is at a low level, the selector 35 outputs “5” which is an address signal (ADIN). Therefore, “5” which is the address signal (ADIN) is supplied to the address (AD) of the memory cell 21. At this time, the memory cell 21 outputs read data (RD = “D5”) corresponding to AD = “5” to the ECC circuit 22. The selector 36 selects the output of the ECC circuit 22 because the output of the AND gate 31 is at a low level. The register (HLDR) 26 holds the output “D5” of the ECC circuit 22. The register (REWR) 27 also holds the output “D5” of the ECC circuit 22. The selector 37 selects the output of the ECC circuit 22 because the output of the AND gate 31 is at a low level. Therefore, “D5” is output as the output (RDOUT) of the semiconductor memory device 20.

  Next, when the second “5” (indicated by reference numeral 52) is supplied as the address signal (ADIN) to the semiconductor memory device 20, the comparator 29 compares the supplied address signal (ADIN) with the register (ADR). ) Since the values held in 23 are both “5”, a high level signal is output to the AND gate 31. Further, since the AND gate 30 has both a signal obtained by inverting the supplied write enable signal (WEIN) and a value held in the register (WER) 24, the AND gate 31 outputs a high level signal to the AND gate 31. Output. Therefore, the output of the AND gate 31 is at a high level.

  The selector 32 selects the output of the inverter 33 because the output of the AND gate 31 is at a high level. Here, since the value held in the register (TMGR) 28 is low level (“0”), a high level signal is output from the selector 32. Since both the output of the AND gate 31 and the output of the selector 32 are at the high level, the selector 34 outputs “6” obtained by adding 1 to the value “5” held in the register (PATR) 25. The register (PATR) 25 holds the output value “6” of the selector 34. On the other hand, since the output of the AND gate 31 is at a high level, the selector 35 selects the value already held in the register (PATR) 25 (that is, the value “5” before being selected by the selector 34).

  Since the output of the selector 32 is at a high level, the OR gate 39 outputs a high level signal to the write enable (WE) of the memory cell 21. The address (AD) of the memory cell 21 is supplied with “5” that is the output value of the selector 35. Since the output of the AND gate 31 is at a high level, the selector 40 supplies REWR = “D5”, which is the value of the register (REWR) 27, as write data (WD) of the memory cell 21. At this time, since the write enable (WE) of the memory cell 21 is at the high level, the write data (WD = “D5”) corresponding to the address (AD = “5”) is rewritten to the memory cell 21.

  At this time, since the memory cell 21 is performing a rewrite operation, read data (RD) is not output from the memory cell 21. Therefore, the data held in the register (REWR) 27 becomes “undefined”. However, since this “indefinite” data is not used as rewrite data to the memory cell 21, it does not affect the operation of the semiconductor memory device 20.

  The selector 36 holds the value of the register (HLDR) 26 because the output of the AND gate 31 is at a high level. On the other hand, since the output of the AND gate 31 is at the high level, the selector 37 selects the error-corrected data “D5” by the ECC circuit 22 held in the register (HLDR) 26. Therefore, “D5” is output as the output (RDOUT) of the semiconductor memory device 20.

  Next, when the third “5” (indicated by reference numeral 53) is supplied as the address signal (ADIN) to the semiconductor memory device 20, the comparator 29 compares the supplied address signal (ADIN) and the register (ADR). ) Since the values held in 23 are both “5”, a high level signal is output to the AND gate 31. Further, since the AND gate 30 has both a signal obtained by inverting the supplied write enable signal (WEIN) and a value held in the register (WER) 24, the AND gate 31 outputs a high level signal to the AND gate 31. Output. Therefore, the output of the AND gate 31 is at a high level.

  The selector 32 selects the output of the inverter 33 because the output of the AND gate 31 is at a high level. Here, since the value held in the register (TMGR) 28 is high level (“1”), a low level signal is output from the selector 32. The selector 34 outputs the value “6” held in the register (PATR) 25 because the output of the AND gate 31 is high and the output of the selector 32 is low. The register (PATR) 25 holds the output value “6” of the selector 34. On the other hand, the selector 35 selects the value “6” already held in the register (PATR) 25 because the output of the AND gate 31 is at a high level.

  Since the output of the selector 32 and the supplied write enable signal (WEIN) are both at the low level, the OR gate 39 outputs a low level signal to the write enable (WE) of the memory cell 21. The address (AD) of the memory cell 21 is supplied with “6” that is the output value of the selector 35. At this time, the memory cell 21 outputs read data (RD = “D6”) corresponding to AD = “6” to the ECC circuit 22. The register (REWR) 27 holds the output “D6” of the ECC circuit 22. The selector 36 holds the value “D5” of the register (HLDR) 26 because the output of the AND gate 31 is at a high level. Since the output of the AND gate 31 is at a high level, the selector 37 selects the data “D5” that has been error-corrected by the ECC circuit 22 held in the register (HLDR) 26. Therefore, “D5” is output as the output (RDOUT) of the semiconductor memory device 20.

  Next, when the fourth “5” (indicated by reference numeral 54) is supplied as the address signal (ADIN) to the semiconductor memory device 20, the comparator 29 compares the supplied address signal (ADIN) with the register (ADR). ) Since the values held in 23 are both “5”, a high level signal is output to the AND gate 31. Further, since the AND gate 30 has both a signal obtained by inverting the supplied write enable signal (WEIN) and a value held in the register (WER) 24, the AND gate 31 outputs a high level signal to the AND gate 31. Output. Therefore, the output of the AND gate 31 is at a high level.

  The selector 32 selects the output of the inverter 33 because the output of the AND gate 31 is at a high level. Here, since the value held in the register (TMGR) 28 is low level (“0”), a high level signal is output from the selector 32. Since both the output of the AND gate 31 and the output of the selector 32 are at a high level, the selector 34 outputs “7” obtained by adding 1 to the value “6” held in the register (PATR) 25. The register (PATR) 25 holds the output value “7” of the selector 34. On the other hand, since the output of the AND gate 31 is at a high level, the selector 35 selects the value already held in the register (PATR) 25 (that is, the value “6” before being selected by the selector 34).

  Since the output of the selector 32 is at a high level, the OR gate 39 outputs a high level signal to the write enable (WE) of the memory cell 21. The address (AD) of the memory cell 21 is supplied with “6” that is the output value of the selector 35. Since the output of the AND gate 31 is at a high level, the selector 40 supplies REWR = “D6”, which is the value of the register (REWR) 27, as write data (WD) of the memory cell 21. At this time, since the write enable (WE) of the memory cell 21 is at the high level, the write data (WD = “D6”) corresponding to the address (AD = “6”) is rewritten to the memory cell 21.

  The selector 36 holds the value “D5” of the register (HLDR) 26 because the output of the AND gate 31 is at a high level. On the other hand, since the output of the AND gate 31 is at the high level, the selector 37 selects the error-corrected data “D5” by the ECC circuit 22 held in the register (HLDR) 26. Therefore, “D5” is output as the output (RDOUT) of the semiconductor memory device 20.

Thereafter, as long as “5” is continuously supplied as the address signal (ADIN) to the semiconductor memory device 20, the same operation as described above is repeated.
The operation of the semiconductor memory device according to the present embodiment described above is summarized as follows.

(1) Timing corresponding to the first cycle in which the same address n (n is an arbitrary integer) is input.
The output of the AND gate 31 is low level, and the output of the selector 32 is low level. The address generator 47 outputs the input address (ADIN) n as an address. The memory cell 21 outputs read data (RD = Dn) corresponding to the address n. The register (HLDR) 26 and the register (REWR) 27 hold data Dn after error correction corresponding to the address n. The selector 37 outputs the error-corrected data Dn corresponding to the address n output from the ECC circuit 22 as an output (RDOUT) of the semiconductor memory device.

(2) Timing corresponding to the second cycle in which the same address n is input.
The output of the AND gate 31 is high level, and the output of the selector 32 is high level. The address generation means 47 increments the address and holds this address n + 1 in the register (PATR) 25 (this address n + 1 is used in the next cycle). At this time, the address generation means 47 outputs the address n. The memory cell 21 writes the data Dn held in the register (REWR) 27 in association with the address n (rewrite). The register (HLDR) 26 outputs data Dn held in the register (HLDR) 26 as read data corresponding to the address n. The selector 37 outputs the data Dn held in the register (HLDR) 26 as an output (RDOUT) of the semiconductor memory device.

(3) Timing corresponding to the third cycle in which the same address n is input.
The output of the AND gate 31 is high level, and the output of the selector 32 is low level. The address generation means 47 holds the address n + 1 held in the register (PATR) 25. At this time, the address generator 47 outputs the address n + 1. The memory cell 21 outputs read data (RD = Dn + 1) corresponding to the address n + 1. The register (REWR) 27 holds data Dn + 1 after error correction corresponding to the address n + 1. The selector 37 outputs data Dn corresponding to the address n held in the register (HLDR) 26 as an output (RDOUT) of the semiconductor memory device.

(4) Timing corresponding to the fourth cycle in which the same address n is input.
The output of the AND gate 31 is high level, and the output of the selector 32 is high level. The address generation means 47 increments the address and holds this address n + 2 in the register (PATR) 25 (this address n + 2 is used in the next cycle). At this time, the address generator 47 outputs the address n + 1. The memory cell 21 writes the data Dn + 1 held in the register (REWR) 27 in association with the address n + 1 (rewrite). The register (HLDR) 26 outputs data Dn held in the register (HLDR) 26 as read data corresponding to the address n. The selector 37 outputs the data Dn held in the register (HLDR) 26 as an output (RDOUT) of the semiconductor memory device.

  As described above, in the semiconductor memory device 20 according to the present embodiment, when reading is performed at the same address for four cycles or more, the address is set at a rate of once every two cycles from the read address at which rewriting is performed. The data is read out from the memory cell 21 using the incremented address, the data is corrected by the ECC circuit 22, and the corrected data is rewritten using the same address (incremented address). . At this time, since the semiconductor memory device 20 outputs the data held in the register (HLDR) 26 as the output (RDOUT), the data corresponding to the input address (ADIN) is output.

  Thus, in the semiconductor memory device 20 according to the present embodiment, since the cyclic function that alternately repeats reading from the memory cell 21 and writing to the memory cell 21 is implemented, the reliability of the semiconductor memory device is improved. Can be made. Therefore, the invention according to the present embodiment can provide a semiconductor memory device and a control method thereof that can improve data reliability without deteriorating program processing performance.

  Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention. In the above embodiment, a 1-port RAM that can only be read or written in one cycle has been described. However, the present invention is not limited to this. For example, the present invention may be applied to a multi-port RAM such as a 2-port RAM (also referred to as 1R1W) or a 4-port RAM (also referred to as 2R2W).

  Although the present invention has been described with reference to the above embodiment, the present invention is not limited to the configuration of the above embodiment, and can be made by those skilled in the art within the scope of the invention of the claims of the claims of the present application. It goes without saying that various modifications, corrections, and combinations are included.

1, 20 Semiconductor memory device 2, 21 Memory cell 3, 22 ECC circuit 4, 23 Register (ADR)
5, 24 registers (WER)
6, 27 Register (REWR)
7, 29 Comparator 8, 30 AND gate (first AND gate)
9, 31 AND gate (second AND gate)
10, 13, 14, 32, 34, 35, 36, 37, 40 Selector 11, 33, 38 Inverter 12, 39 OR gate 15, 45 Detection means 25 Register (PATR)
26 registers (HLDR)
28 registers (TMGR)
46 switching means 47 address generating means 48 data holding means

Claims (7)

A memory cell that reads or writes data according to an address;
Detecting means for detecting that the memory cell is read at the same address for two cycles or more;
Error correction means for correcting an error in data read from the memory cell;
Data holding means for holding the error-corrected data;
Address generating means for incrementing the address once every two cycles;
Switching means for alternately switching the reading of data from the memory cell or the writing of data to the memory cell every cycle ,
The memory cell writes the data held in the data holding unit in association with the address according to the detection result of the detection unit,
The data holding means outputs the data held in the data holding means as read data corresponding to the address ,
Further, the memory cell reads the data according to the address generated by the address generation unit or holds the data in the data holding unit associated with the address according to a signal from the switching unit. Write data,
Semiconductor memory device. At the timing corresponding to the first cycle in which the same address is input, the data holding means holds the error-corrected data corresponding to the address,
At the timing corresponding to the second cycle in which the same address is input, the memory cell writes the data held in the data holding means in association with the address, and the data holding means corresponds to the address. Output the data held in the data holding means as read data
The semiconductor memory device according to claim 1. The data holding means is a first data holding means for holding the data after error correction, and a second data holding means for holding the data after error correction and holding the data according to the detection result of the detection means. Data holding means, and
At the timing corresponding to the first cycle in which the same address n (n is an arbitrary integer) is input, the first and second data holding means hold the error-corrected data corresponding to the address n And
At a timing corresponding to the second cycle in which the same address n is input, the memory cell writes the data held in the first data holding means in association with the address n, and the second data The holding means outputs the data held in the second data holding means as read data corresponding to the address n,
At the timing corresponding to the third cycle in which the same address n is input, the first data holding means holds the error-corrected data corresponding to the address n + 1 generated by the address generating means,
At a timing corresponding to the fourth cycle in which the same address n is input, the memory cell writes the data held in the first data holding means in association with the address n + 1, and the second data A holding unit that outputs the data held in the second data holding unit as read data corresponding to the address n;
The semiconductor memory device according to claim 1 . A memory cell that reads or writes data according to an address;
Detecting means for detecting that the memory cell is read at the same address for two cycles or more;
Error correction means for correcting an error in data read from the memory cell;
Data holding means for holding the error-corrected data;
A first selector that selectively outputs write data supplied to the semiconductor memory device and the data held in the data holding means ;
When a write enable signal instructing writing to the memory cell is supplied to the semiconductor memory device, the first selector supplies the write data to the memory cell;
When the detecting means detects that the memory cell is read at the same address for two cycles or more, the first selector is held in the data holding means as read data corresponding to the address. the data was supplied to the memory cell, the memory cell write No write the data held before Symbol data holding means associated to said address,
Semiconductor memory device. A second selector for selectively outputting the write data supplied to the semiconductor memory device and the data held in the first data holding means;
When a write enable signal instructing writing to the memory cell is supplied to the semiconductor memory device, the second selector supplies the write data to the memory cell;
When the switching means outputs a signal for instructing data writing to the memory cell, the second selector supplies the data held in the first data holding means to the memory cell.
The semiconductor memory device according to claim 3 . A memory cell that reads or writes data according to an address;
Detecting means for detecting that the memory cell is read at the same address for two cycles or more;
Error correction means for correcting an error in data read from the memory cell;
Data holding means for holding the data after error correction,
The memory cell writes the data held in the data holding unit in association with the address according to the detection result of the detection unit,
The data holding means outputs the data held in the data holding means as read data corresponding to the address,
The detection means includes
A comparator supplied to one input with the address supplied to the semiconductor memory device and supplied to the other input via a first register;
A signal obtained by inverting the write enable signal supplied to the semiconductor memory device is supplied to one input, and a signal obtained by inverting the write enable signal is supplied to the other input via a second register. AND gate of
A semiconductor memory device comprising: a second AND gate having one input supplied with the output of the comparator and the other input supplied with the output of the first AND gate . A method for controlling a semiconductor memory device, comprising:
The semiconductor memory device
A memory cell that reads or writes data according to an address;
Detecting means for detecting that the memory cell is read at the same address for two cycles or more;
Error correction means for correcting an error in data read from the memory cell;
First data holding means for holding the error-corrected data;
Second data holding means capable of holding the error-corrected data and holding the data according to the detection result of the detection means;
Address generating means for incrementing the address once every two cycles;
Switching means for alternately switching the reading of data from the memory cell or the writing of data to the memory cell every cycle ,
At the timing corresponding to the first cycle when the same address n (n is an arbitrary integer) is input, the first and second data holding means hold the data after error correction corresponding to the address n. And
At the timing corresponding to the second cycle in which the same address n is input, the memory cell writes the data held in the first data holding means in association with the address n, and the second data A holding unit outputs the data held in the second data holding unit as read data corresponding to the address n,
At the timing corresponding to the third cycle in which the same address n is input, the first data holding means holds the error-corrected data corresponding to the address n + 1 generated by the address generating means,
At the timing corresponding to the fourth cycle in which the same address n is input, the memory cell writes the data held in the first data holding means in association with the address n + 1, and the second data Holding means outputs the data held in the second data holding means as read data corresponding to the address n;
A method for controlling a semiconductor memory device.

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