JP5347373B2 - Semiconductor device design apparatus, design method, and program - Google Patents

Description

  The present invention relates to a semiconductor device design apparatus, a design method, and a program. More specifically, the present invention relates to a semiconductor device design apparatus, a design method, and a program for designing a semiconductor device having connection pins arranged in an array. About.

  As semiconductor chips are becoming larger and more multifunctional, multi-pin chips with arrayed connection pins such as BGA (Ball Grid Array) devices and PLCC (Plastic Leaded Chip Carrier) devices have become mainstream. ing. For this reason, for example, on a wiring board (multilayer wiring board) on which a semiconductor chip is mounted, the design of wiring for connecting the semiconductor chip with other semiconductor chips, and electrical components (circuit elements) such as resistors and capacitors is also complicated. ing. Generally, in a CAD (computer-aided design) system that designs a semiconductor device using a computer, when the circuit design of a semiconductor chip or an electrical component is completed, the number of wiring layers of the wiring board is determined based on the circuit design. In addition, automatic layout design of electrical parts is performed, and automatic wiring design of in-circuit wiring is performed accordingly.

  In a semiconductor device for which circuit design and automatic placement design of electrical components have been completed, there may be a situation in which wiring connection between the BGA semiconductor chip and other electrical components cannot be made at the stage of automatic wiring design on the wiring board. There is. In such a case, a change of pin assignment (pin assignment) on a semiconductor chip that has already been completed occurs, or the number of wiring layers of a multilayer wiring board is added or the arrangement on the wiring board is changed. Occur. For this reason, the design lead time of the semiconductor device becomes longer, and it becomes difficult to ensure its QCD (Quality Cost Delivery).

Patent Document 1 describes an automatic wiring technique using a computer in the mounting design of a semiconductor device on a wiring board. In the technique of Patent Document 1, in the stage of automatic placement of circuit elements, the actual size of the semiconductor chip or electrical component is enlarged in advance when securing the area for the lead wiring drawn from the semiconductor chip or electrical component. A method of arranging on the wiring board with an enlarged virtual size is adopted. In this enlargement, the number of bending of the wiring is predicted when the wiring is drawn in consideration of the restriction of the wiring pitch at the stage of automatic wiring.
Japanese Patent Laid-Open No. 10-134098

  Although the technique of Patent Document 1 designs the layout of the lead wiring on the wiring board on which the multi-pin semiconductor chip is mounted, what is considered here is how many bends occur after the wiring is pulled out. That is, there is no specific description as to in which direction the wiring is drawn from the semiconductor chip. In the design of a semiconductor device, if the direction in which the wiring is drawn out from the connection pin is not set appropriately, the wiring length becomes unnecessarily long, resulting in a reduction in wiring arrangement efficiency or a large delay in signal propagation. Furthermore, in order to avoid these problems, it is necessary to correct the automatic arrangement of the electrical parts previously performed. Also, it may be necessary to review the pin assignment of the semiconductor chip itself.

  It is an object of the present invention to provide a semiconductor device design apparatus, a design method, and a program that allow efficient wiring design and layout design when designing a semiconductor device using CAD. .

In order to achieve the above object, the present invention provides a design apparatus for a semiconductor device having connection pins arranged in an array,
Based on the arrangement information of the connection pins, a drawing direction calculation unit that calculates the drawing direction of the wiring connected to the connection pins ;
The wiring drawn in the same direction is selected based on the wiring drawing direction calculated by the drawing direction calculation unit, and the wiring drawn in the same direction is selected based on the board information including information on the electrical component of the connection destination. A priority calculation unit for calculating the priority;
Based on the priority calculated by the priority calculation unit, the electrical component connected to the wiring with higher priority than the electrical component connected to the wiring with lower priority is positioned closer to the semiconductor device. A component arrangement calculation unit for calculating the arrangement of the electrical components to
An apparatus for designing a semiconductor device is provided.

The present invention is also a design method for a semiconductor device having connection pins arranged in an array,
Based on the arrangement information of the connection pins, a drawing direction calculation step for calculating a drawing direction of the wiring connected to the connection pins ;
The wiring that is drawn in the same direction is selected based on the drawing direction of the wiring calculated in the drawing direction calculating step, and the wiring that is drawn in the same direction is selected based on the board information including information on the electrical component of the connection destination. A priority calculation step for calculating the priority for
Based on the priority calculated in the priority calculation step, the electrical component connected to the wiring having a higher priority than the electrical component connected to the wiring having a lower priority is placed closer to the semiconductor device. A component placement computation step for computing the placement of the electrical components to be positioned;
A method for designing a semiconductor device is provided.

The present invention further relates to a program for a CAD apparatus for designing a semiconductor device having connection pins arranged in an array.
Based on the pin assignment information of the connection pins, a drawing direction calculation step for calculating the drawing direction of the wiring connected to the connection pins ,
The wiring that is drawn in the same direction is selected based on the drawing direction of the wiring calculated in the drawing direction calculating step, and the wiring that is drawn in the same direction is selected based on the board information including information on the electrical component of the connection destination. A priority calculation step for calculating the priority for
Based on the priority calculated in the priority calculation step, the electrical component connected to the wiring having a higher priority than the electrical component connected to the wiring having a lower priority is placed closer to the semiconductor device. A component placement computation step for computing the placement of the electrical components to be positioned;
A program characterized in that is executed is provided.

  According to the design apparatus, design method, and program of the semiconductor device of the present invention, by determining the lead-out direction of the wiring connected to the connection pin by calculation based on the array information of the connection pin, there is less backtracking of the design and Efficient automatic wiring design of semiconductor devices becomes possible.

  Embodiments of the present invention will be described below with reference to the drawings. The semiconductor device design apparatus according to the first embodiment of the present invention is configured as a CAD system. As hardware, a computer that performs arithmetic processing, an electrical component including a semiconductor chip, a wiring board, a wiring specification, and the like. A database for storing library information, a keyboard for receiving input from the designer, an input device such as a communication unit for acquiring information from the database, a storage device for storing programs and data, a display for outputting calculation results, Output devices such as printers.

  FIG. 1 is a functional block diagram of a semiconductor device design apparatus according to the present embodiment. The design device includes an input unit 1, a calculation unit 2, and an output unit 3. The input unit 1 includes a column number input unit 4, a pin assignment input unit 5, a net information input unit 6, and a board information input unit 7. The column number input unit 4 inputs the number of columns in the X direction and Y direction of connection pins arranged in an array such as a BGA device or a PLCC device at the design stage of the semiconductor chip. The pin assignment input unit 5 inputs the pin assignment of each wiring determined when the semiconductor chip design is completed. The net information input unit 6 inputs information including device names and terminal numbers of the start point and end point of each wiring (net). The board information input unit 7 inputs various information on the wiring board including information such as the number of layers of the wiring board, the size and specifications of the electrical components, and the like.

  The calculation unit 2 is configured by a computer that operates according to a program, and includes a pin assignment information calculation unit 8, a wiring lead-out direction information calculation unit 9, a wiring priority information calculation unit 10, and an opposing component placement information calculation unit 11. . The pin assignment information calculation unit 8 assumes or determines the arrangement of connection pins based on the number of columns input from the column number input unit 4. For example, when the number of columns X is equal to the number of columns Y, the arrangement of connection pins can be uniquely determined. The wiring lead direction information calculation unit 9 is based on pin assignment information including an array of connection pins output from the pin assignment information calculation unit 8 or based on pin assignment information for each wiring input from the pin assignment input unit 5. Then, the drawing direction of the wiring connected to the connection pin of the semiconductor chip is determined.

  The wiring drawing direction information calculation unit 9 determines the drawing direction of each wiring based on the pin assignment information calculated by the pin assignment information calculation unit 8 or the pin assignment information input from the pin assignment input unit 5, and the wiring drawing Output as direction information. The wiring lead direction information is output from the wiring lead direction information output unit 12 and is also input to the wiring priority information calculation unit 10. The wiring priority information calculation unit 10 is based on the wiring drawing direction information, or based on the net information input from the net information input unit 6 and the board information input from the board information input unit 7. The order is determined and output as wiring priority order information. The wiring priority order information is output from the wiring priority order information output unit 13 and is also input to the opposing component placement information calculation unit 11. The opposing component placement information calculation unit 11 determines the placement of the opposing component, which is an electrical component connected to the connection pin of the semiconductor chip, based on the wiring priority. The determined opposing component arrangement information is output via the opposing component arrangement information output unit 14.

  The output unit 3 includes a wiring drawing direction information output unit 12, a wiring priority order information output unit 13, and a counter component placement information output unit 14. Each element of the output unit 3 is activated by the setting of a designer who is a user, and outputs information necessary for the user.

  The column number input unit 4 is used at the design stage of the semiconductor chip. The column number input unit 4 receives user input and inputs the maximum column number of the device to the pin assignment information calculation unit 8. For example, if the BGA device is a 256-pin full-grid device, the pin arrangement is 16 columns × 16 columns. For example, the number “16” is input. The pin assignment information calculation unit 8 outputs the pin arrangement based on the input from the column number input unit 4 at the design stage of the semiconductor chip. At the design stage of the wiring board, pin assignment information for each net that has already been assigned is input from the pin assignment input unit 5.

FIG. 2 illustrates a pin array in which 16 rows in the X direction and 16 rows in the Y direction are output from the pin assignment information calculation unit 8. When receiving the input of the number of columns, the pin assignment information calculation unit 8 outputs the predictive pin arrangement of FIG. 2 as pin assignment information. Each connection pin has column numbers 1, 2,..., 16 in the X direction and column numbers (ID) A, B,. . . T (or 1, 2,..., 16) is added. The wiring lead-out direction information calculation unit 9 obtains wiring lead-out direction information by calculation based on pin assignment information including the column number and column ID of each connection pin. At this time, the wiring lead-out direction information calculation unit 9 calculates the following formula for each calculation target connection pin:
P = 1 × (Int ((Xp-Yp) / Lp) +1) + 2 × (Int ((Lp-Xp-Yp) / Lp) +1) (1)
Is used to calculate the wire drawing direction. Each symbol in the formula is as follows.
P: Numerical value indicating the drawing direction Xp: Column number in the X direction of the calculation target pin Yp: Column number in the Y direction of the calculation target pin Lp: Number of columns of the connection pins of the device Int: Function for obtaining an integer value of the calculated value

  For the calculation target pin, the wiring lead-out direction is determined according to the numerical values illustrated in FIG. 3 based on the numerical values 0 to 3 obtained by Expression (1). In FIG. 3, if the calculation result of the calculation target pin is “0”, it is downward, “1” is right, “2” is left, and “3” is upward. , Decide to pull out the wiring respectively. The wiring lead-out direction information output unit 12 outputs a calculation result by the wiring lead-out direction information calculation unit 9. The wiring drawing groups “0” to “3” are obtained by dividing the bottom surface of a rectangular semiconductor chip on which connection pins are mounted into four diagonal lines. The connection pins located on the diagonal line are divided into any group according to a preset setting. In this case, preferably, the number of connection pins belonging to each group is the same as shown in FIG.

  The wiring priority information calculation unit 10 includes the wiring drawing direction obtained by the wiring drawing direction information calculation unit 9 and the configuration of the wiring board input from the board information input unit 7 (number of wiring layers, presence / absence of through plugs, etc.) ) And the net information input from the net information input unit 6, the wiring order is calculated. The wiring priority information calculation unit 10 calculates a wiring priority considering the wiring drawing efficiency, calculates a number indicating the wiring priority for each group in the wiring drawing direction, and the wiring priority information output unit 13 The calculation result is transferred to the counter component arrangement information calculation unit 11.

  FIG. 4 schematically shows the wiring of the wiring board to be subjected to the process of determining the wiring priority. This wiring board is a so-called through board in which a single through plug is inserted from the surface wiring layer to the lowermost wiring layer of the wiring board. Further, an example is shown in which only one lead wiring can pass between two adjacent connection pins and between two adjacent through plugs in one wiring layer. Under this condition, as shown in FIG. 4, in the surface wiring layer (first wiring layer) 17, wiring can be drawn from two rows of connection pins from the outside. From the second wiring layer 18 immediately below the surface wiring layer 17, wiring can be drawn from the connection pins in the third and fourth rows from the outside. In the next third wiring layer 19 and the subsequent wiring layers, wiring can be drawn only from one row of connection pins. The restrictions such as the wiring pitch described above, the number of wiring layers, and the type of wiring board are merely examples, and are set according to the type of wiring board used.

  FIG. 5 shows a part of the wiring priorities obtained for the pins in the “1” group in FIG. 3 under the wiring drawing conditions described with reference to FIG. The numbers shown on each connection pin in FIG. 5 are priorities. In this example, the connection pins in the outermost 15th and 16th rows in the X direction can be pulled out via the first wiring layer in the wiring board, indicating that the priority is high. ing. In the example of the figure, the rank in the Y direction is an example. Next, the outer thirteenth and fourteenth row connection pins can be drawn from the inner second wiring layer and have the second highest priority after the outermost connection pins. Thereafter, one row of connection pins is drawn out from the inner wiring layer of one layer, and the priority is given sequentially.

  In the net information input unit 6, if there is a pin that does not carry out wiring in the wiring layer of the wiring board only by hitting a pin that does not perform wiring, a power supply, and a through plug such as GND. Calculation is performed avoiding the allocation of ranks.

  The wiring priority order information output unit 13 outputs the result of the wiring priority order information calculation unit 10. The facing component placement information calculation unit 11 calculates the placement of the facing component in consideration of the wiring efficiency from the calculation results of the wiring lead-out direction information calculation unit 9 and the wiring priority order information calculation unit 10, and sends it to the facing component placement information output unit 14. Pass information.

  The opposing component arrangement information calculation unit 11 calculates the position of the opposing component connected to the semiconductor chip. The opposing component arrangement information calculation unit 11 is connected to the wiring drawn in the X direction (or Y direction), and the opposing component connected to the connection pin with the highest priority is the X direction (or as viewed from the semiconductor chip). It is arranged at a position closest to (Y direction). Further, when the connection pin as a target is pulled out in the X direction, the connection pin is arranged at the Y direction position closest to the Y direction position of the connection pin. Here, the opposing component refers to each component of the net information input from the net information input unit 6 when there is a connection destination component, and when there is no such component, or the net information. In the stage where is not input, a test pin or a test pad can be prepared in a pseudo manner and used as a counter part.

  FIG. 6 shows an example in which the connection pin having the wiring priority information shown in FIG. 5 and the opposing component are connected through the wiring drawn in the X direction. The facing component is, for example, a resistor or a capacitor. The opposing parts connected by the first wiring layer with the lead wiring having a high priority are arranged at the position closest to the semiconductor chip in the X direction. Opposing components connected to the wiring having a low priority are sequentially arranged at positions far from the semiconductor chip in the X direction according to the priority. Further, in the Y direction, it is arranged at a position close to the position in the Y direction of the target connection pin. The opposed component arrangement information output unit 14 outputs the result of the opposed component arrangement information calculation unit 11.

  The semiconductor device design apparatus of the present embodiment provides the following effects. First, even when there is no wiring board design information at the circuit design stage, pin assignment can be optimized and opposing component placement can be examined. Conventionally, if the same examination is performed at the circuit design stage, manual work is required, and much examination time is required. However, in the present embodiment, it is possible to make an examination immediately by inputting only the conditions that are actually clear. In addition, since the examination result can be obtained instantaneously, repeated examination such as trial and error correction becomes easy. Therefore, a highly accurate examination result can be obtained.

  In the above-described embodiment, the example in which the calculation is performed according to the equation (1) has been shown. However, equation (1) is merely an example, and other methods can be employed. For example, the calculation result may be stored in the storage device in the form of a table in advance by calculation using the formula (1) and correction as necessary. In the table, for example, the drawing direction is described corresponding to the column numbers of the X direction and the Y direction of the pins.

A second embodiment of the present invention will be described. The configuration of the semiconductor device design apparatus of this embodiment is the same as that of the first embodiment. This embodiment is different from the first embodiment in that the following expression (2) is adopted as an expression for performing calculation for the wiring lead-out direction.
P = 1 × (Int ((Xp-Yp) / Lp) +1) + 2 × (Int ((Lp-Xp-Yp) / Lp) +1)
+ 4 × (Int ((Xp-1) / (Lp / 2))) + 8 × (Int ((Yp-1) / (Lp / 2))) (2)
The symbols in the formula are the same as those in the formula (1).

  FIG. 7 shows the numerical value of P as a result of calculation by Equation (2) for the 256-pin BGA device of FIG. In the present embodiment, in addition to the division of the drawing direction by the two diagonal lines in the previous embodiment, the connection pins of the group with the same drawing direction are divided into two corresponding to the drawing positions. That is, the pins are divided into 8 groups. In this calculation result, for example, the connection pins drawn in the X direction are divided into two groups in the Y direction. Thereby, when arranging the opposing parts, the X direction position can be calculated from the priority order of the opposing parts based on the calculation result, and the Y direction position can be calculated based on the group division. The division within the group can be divided into an arbitrary number of 2 or more.

  In the present embodiment, by outputting the result of the opposed component arrangement information calculation unit 11 in accordance with the format of the board design CAD, it can be used for the design of the wiring board. An example of the calculation result is shown in FIG. FIG. 8 shows an example in which a file output in accordance with the format of the board design CAD is read by the board CAD and arranged.

  If the net information has not yet been obtained, the wiring priority information calculation unit 10 can generate data similar to that shown in FIG. 8 by creating a net list in accordance with the board design CAD format. Therefore, using the output data, the autorouter function of the board design CAD can be used to examine the number of wiring layers of the wiring board at the stage of circuit design.

  The semiconductor device design apparatus and method of the above embodiment can also be used for designing a semiconductor chip (LSI). In this case, it is possible to efficiently design circuit elements and circuit wiring in the chip connected to the connection pins. In addition, the results of the wiring lead-out direction information output unit 12 are color-coded and displayed in a pin assignment table of a programmable LSI such as an FPGA, thereby facilitating pin assignment in consideration of wiring efficiency.

  The design apparatus according to each of the above embodiments includes the number of pin arrangements of a multi-pin device such as a BGA device in which connection pins are arranged in a lattice shape or a PLCC device, pin assignment information, board design conditions, and net information. Can be input to the input unit 1. In this case, the wiring direction classification and wiring priority of each pin, and the arrangement information of the opposing parts can be calculated by the calculation unit and output via the output unit 3. For this reason, it is difficult for the design to reverse, and it is easy to secure the QCD.

  In the above-described embodiment, an example in which the number of rows of connection pins is the same in the X direction and the Y direction is shown, but the present invention is not limited to this example. Even when the number of columns of the connection pins is different between the X direction and the Y direction, the calculation can be performed using, for example, a table describing the drawing direction corresponding to each connection pin.

  Although the invention has been particularly shown and described with reference to illustrative embodiments, the invention is not limited to these embodiments and variations thereof. It will be apparent to those skilled in the art that various modifications can be made to the present invention without departing from the spirit and scope of the invention as defined in the appended claims.

1 is a block diagram of a semiconductor device design apparatus according to a first embodiment of the present invention. The back view of the semiconductor chip which shows the specific example of arrangement | positioning of a connection pin typically. FIG. 3 is a back view of a semiconductor chip illustrating a calculation result in a direction in which a wiring is drawn from the connection pin of FIG. The typical top view which illustrates the lead-out wiring used as the calculation object which determines a priority on a wiring board. The top view which shows the wiring priority determined on the wiring board about a part of drawer wiring of FIG. The top view which shows the example which has arrange | positioned the electrical component corresponding to the wiring which has the wiring priority of FIG. The back view which illustrates the wiring drawer | drawing-out direction determined by the design apparatus of the 2nd Embodiment of this invention. The design data of the Example which shows the connection relation of the semiconductor chip and electric component obtained by the method of this invention.

Explanation of symbols

1: Input unit 2: Calculation unit 3: Output unit 4: Number of columns input unit 5: Pin assignment input unit 6: Net information input unit 7: Board information input unit 8: Pin assignment information calculation unit 9: Calculation of wiring lead direction information Unit 10: Wiring priority information calculation unit 11: Opposing component placement information computing unit 12: Wiring lead direction information output unit 13: Wiring priority information output unit 14: Opposing component placement information output unit 17: First layer wiring 18: First Second layer wiring 19: Third layer wiring

Claims (10)

A design apparatus for a semiconductor device having connection pins arranged in an array,
Based on the arrangement information of the connection pins, a drawing direction calculation unit that calculates the drawing direction of the wiring connected to the connection pins ;
The wiring drawn in the same direction is selected based on the wiring drawing direction calculated by the drawing direction calculation unit, and the wiring drawn in the same direction is selected based on the board information including information on the electrical component of the connection destination. A priority calculation unit for calculating the priority;
Based on the priority calculated by the priority calculation unit, the electrical component connected to the wiring with higher priority than the electrical component connected to the wiring with lower priority is positioned closer to the semiconductor device. A component arrangement calculation unit for calculating the arrangement of the electrical components to
An apparatus for designing a semiconductor device, comprising: The pull-out direction calculation section, based on the number of columns in the X direction and Y direction of the connecting pin, and calculates the withdrawing direction of the wires connected to each of the connecting pins, the design of the semiconductor device according to claim 1 apparatus. The pull-out direction calculation section, the number of columns in the X direction and Y direction of the connecting pin Lp, the connection pin in the X and Y directions, respectively Xp and Yp the column number of the to be calculated, the calculation of the brackets Int Given a function that gets an integer value,
P = 1 × (Int ((Xp-Yp) / Lp) +1) + 2 × (Int ((Lp-Xp-Yp) / Lp) +1)
3. The semiconductor device design apparatus according to claim 1, wherein a direction in which the wiring is drawn from the connection pin to be calculated is determined based on a calculated value of P. 4. The pull-out direction calculation section, the number of columns in the X direction and Y direction of the connecting pin Lp, the connection pin in the X and Y directions, respectively Xp and Yp the column number of the to be calculated, the calculation of the brackets Int Given a function that gets an integer value,
P = 1 × (Int ((Xp-Yp) / Lp) +1) + 2 × (Int ((Lp-Xp-Yp) / Lp) +1)
+ 4 × (Int ((Xp-1) / (Lp / 2))) + 8 × (Int ((Yp-1) / (Lp / 2)))
3. The semiconductor device design apparatus according to claim 1, wherein a direction in which the wiring is drawn from the connection pin to be calculated is determined based on a calculated value of P. 4. The board information, the comprises a arrangement pitch of the connecting pins, the sequence constraints and the wiring connected to the connection pin, and a number of layers of wiring connected to the connection pins, the semiconductor device according to claim 1 Design equipment. The component placement operation unit, said a priority priority calculation unit is calculated, and the number of layers of the wiring connected to the connection pins, on the basis of the size of the electrical component, calculating the placement of the electrical components The apparatus for designing a semiconductor device according to claim 1 . The semiconductor device to be designed is a semiconductor chip having the connection pins, and a wiring substrate for mounting the semiconductor chip, the design apparatus for a semiconductor device according to any one of claims 1-6. The semiconductor device to be designed is a semiconductor chip including a semiconductor element connected to the connecting pin and the connecting pin, the design apparatus for a semiconductor device according to any one of claims 1-6. A design method for a semiconductor device having connection pins arranged in an array,
Based on the arrangement information of the connecting pins, a drawing direction calculating step for calculating the drawing direction of the wiring connected to the connecting pins ;
The wiring that is drawn in the same direction is selected based on the drawing direction of the wiring calculated in the drawing direction calculating step, and the wiring that is drawn in the same direction is selected based on the board information including information on the electrical component of the connection destination. A priority calculation step for calculating the priority for
Based on the priority calculated in the priority calculation step, the electrical component connected to the wiring having a higher priority than the electrical component connected to the wiring having a lower priority is placed closer to the semiconductor device. A component placement computation step for computing the placement of the electrical components to be positioned;
A method for designing a semiconductor device, comprising: A program for a CAD device for designing a semiconductor device having connection pins arranged in an array, the computer comprising:
Based on the pin assignment information of the connection pins, a drawing direction calculation step for calculating the drawing direction of the wiring connected to the connection pins ,
The wiring that is drawn in the same direction is selected based on the drawing direction of the wiring calculated in the drawing direction calculating step, and the wiring that is drawn in the same direction is selected based on the board information including information on the electrical component of the connection destination. A priority calculation step for calculating the priority for
Based on the priority calculated in the priority calculation step, the electrical component connected to the wiring having a higher priority than the electrical component connected to the wiring having a lower priority is placed closer to the semiconductor device. A component placement computation step for computing the placement of the electrical components to be positioned;
A program characterized by having executed.

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