JP5352966B2 - Method of manufacturing resistance change memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To shorten the manufacture time of a resistance change memory device (ReRAM) for which one electrode of a resistance change element is constituted of a transition metal, to improve the working accuracy of a transition metal electrode, and to prevent the degradation of the current/voltage characteristics of the resistance change element. <P>SOLUTION: The manufacturing method of the resistance change memory device, which is provided with the resistance change element comprising a first electrode, a second electrode composed of the transition metal and the oxide of the transition metal disposed between the first electrode and the second electrode and utilizes the reversible and nonvolatile resistance change of the resistance change element, comprises: a first process of forming a laminate 16 comprising the first electrode 4 and the oxide 8 laminated on the first electrode on a base 62; and a second process of reducing the oxide 8 and forming the second electrode 6. <P>COPYRIGHT: (C)2009,JPO&amp;INPIT

Description

  The present invention relates to a method of manufacturing a semiconductor memory device, and more particularly to a method of manufacturing a resistance change memory device (ReRAM) (ReRAM) having a small forming voltage and reset current.

  When a voltage pulse is applied to an element in which a transition metal oxide (for example, NiO) is sandwiched between metal electrodes (for example, Pt), the resistance value reversibly changes and a nonvolatile resistance switch effect is exhibited.

In recent years, resistance random access memory (ReRAM) using this phenomenon has attracted attention as a universal memory that combines the advantages of high-speed DRAM and non-volatile flash memory. (Non-Patent Document 1).
(1) Resistance change element (i) Configuration The resistance change element has a configuration in which a transition metal oxide is sandwiched between metal electrodes, a resistance value reversibly changes, and the change is a non-volatile element.

  FIG. 11 is a cross-sectional view for explaining the configuration of a conventional resistance change element 100 and its periphery that constitute a resistance change memory (ReRAM).

  For example, as shown in FIG. 11, the variable resistance element 100 is configured by sandwiching a thin film of a transition metal oxide 104 made of, for example, NiO (nickel oxide) between upper and lower electrodes 102a and 102b made of, for example, Pt (platinum). Is done. The layer made of the transition metal oxide 104 is hereinafter referred to as a resistance change layer.

In addition to NiO, for example, any transition metal oxide selected from the group consisting of TiO ₂ , HfO, ZrO, ZnO, WO ₃ , CoO, and Nb ₂ O ₅ may be used as the transition metal oxide 104. (Patent Document 1).

  On the other hand, noble metals such as Au and Pt are often used as the upper and lower electrodes 102a and 102b. This is to prevent the electrodes 102a and 102b from reacting with the transition metal oxide 104 and being oxidized.

  In FIG. 11, the lower electrode 102 b of the resistance change element 100 is formed on the Ti film 106. A TiN film 108 is formed on the upper electrode 102a.

The element structure 111 in which the variable resistance element 100 is sandwiched between the Ti film 106 and the TiN film 108 is filled in the first contact hole 112 opened in the base 110 made of an insulating film (for example, SiO ₂ film). It is formed on the first plug 114 and the base 110 made of W. Here, the first plug 114 is formed on the first wiring 115 made of Al.

Further, the element structure 111 including the Ti film 106, the resistance change element 100, and the TiN film 108 is embedded in an interlayer insulating film (for example, SiO ₂ film) 116. On the TiN film 108, a second plug 120 made of Al filled in the second contact hole 118 opened in the interlayer insulating film 116 is formed. A second wiring 122 made of Al whose surface is covered with TiN is formed on the second plug 120.

  Here, the Ti film 106 and the TiN film 108 are not essential components, but are for improving the adhesion between the upper and lower layers.

(Ii) Characteristics (resistance switch effect)
FIG. 12 shows an example of current-voltage characteristics of a Pt / NiO / Pt resistance change element in which a resistance change layer made of NiO is sandwiched between electrodes made of Pt.

  In a resistance change element using a highly variable binary oxide such as NiO as a resistance change layer, a process of applying a predetermined voltage to the resistance change element to cause dielectric breakdown (electroforming: hereinafter referred to as “forming”) After passing through, the resistance switch effect appears.

  FIG. 12 is a diagram showing a state change of the Pt / NiO / Pt resistance change element. The horizontal axis (linear display) is the voltage, and the vertical axis (linear display) is the current (note that “A / B / C resistance change element” indicates A, B, and C respectively for the upper electrode. , A variable resistance layer (transition metal oxide), and a variable resistance element as a lower electrode).

  As shown in FIG. 12, the resistance change element transitions between a high resistance state and a low resistance state in accordance with a current flowing through the resistance change element and an applied voltage. In the high resistance state (for example, 10 kΩ to 1 MΩ), as shown by a in the figure, the current flowing through the inside increases as the applied voltage increases, but the curve showing the relationship between the voltage and the current The inclination is relatively small. However, when the applied voltage is equal to or higher than a specific voltage (indicated by b in FIG. 12), the resistance value rapidly decreases.

  In this case, if the applied voltage remains high, the current increases rapidly. However, the resistance change memory device (ReRAM) is provided with a limiter circuit that prevents a sudden increase in current. Due to the action of the limiter circuit, the applied voltage is lowered, and a large current flows through the resistance change element. Is prevented (indicated by c in the figure).

  In the low resistance state (for example, several kΩ), as shown by d in the figure, the slope of the curve indicating the relationship between the voltage and the current increases. When the current flowing through the variable resistance element reaches a certain value (indicated by e in the figure), the variable resistance element transitions to a high resistance state (indicated by f in the figure), and the current decreases rapidly.

  As described above, the resistance change element transitions to the low resistance state when a voltage higher than a specific voltage is applied in the high resistance state, and increases in resistance when a current higher than the specific current flows in the low resistance state. The resistance switch effect that changes to the state is exhibited.

  The resistance value in the low resistance state is about several kΩ, and the resistance value in the high resistance state is about several tens kΩ to 1 MΩ. In general, a change from a high resistance state to a low resistance state is called a set, and a change from the low resistance state to a high resistance state is called a reset.

(Iii) Operation Model The details of the operation mechanism of the variable resistance element are still unclear.

  As for the Pt / NiO / Pt variable resistance element, there is a report that the element resistance does not depend on the element area. Based on this report, the following model is considered.

  First, as shown in FIG. 13, a conductive filament 124 is formed on the transition metal oxide 104 made of NiO by forming. The filament 124 functions as a current path and opens and closes when a voltage is applied. It is considered that a resistance switch effect is exhibited by opening and closing the current path.

  However, how the current path is opened and closed by the filament 124 has not yet been elucidated.

(2) Resistance change memory The resistance switch effect in the resistance change element (FIG. 11) described above is reversible, and the transition between the high resistance state and the low resistance state can be repeated any number of times.

  Furthermore, this resistance switch effect is non-volatile. That is, even if the supply of voltage and current to the resistance change element is stopped, the resistance state immediately before the stop is maintained.

The resistance change memory is a non-volatile memory (memory that can retain contents even when the power is turned off) that uses this reversible and non-volatile resistance change.
JP 2006-140489 A K. Kinoshita et al. "Bias polarity dependent data retention of resistive random access memory consisting of binary transition metal oxide" APPLIED PHYSICS LETTER 89, 103509 (2006). S. Seo et al. "Reproducible resistance switching in retained NiO films" APPLIED PHYSICS LETTER Vol. 85, No, 23, 6 December (2004.)

(1) Variable resistance element composed of noble metal electrodes (Pt / NiO / Pt variable resistance element, etc.)
As described above, noble metals having excellent oxidation resistance have been used for electrodes of conventional resistance change elements. However, such a resistance change element has a high voltage required for forming (the voltage at b in FIG. 12; hereinafter referred to as the forming voltage), and the current required for reset (the current at e in FIG. 12). Hereinafter referred to as reset current).

  FIG. 14 is an example of current-voltage characteristics of the Pt / NiO / Pt variable resistance element. The horizontal axis (linear display) is voltage, and the vertical axis (logarithmic display) is current. FIG. 15 is a schematic sectional view of a sample used for measuring the current-voltage characteristics. A transition metal 104 made of NiO is disposed between an upper electrode 102a made of Pt and a lower electrode 102b made of Pt.

  As shown in FIG. 14, in the resistance change element in which both the upper electrode and the lower electrode are made of Pt, the voltage (forming voltage) required for forming (f) is as high as about 5 V, and at the first reset (r1) The reset current flowing through the variable resistance element exceeds 10 mA. The reset current at the second and third resets (r2, r3) is also as large as 5 to 10 mA. Further, as shown in FIG. 14, there is a large variation in characteristics during setting and resetting.

  Incidentally, in a normal memory device such as a DRAM, a reduction in voltage and a reduction in power consumption are progressing. For this reason, the voltage and current that the memory device can supply to one memory cell are also reduced to 3.3 V or less and 1 mA or less.

  However, as shown in FIG. 14, the reset current of the resistance change element formed of the noble metal electrode greatly exceeds 1 mA that a normal memory device can supply to one memory cell.

  On the other hand, once the forming is performed, it is not necessary thereafter, and the forming voltage is not necessarily supplied by the memory device. For example, it is conceivable to perform the forming process in the manufacturing stage of the resistance change memory (ReRAM). However, in order to perform the forming process at the manufacturing stage, equipment and processes are required for that purpose, which is inefficient. Therefore, it is desirable that the ReRAM is built into a computer and then formed by a voltage generated by the memory device itself.

  However, as described above, in the variable resistance element made of a noble metal electrode, the forming voltage greatly exceeds 3.3 V that can be supplied by the memory device.

(2) Variable resistance element composed of transition metal electrodes (Pt / NiO / Ni variable resistance element, etc.)
To solve such a problem, the present inventor replaces one of the opposing noble metal electrodes with an electrode made of a transition metal (hereinafter referred to as a transition metal electrode), thereby reducing both the forming voltage and the reset current. I have already found that.

  In the Pt / NiO / Ni variable resistance element, a current path is formed from the beginning, and forming itself is often unnecessary. Even if a current path is not formed and forming is necessary, the forming voltage is as low as about 2 to 3 V, and the reset current is as low as about 1 mA.

  FIG. 16 is a cross-sectional view of a Pt / NiO / Ni resistance change element and its periphery in a resistance change memory (ReRAM). The configuration of the Pt / NiO / Ni resistance change element 101 is substantially the same as that of the Pt / NiO / Pt resistance change element shown in FIG. 11 except that the lower electrode 102b is made of Ni (transition metal) instead of Pt. It is.

  Although it is conceivable that both the upper and lower electrodes 102a and 102b are made of a transition metal, such a configuration does not produce a resistance switch effect.

(3) Processing Problem However, such a Pt / NiO / Ni resistance change element 101 has a processing problem as described below.

  In order to manufacture the structure as shown in FIG. 16, the TiN film 106, the Ni film that becomes the lower electrode 102b, the NiO that becomes the resistance change layer 105, the Pt film that becomes the upper electrode 102a, and the TiN film on the base 110 It is necessary to form the resistance change element 101 by sequentially depositing 108 and etching the deposited film by reactive ion etching (RIE) using, for example, a photoresist film as an etching mask.

Of the deposited films, the Pt film and the NiO film can be easily etched by RIE using a chlorine-based gas (for example, Cl ₂ gas) as a reactive gas, which is widely used in the manufacture of integrated circuits. .

  However, since transition metals such as Ni have poor reactivity, the etching rate of RIE using a chlorine-based gas is slow. Moreover, side wall adsorbate and corrosion (corrosion) are likely to occur.

  For this reason, the etching process takes a long time, and the processing accuracy further deteriorates. Furthermore, there is a concern that the current-voltage characteristics of the resistance change element are deteriorated due to corrosion of the transition metal electrode. Hereinafter, these problems will be described.

  FIG. 17 is a diagram for sequentially explaining the process of forming the Pt / NiO / Ni variable resistance element using RIE using a chlorine-based gas. Note that the TiN film 108 and the Ti film 106 are omitted here for the sake of simplicity.

  First, a Pt / NiO / Ni deposited film composed of a Pt film 128, a NiO film 130, and a Pt film 132 is formed on the substrate 126 (FIG. 17A).

  Next, a first etching mask 134 made of a photoresist film is formed on the deposited film (FIG. 17B).

  Next, the Pt film and the NiO film in the region not covered with the first etching mask are etched by RIE using chlorine gas. Thereafter, the first etching mask 134 is removed (FIG. 18C).

  Next, a second etching mask 136 made of a photoresist film is formed so as to cover the Pt film 132 and the NiO film 130 remaining without being etched (FIG. 18D).

  Next, the Ni film not covered with the second etching mask is etched by RIE using chlorine gas as a reaction gas. Thereafter, the second etching mask is removed (FIG. 17E).

  As described above, the Ni film 128 is etched after the Pt film 132 and the NiO film 130 are etched, the first etching mask 134 is removed, and a second etching mask is formed again. This is because it takes a long time to etch the Ni film 128 having a low etching rate, so that the first etching mask 134 damaged by RIE with respect to the Pt film 132 and the NiO film 130 becomes the RIE with respect to the Ni film 128 thereafter. Because I can't stand it.

  Thus, in order to process the resistance change element in which one electrode is constituted by the transition metal, the formation of the etching mask and RIE must be repeated twice. For this reason, the etching process takes a long time.

  FIG. 19 is a plan view showing the state of the resistance change element formed by the etching process. An adsorbate is formed on the side wall of the Ni film to form a residue 142, which sometimes peels off the side wall and adheres to the surface of the base 110. Such side wall adsorbents cause deterioration in processing accuracy.

  Further, as shown in FIG. 19, the lower electrode made of the Ni film 128 is corroded by chlorine, and a corrosion mark 144 is generated. Such corrosion is caused by diffusion of chlorine-based reaction gas 140 adsorbed on the surface of the substrate 126 during RIE to the exposed surface of the Ni film 128 after the removal of the second resist mask 136 (see FIG. (See FIG. 18 (e)).

  Such corrosion changes the electrical characteristics of the lower electrode made of the Ni film 128 and the properties of the Ni lower electrode / NiO transition metal oxide interface. Therefore, there is a concern about deterioration of the current-voltage characteristics of the resistance change element.

  Accordingly, an object of the present invention is to provide a method of manufacturing a resistance change memory device (ReRAM) in which various problems associated with such reactive ion etching are solved.

(First side)
In order to achieve the above object, a first aspect of the present invention provides a first electrode, a second electrode made of a transition metal, and the first electrode and the second electrode, In the method of manufacturing a resistance change memory device including the resistance change element made of the transition metal oxide and using the reversible and nonvolatile resistance change of the resistance change element, the first electrode and the first electrode A first step of forming a stacked body made of the oxide stacked on the electrode on a base, and a second step of forming the second electrode by reducing the oxide. It is characterized by doing.

  According to the first aspect, since the transition metal oxide stacked on the first electrode is reduced to form the second electrode made of the transition metal, the transition metal is processed by reactive ion etching. The main problems caused by this (longer etching process and worsening of processing accuracy) can be solved.

(Second aspect)
According to a second aspect of the present invention, in the first aspect, the second step forms the second electrode by reducing the oxide using one or both of hydrogen and ammonia as a reducing gas. It is a process to perform.

  According to the second aspect, the transition metal oxide can be easily reduced.

(Third aspect)
According to a third aspect of the present invention, in the first or second aspect, the second step includes a third step of forming an insulating film on the base and embedding the stacked body, and the insulation. A fourth step of forming a contact hole reaching the oxide in the film; and a fifth step of forming the second electrode by reducing the oxide exposed at the bottom of the contact hole. It is characterized by.

  In the third aspect, after forming an insulating film on the base, the surface of the oxide (transition metal oxide) is reduced to form the second electrode (transition metal electrode). For this reason, since the reactive gas used for RIE is confined by the insulating film, the second electrode (transition metal electrode) is not corroded. Therefore, the current-voltage characteristic of the resistance change memory device does not deteriorate.

(Fourth aspect)
According to a fourth aspect of the present invention, in the first to third aspects, the transition metal is nickel.

(5th side)
According to a fifth aspect of the present invention, in the first to fourth aspects, the second electrode is grounded, and the first electrode has a positive potential via a transistor whose gate is connected to a word line. It is connected to a bit line to be applied.

  According to the present invention, the upper part of the transition metal oxide constituting the variable resistance layer is reduced to form the transition metal electrode, so that the problem caused by processing the transition metal by reactive ion etching (the length of the etching process) Time and deterioration of processing accuracy) can be eliminated.

  In the present invention, since the reactive gas for RIE adsorbed on the base is confined by the insulating film, a part of the transition metal oxide serving as the resistance change layer is reduced, so that the transition metal electrode is not corroded. Accordingly, there is no possibility that the transition metal electrode is corroded and the current-voltage characteristics of the resistance change memory device are deteriorated.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the technical scope of the present invention is not limited to these embodiments, but extends to the matters described in the claims and equivalents thereof. Note that even if the drawings are different, corresponding parts are denoted by the same reference numerals, and description thereof is omitted.

(Embodiment 1)
In the present embodiment, for example, a transition metal oxide (for example, NiO) stacked on a first electrode (lower electrode) made of a noble metal (Pt or the like) is reduced to form a second electrode made of a transition metal. Since the (upper electrode) is formed, main problems (longer etching process and deterioration in processing accuracy) caused by processing the transition metal by reactive ion etching are solved.

(1) Element structure (resistance change element)
FIG. 1 is a cross-sectional view showing a configuration of a resistance change element 2 constituting a resistance change memory device (ReRAM) manufactured according to this embodiment and the vicinity thereof.

  The resistance change memory device (ReRAM) manufactured according to the present embodiment includes, for example, a first electrode (lower electrode) 4 made of a noble metal, a second electrode (upper electrode) 6 made of a transition metal, and a first The resistance change element 2 made of the transition metal oxide (transition metal oxide) 8 disposed between the electrode 4 and the second electrode 6 is provided. The resistance change element 2 is reversible and non-volatile. This is a resistance change memory device (ReRAM) using resistance change.

(2) Manufacturing Method FIG. 2 is a diagram for sequentially explaining a method of manufacturing a resistance change element according to this embodiment.

In the manufacturing method according to this embodiment, first, a first electrode (lower electrode) 4 and an oxide (transition metal oxide) 8 stacked on the first electrode (lower electrode) 4 are formed. The stacked body 16 is formed on a base 62 made of, for example, an insulating film (SiO ₂ or the like) (first step; FIG. 2A).

  Next, the oxide (transition metal oxide) 8 is reduced to form a second electrode (upper electrode) 6 (second step; FIG. 2B). In the example shown in FIG. 2B, only a part of the upper surface of the transition metal oxide 8 is reduced, but the entire upper surface of the transition metal oxide 8 may be reduced.

Here, the reduction of the oxide (transition metal oxide) 8 is performed by, for example, converting one or both of hydrogen (H ₂ ) and ammonia (NH ₃ ) into a reducing gas and converting these reducing gases into plasma. Can do. Alternatively, the substrate on which the oxide (transition metal oxide) 8 is formed may be heated to a high temperature and reacted with these reducing gases. At that time, the region of the transition metal oxide 8 that is not subjected to the reduction treatment has its surface covered with a SiO ₂ film or the like.

  In the variable resistance element 2 shown in FIG. 1, the first electrode (lower electrode) 4 is formed on the base 62 via the Ti film 106. However, the Ti film 106 is for improving the close contact between the base 62 and the first electrode (lower electrode) 4 and is not essential. The example shown in FIG. 2 is a manufacturing method when the Ti film 106 is not used.

In addition to NiO, for example, any transition metal oxide selected from the group consisting of TiO ₂ , HfO, ZrO, ZnO, WO ₃ , CoO, and Nb ₂ O ₅ may be used as the transition metal oxide 104. You can also.

(3) Effects As described above, in the present embodiment, the second electrode 6, that is, the transition metal electrode is formed by reducing the surface of the oxide (transition metal oxide) 8. Therefore, the step of etching the transition metal by RIE to form the transition metal electrode is not necessary. For this reason, according to the present embodiment, problems caused by processing the transition metal electrode by reactive ion etching (longer etching process and lower processing accuracy) are solved.

(Embodiment 2)
In this embodiment, an insulating film is formed on the base 62 and the stacked body 16 is embedded, and then the surface of the oxide (transition metal oxide) 8 is reduced to form the second electrode (transition metal electrode). Therefore, all of the above-mentioned problems caused by processing the transition metal by reactive ion etching (longer etching process, lower processing accuracy, and current-voltage characteristics) are all solved.

(1) Element structure (resistance change element)
The resistance change element 2 constituting the resistance change memory device (ReRAM) manufactured according to the present embodiment and the configuration in the vicinity thereof are the same as those described in the first embodiment (see FIG. 1).

(2) Manufacturing Method The manufacturing method according to the present embodiment includes all the manufacturing steps of the first embodiment. However, in the manufacturing method according to the present embodiment, the second step in the first embodiment is more concrete.

  FIG. 3 shows a method of manufacturing a resistance change memory device (ReRAM) according to this embodiment.

In this embodiment, first, a laminated body 16 including a first electrode (lower electrode) 4 and an oxide (transition metal oxide) 8 laminated on the first electrode (lower electrode) 4 is formed. For example, it is formed on the base 62 made of silicon dioxide (SiO ₂ ) (FIG. 3A).

  Here, the stacked body 16 is formed, for example, by depositing a noble metal film and a transition metal oxide film on the base 62 and forming a laminated structure composed of the noble metal film and the transition metal oxide film using an etching mask and chlorine gas as a reaction gas. It is formed by etching by RIE.

  Next, the insulating film 12 is formed on the base 62, and the stacked body 16 is embedded (FIG. 3B).

  Next, a contact hole 14 reaching the oxide (transition metal oxide) 8 is formed in the insulating film 12 (FIG. 3C).

  Next, the oxide (transition metal oxide) 8 exposed at the bottom of the contact hole 14 is reduced to form the second electrode (upper electrode) 6 (FIG. 3D).

  The insulating film 12 is polished by CMP (Chemical Mechanical Polishing) until the entire surface of the oxide (transition metal oxide) 8 is exposed without forming a contact hole, and then the oxide (Transition metal oxide) 8 may be reduced.

(3) Effect As described above, in the present embodiment, the second electrode, that is, the transition metal electrode is formed by reducing the surface of the oxide (transition metal oxide) 8 as in the first embodiment. It is formed. Therefore, main problems (longer etching process and worsening of processing accuracy) caused by processing the transition metal electrode by reactive ion etching are solved.

  Furthermore, in this embodiment, after the insulating film 12 is formed on the base 62, the surface of the oxide (transition metal oxide) 8 is reduced to form the second electrode (transition metal electrode) 6. Form.

  Therefore, even if the stacked body 16 composed of the first electrode (lower electrode) 4 and the oxide transition metal oxide 8 is formed by RIE using a chlorine-based reaction gas, the reaction gas remaining on the surface of the base 62. (Chlorine or the like) 140 is not confined by the insulating film 12 and does not diffuse. For this reason, the second electrode (transition metal electrode) is not corroded by the residual reaction gas (chlorine or the like) 140. Therefore, there is no possibility that the current-voltage characteristic of the resistance change element 2 is deteriorated.

  That is, according to the present embodiment, all the problems caused by processing the transition metal by reactive ion etching (long etching process, deterioration of processing accuracy, and current-voltage characteristic deterioration) are all solved. The

  The present embodiment relates to a method of manufacturing a resistance change memory device (ReRAM) that solves the above-described problems caused by processing a transition metal electrode by reactive ion etching.

  In the manufacturing method according to the present embodiment, the transition metal oxide (NiO) laminated on the first electrode (lower electrode; Pt electrode) 4 after the insulating film 12 is formed on the base 62. 8 is reduced to form a second electrode (upper electrode; Ni electrode) 6. Therefore, all the problems caused by processing the transition metal by reactive ion etching (longer etching process, deterioration in processing accuracy, and current-voltage characteristic deterioration) are all solved.

(1) Device Configuration FIG. 4 is a cross-sectional view of a memory cell 18 constituting a resistance change memory device (ReRAM) manufactured in this embodiment.

The resistance change memory device (ReRAM) in this embodiment is formed on a p-type semiconductor substrate 10. The semiconductor substrate 10 is separated into a plurality of element regions 22 by trenches 20 embedded with SiO ₂ .

  Two gate electrodes 26 are formed on the element region 22 via a gate insulating film 24. These gate electrodes 26 are arranged in parallel to each other. Further, on both sides of these gate electrodes 26, n-type impurity regions 28a and 28b formed by introducing n-type impurities at a high concentration on the surface of the element region 22 are arranged. (N-channel MOS FET) is formed.

  The n-type impurity region 28a is an impurity region (source) disposed between the gate electrode 26 and the trench 20, and the n-type impurity region 28b is an impurity region (drain) disposed between the two gate electrodes 26. ).

  As shown in FIG. 4, in this embodiment, the n-type impurity region 28b is used as an impurity region common to the two selection transistors T.

  These select transistors T are covered with a first interlayer insulating film 30 formed on the semiconductor substrate 10. The first interlayer insulating film 30 has first and second W plugs 32a and 32b formed by filling W (tungsten) into contact holes reaching the n-type impurity regions 28a and 28b from the upper surface thereof. Is provided. The first W plug 32a is connected to the n-type impurity region 28a, and the second W plug 32b is connected to the n-type impurity region 28b.

On the first interlayer insulating film 30, a first electrode (lower electrode) 4 made of Pt, a second electrode (upper electrode) 6 made of Ni, a first electrode (lower electrode) 4, A resistance change element 2 constituted by a transition metal oxide 8 made of NiO disposed between the second electrodes (upper electrodes) 6 is provided. Here, NiO _x (x is a positive number; 0 <x ≦ 1) may be used instead of NiO.

  The resistance change element 2 is disposed on the first W plug 32 a via the Ti film 106. The first electrode (lower electrode) 4 is electrically connected to the n-type impurity region 28a via the Ti film 106 and the first W plug 32a. The Ti film 106 improves the adhesion between the first interlayer insulating film 30 and the first electrode (lower electrode) 4, and the first W plug 32 a and the first electrode (lower electrode) 4 The electrical connectivity is also improved.

  A second interlayer insulating film 34 is formed on the first interlayer insulating film 30, and the resistance change element 2 and the Ti film 106 are covered with the second interlayer insulating film 34. The second interlayer insulating film 34 is provided with a third W plug 36 formed by filling W into a contact hole reaching the second W plug 32b from the upper surface thereof.

  The second interlayer insulating film 34 further includes a fourth W plug 38 formed by filling W into a contact hole that reaches the second electrode (upper electrode) 6 of the resistance change element 2 from the upper surface thereof. Is provided. A pad 40 and a first wiring 42 are formed on the second interlayer insulating film 34. The pad 40 is disposed on the third W plug 36. Here, the first wiring 42 passes over the fourth W plug 38 and is electrically connected to the second electrode (upper electrode) 6 of the resistance change element 2 via the fourth W plug 38. Yes.

  A third interlayer insulating film 44 is formed on the second interlayer insulating film 34, and the pad 40 and the first wiring 42 are covered with the third interlayer insulating film 44. The fourth interlayer insulating film 44 is provided with a fifth W plug 46 formed by filling W into a contact hole reaching the pad 40 from its upper surface. Here, the second wiring 48 is disposed on the fifth W plug 46, and the n-type impurity is interposed via the fifth W plug 46, the pad 40, the third plug 36, and the second plug 32b. It is electrically connected to the region 28b.

  In the resistance change memory (ReRAM) configured as described above, the second wiring 48 is a bit line, the gate electrode 26 of the selection transistor T is a word line, and the first wiring 42 is a ground line.

(2) Operation When the resistance change element 2 is set, the selection transistor T is turned on, and the first electrode (lower electrode) 4 is connected to the first voltage higher than the set voltage from the second wiring 48 (bit line). The voltage pulse (positive voltage pulse) is applied.

  Since the variable resistance element 2 is brought into a low resistance state by the application of the first voltage pulse, an excessive current flows through the variable resistance element 2 as it is. Therefore, a limiter is provided in the peripheral circuit of the resistance change memory (ReRAM) to limit the current flowing through the resistance change element 2 to a predetermined value or less.

  Also, when resetting the resistance change element 2, the selection transistor T is turned on so that the reset current flows from the second wiring 48 (bit line) to the first electrode (lower electrode) 4. Is applied, but a second voltage pulse (positive voltage pulse) smaller than the set voltage is applied.

  When the resistance state of the resistance change element 2 is detected, the selection transistor T is turned on, and the reset current does not flow between the second wiring (bit line) 48 and the first wiring 42 (ground line). A third voltage is applied to detect the magnitude of the current flowing through the second wiring 48 (bit line).

  Here, the polarity of the first and second voltage pulses and the sign of the third voltage are positive, and the height of the second voltage pulse (reset voltage) is the third voltage (resistance state detection). Higher than the voltage). The height of the first voltage (setting voltage) is higher than the height of the second voltage (resetting voltage).

  As is clear from the above description, a positive potential is applied to the first electrode (lower electrode) 4 made of a noble metal with respect to the second electrode (upper electrode) 6 made of a transition metal. By doing so, the variable resistance element 2 operates stably (when a negative potential is applied to the noble metal electrode with respect to the transition metal electrode, the set and reset become unstable).

(3) Manufacturing method
5 to 8 are cross-sectional views showing the method of manufacturing the resistance change memory device (ReRAM) described above in the order of steps. Normally, peripheral circuits (such as a writing circuit and a reading circuit) are formed on a semiconductor substrate simultaneously with the memory cells, but these are omitted here.

(I) Structure shown in FIG. 5A First, steps required until a structure shown in FIG. As shown in FIG. 5A, trenches 20 filled with SiO ₂ are formed in a predetermined region of a p-type semiconductor substrate (silicon substrate) 10 by a known STI (Shallow Trench Isolation) method. The surface of the semiconductor substrate 10 is separated into a plurality of element regions 22 by the trench 20.

  Next, the surface of the element region 22 is thermally oxidized to form the gate insulating film 24. Thereafter, a polysilicon film is formed on the entire upper surface of the semiconductor substrate 10 by a CVD (Chemical Vapor Deposition) method, and the polysilicon film is patterned by a photolithography method and an etching method to form the gate electrode 26. At this time, as shown in FIG. 5A, two gate electrodes 26 serving as word lines are arranged on one element region 22 in parallel to each other.

  Next, using the gate electrode 26 as a mask, an n-type impurity such as phosphorus (P) is ion-implanted into the element region 22 at a low concentration to form an n-type low-concentration impurity region (not shown).

Next, sidewalls (not shown) are formed on both sides of the gate electrode 26. The sidewall is formed by forming an insulating film made of SiO ₂ or SiN on the entire upper surface of the semiconductor substrate 10 by CVD and then etching back the insulating film to leave only on both sides of the gate electrode 26. .

  Thereafter, n-type impurities are ion-implanted at a high concentration into the element region 22 using the gate electrode 26 and the sidewall as a mask to form an n-type high-concentration impurity region (not shown).

  In this manner, n-type impurity regions 28 a and 28 b are formed which are composed of the low concentration impurity region and the high concentration impurity region, and the low concentration impurity region is in contact with the channel region immediately below the gate insulating film 24. That is, a transistor T having an LDD (Lightly Doped Drain) structure source / drain is formed in each transistor formation region.

(Ii) Structure shown in FIG. 5B Next, steps required until the structure shown in FIG. After the transistor T is formed by the above-described process, for example, a SiO ₂ film is formed as the first interlayer insulating film 30 on the entire upper surface of the semiconductor substrate 10 by the CVD method, and the transistor T is covered with the interlayer insulating film 30. Thereafter, the surface of the first interlayer insulating film 30 is polished and planarized by a CMP (Chemical Mechanical Polishing) method.

  Next, contact holes reaching the n-type impurity regions 28a and 28b from the upper surface of the first interlayer insulating film 30 are formed by using a photolithography method and an etching method. Then, after forming a TiN film (not shown) as a barrier metal on the entire upper surface of the semiconductor substrate 10 by sputtering, a W film is formed on the TiN film by sputtering or CVD, and in the contact hole. Fill with W. Thereafter, the W film and the TiN film are polished by CMP until the first interlayer insulating film 30 is exposed. In this way, the first and second W plugs 32a and 32b are formed by filling the contact holes with W. Here, the first W plug 32a is a plug connected to the n-type impurity region 28a, and the second W plug 32b is a plug connected to the n-type impurity region 28b.

(Iii) Structure shown in FIG. 5C Next, steps required until the structure shown in FIG.

  After the first and second W plugs 32a and 32b are formed by the above-described steps, the Ti film 52 is formed on the first interlayer insulating film 30 and the first and second W plugs 32a and 32b by the sputtering method. Is formed to a thickness of 20 nm, for example.

  Thereafter, by sputtering, as shown in FIG. 5C, a Pt film 54 to be the first electrode (lower electrode) 4 and NiO to be the resistance change layer 105 (transition metal oxide 8) are formed on the Ti film 52. A film 56 is formed sequentially. The thickness of the Pt film 54 is 50 nm, for example, and the thickness of the NiO film 56 is 100 nm, for example.

Note that NiO _x (x is a positive number; 0 <x ≦ 1) may be formed instead of NiO.

(Iv) Structure shown in FIGS. 6A to 6C Next, steps required until the structure shown in FIGS. 6A to 6C is formed will be described.

  An etching mask (not shown) made of a photoresist film is formed on the surface of the NiO / Pt / Ti laminated structure 58 made of the Ti film 52, the Pt film 54, and the NiO film 56 formed by the above-described steps. Using this etching mask, the NiO / Pt / Ti laminated structure 58 is etched by RIE using chlorine gas as a reaction gas. In this way, the first electrode (lower electrode) 4 made of Pt and the stacked body 16 made of the transition metal oxide 8 (NiO) stacked on the first electrode (lower electrode) 4 are It is formed on a base 62 made of one interlayer insulating film 30.

Next, as shown in FIG. 6B, the insulating film 12 (for example, SiO ₂ ) to be the second interlayer insulating film 34 is formed on the base 62 made of the first interlayer insulating film 30 by the CVD method. And the laminated body 16 is embedded.

  Next, as shown in FIG. 6C, a contact hole 64a reaching the stacked body 16 from the upper surface of the insulating film 12 is formed by using a photolithography method and an etching method. At the same time, a contact hole 64b reaching the second W plug 32b is formed.

  (V) Structure shown in FIG. 7A (reduction process) Next, steps required until the structure shown in FIG.

  The transition metal oxide 8 (NiO) exposed at the bottom of the contact hole 64a formed by the above process is reduced to form a second electrode (upper electrode) 6 made of Ni. By this reduction treatment, the resistance change element 2 constituted by the first electrode (lower electrode) 4 made of Pt, the second electrode (upper electrode) 6 made of Ni, and the transition metal oxide 8 made of NiO is obtained. It is formed.

The reduction process is performed by exposing the transition metal oxide 8 (NiO) exposed at the bottom of the contact hole 64a to plasma generated from ammonia gas (NH ₃ ).

  The plasma is supplied with ammonia gas at a flow rate of 100 cc / min to a plasma generator (not shown), and 400 W radio frequency (RF) power is input to the plasma generator while maintaining the pressure at 5 Pa. Generate.

  The semiconductor substrate 10 on which the structure shown in FIG. 6C is formed is heated to 350 ° C. in this plasma generator and exposed to the generated ammonia plasma for 1 minute. Then, the transition metal oxide 8 (NiO) is reduced to form Ni.

  The above processing conditions are an example, and the reduction process for forming the second electrode (upper electrode) 6 does not necessarily have to be performed under such conditions. Table 1 illustrates the conditions for the reduction treatment of the transition metal oxide 8 made of NiO. Table 1 shows the substrate temperature, the type and supply speed of the plasma generation gas, the pressure of the plasma generation gas, the high frequency power (RF power) input to the plasma generation apparatus, and the processing time.

Condition 1 in Table 1 is the above-described reduction treatment condition. Condition 2 and condition 3 are a case where a mixed gas of hydrogen gas (H ₂ ) and ammonia (NH ₃ ) gas is used as a plasma generation gas, respectively, and hydrogen gas (H ₂ ) and nitrogen (H ₂ ) gas. This is a processing condition in the case of using the mixed gas.

尚、コンタクトホール６４ａを通して遷移金属酸化物８を還元する際、コンタクトホール６４ｂの底に露出した第２のプラグ３２ｂの頂上も還元処理用のプラズマに曝される。しかし、後に形成される第３のプラグ３６との電気的接続には何ら支障は生じない。

When the transition metal oxide 8 is reduced through the contact hole 64a, the top of the second plug 32b exposed at the bottom of the contact hole 64b is also exposed to the reduction plasma. However, there is no problem with the electrical connection with the third plug 36 formed later.

(V) Structure shown in FIG. 7B Next, steps required until the structure shown in FIG.

  After the variable resistance element 2 is formed by the above-described process, a TiN film (not shown) is formed as a barrier metal on the entire upper surface of the semiconductor substrate 10, and then a W film is formed on the barrier metal by sputtering or CVD. At the same time, the contact holes 64a and 64b are filled with W.

  Thereafter, the W film and the TiN film are polished by CMP until the second interlayer insulating film 34 is exposed. In this way, the fourth W plug 38 electrically connected to the second electrode (upper electrode) 6 of the resistance change element 2 is formed. At this time, a third W plug 36 electrically connected to the second W plug 32b is also formed at the same time.

(Vi) Formation of the structure shown in FIG. 8A Next, steps required until the structure shown in FIG.

  After the third and fourth W plugs 36 and 38 are formed by the above-described process, the conductive layer made of a metal such as aluminum or copper is formed on the second interlayer insulating film 34 and the W plugs 36 and 38 by sputtering. A film is formed. Then, the conductive film is patterned by a photolithography method and an etching method to form a pad 40 and a first wiring (ground line) 42. The pad 40 is formed on the third W plug 36 and is electrically connected to the third W plug 36. The first wiring 42 passes over the fourth W plug 38 and is electrically connected to the fourth W plug 38.

(Vii) Structure shown in FIG. 8 (b) Processes until the structure shown in FIG. 8 (b) is formed will be described. After the pad 40 and the first wiring 42 are formed by the above-described process, a fourth interlayer insulating film 44 made of SiO ₂ is formed on the entire upper surface of the semiconductor substrate 10 by the CVD method. Then, the fourth interlayer insulating film 44 is polished by the CMP method to planarize the surface, and then reaches the pad 40 from the upper surface of the fourth interlayer insulating film 44 using the photolithography method and the etching method. A contact hole is formed.

  Thereafter, a TiN film (not shown) is formed as a barrier metal on the entire upper surface of the semiconductor substrate 10 by sputtering, and then a W film is formed on the TiN film by sputtering or CVD, and in the contact hole. Fill with W. Next, the W film and the TiN film are polished by CMP until the fourth interlayer insulating film 44 is exposed. In this way, the fifth W plug 46 in which the contact hole is filled with W is formed.

  Next, a conductive film (not shown) having a laminated structure of, for example, TiN / Al / TiN / Ti is formed on the fourth interlayer insulating film 44 and the fifth W plug 46 by sputtering. Then, the conductive film is patterned using a photolithography method and an etching method to form a second wiring (bit line) 48 as shown in FIG. In this way, the resistance change memory device (ReRAM) according to this embodiment can be manufactured.

(Viii) Effect In this example, as shown in the above “(v) structure shown in FIG. 7A (reduction treatment)”, the transition metal electrode 6 made of Ni is used as the transition metal oxide 8 made of NiO. Is formed by reduction treatment. Therefore, it is not necessary to etch transition metals (Ni or the like) having a low etching rate by RIE using a chlorine-based gas, so that the etching process takes a long time or the processing accuracy of the transition metal electrode 8 is deteriorated. There is no.

  Further, as shown in the following “element characteristics”, the transition metal electrode is not corroded by the reaction gas (such as chlorine) remaining on the base, and the current-voltage characteristics are not deteriorated.

(4) Element Characteristics The characteristics of the resistance change element constituting the resistance change memory (ReRAM) formed as described above will be described.

  FIG. 9 shows current-voltage characteristics of the resistance change element 2 in which the transition metal electrode 6 made of Ni is formed by the reduction treatment described above, that is, the resistance change element in this embodiment. On the other hand, FIG. 10 shows a current-voltage characteristic of a resistance change element (see FIG. 16) in which a transition metal electrode 6 is formed by etching a Ni film by RIE using chlorine as a reaction gas as a comparative example.

  In both FIG. 9 and FIG. 10, the horizontal axis (linear display) is voltage, and the vertical axis (log display) is current. Here, r1, r2, and r3 represent the first-time, second-time, and third-time transitions from the low-resistance state to the high-resistance state (that is, reset), respectively. Further, s1, s2, and s3 represent the first-time, second-time, and third-time transitions (ie, sets) from the high-resistance state to the low-resistance state, respectively.

  In both the variable resistance element of this example and the comparative example, a current path was formed from the beginning, and forming was unnecessary. Further, the reset current was about 1 mA in both of the present example and the comparative example.

  On the other hand, the voltage (set voltage) for transition from the high resistance state to the low resistance state is about 1.7 V in the comparative example, but is about 1.2 V in the present embodiment. Further, the variation in the set voltage is smaller than that in the comparative example. This is because in this embodiment, the reaction gas (chlorine or the like) 140 attached to the base 62 by RIE is confined by the second interlayer insulating film 34, and the transition metal electrode 6 is not corroded.

(5) Operating Voltage The resistance change element (ReRAM) in this embodiment can be operated as follows based on the current-voltage characteristics of FIG.

(I) Data writing Data writing, that is, setting and resetting of the resistance change element is performed as follows, for example.

  First, for the transition (set) from the high resistance state to the low resistance state, for example, a voltage pulse of 2 V is applied to the resistance change element. Then, the variable resistance element in the high resistance state transitions to the low resistance state as s1 to s3 in FIG. In this state, a large current flows through the variable resistance element. However, the limiter provided in the peripheral circuit of the resistance change memory (ReRAM) limits the current flowing through the resistance change element to 1 mA or less, for example, 0.8 mA.

  On the other hand, for transition (reset) from the low resistance state to the high resistance state, for example, a voltage pulse of 1 V is applied to the resistance change element. Then, a reset current flows through the resistance change element in the low resistance state, and transitions to the high resistance state as r1 to r3 in FIG. Note that the width of the voltage pulse used for setting and resetting is, for example, 100 ns.

(Ii) Data read Data is read as follows. A voltage that is lower than a voltage that causes a reset current to flow through the variable resistance element, for example, 0.4 V, is applied to the variable resistance element to detect a flowing current. If almost no current flows, the resistance change element is determined to be in a high resistance state, and if current flows, it is determined to be in a low resistance state.

  If the resistance state is low, for example, data “1” is read. On the other hand, if the resistance state is high, for example, data “0” is read.

  In the above-described embodiments and examples, the example in which the present invention is applied to a stacked resistance change memory device (ReRAM) has been described. However, the present invention may be applied to a planar type ReRAM.

  The present invention can be used in the semiconductor device manufacturing industry, particularly in the semiconductor memory device manufacturing industry.

2 is a cross-sectional view illustrating a configuration of a resistance change element and its vicinity in a resistance change memory (ReRAM) according to Embodiment 1. FIG. It is a figure explaining sequentially the manufacturing method of the resistance change element concerning Example 1 of an embodiment. It is a figure explaining the manufacturing method of the resistance change memory device (ReRAM) based on Embodiment 2 in order of a process. It is sectional drawing of the memory cell which comprises the resistance change memory device (ReRAM) manufactured in the Example. FIG. 6 is a cross-sectional view (No. 1) for explaining the method of manufacturing the resistance change memory device (ReRAM) according to the embodiment in order of processes. FIG. 6 is a sectional view (No. 2) for explaining the method of manufacturing the resistance change memory device (ReRAM) according to the embodiment in order of steps. FIG. 6 is a sectional view (No. 3) for explaining the method of manufacturing the resistance change memory device (ReRAM) according to the embodiment in the order of steps. FIG. 8 is a sectional view (No. 4) for explaining the method of manufacturing the resistance change memory device (ReRAM) according to the embodiment in the order of steps. It is a figure which shows the electric current-voltage characteristic of the resistance change element in a present Example. It is a figure which shows the electric current-voltage characteristic of the resistance change element in a comparative example. It is sectional drawing explaining the structure of a resistance change element and its periphery in the conventional resistance change memory (ReRAM). It is a figure explaining the state change of a Pt / NiO / Pt resistance change element. It is a figure explaining the operation | movement model of the state change of a Pt / NiO / Pt resistance change element. It is a figure explaining the current-voltage characteristic of a Pt / NiO / Pt resistance change element. It is a schematic sectional drawing of the sample used in order to measure the current-voltage characteristic of a Pt / NiO / Pt resistance change element. It is sectional drawing explaining the structure of a Pt / NiO / Ni resistance change element and its periphery. FIG. 6 is a diagram (part 1) for sequentially explaining a process of forming a Pt / NiO / Ni resistance change element by RIE; FIG. 8 is a diagram (No. 2) for sequentially explaining the process of forming the Pt / NiO / Ni resistance change element by RIE; It is a top view explaining the state of the Pt / NiO / Ni resistance change element processed by the reactive ion etching by chlorine gas.

Explanation of symbols

2 ... variable resistance element in the present invention 4 ... first electrode (lower electrode)
6 ... Second electrode (upper electrode) 8 ... Oxide (transition metal oxide)
DESCRIPTION OF SYMBOLS 10 ... Semiconductor substrate 12 ... Insulating film 14 ... Contact hole 16 ... Laminated body 18 ... Memory cell 20 ... Trench 22 ... Element region 24 ... Gate insulating film 26. ..Gate electrodes 28a, 28b... N-type impurity region 30... First interlayer insulating film 32a... First W plug 32b... Second W plug 34. Insulating film 36 ... Third W plug 38 ... Fourth W plug 40 ... Pad
42 ... first wiring (ground line) 44 ... fourth interlayer insulating film 46 ... fifth W plug 48 ... second wiring (bit line)
52 ... Ti film 54 ... Pt film 56 ... NiO film 58 ... NiO / Pt / Ti laminated structure 62 ... Base 64a, 64b ... Contact hole 100 ... Conventional resistance change element
101 ... Pt / NiO / Ni variable resistance element 102a ... Upper electrode (Pt, etc.)
102b ... Lower electrode (Pt, etc.) 104 ... Transition metal oxide (NiO, etc.)
105 ... variable resistance layer 106 ... Ti film 108 ... TiN film 110 ... base 112 ... first contact hole 114 ... plug (W) 115 ... first wiring 116 ... Interlayer insulating film 118 ... Second contact hole 120 ... Second plug 122 ... Second wiring 124 ... Filament 126 ... Substrate 128 ... Ni film 130 ... NiO film 132 Pt film 134 first etching mask 136 second etching mask 140 reactive gas (chlorine etc.) 142 residue 144 144 corrosion mark

Claims (5)

A first electrode;
A second electrode made of a transition metal;
Comprising a resistance change element made of an oxide of the transition metal, disposed between the first electrode and the second electrode;
In a method of manufacturing a resistance change memory device using a reversible and nonvolatile resistance change of the resistance change element,
A first step of forming the first electrode and a stack of oxides stacked on the first electrode on a base;
And based on changing a part of the upper surface of the stacked the oxide, by comprising a second step of forming the second electrode, wherein the oxide is disposed between the first electrode A method of manufacturing a resistance change memory device. The method of manufacturing a resistance change memory device according to claim 1,
The second process is a process of forming the second electrode by reducing the oxide using one or both of hydrogen and ammonia as a reducing gas, and manufacturing the resistance change memory device, Method. In the manufacturing method of the resistance change memory device according to claim 1 or 2,
The second step includes
A third step of forming an insulating film on the base and embedding the stacked body;
A fourth step of forming a contact hole reaching the oxide in the insulating film;
A method of manufacturing a resistance change memory device, comprising a fifth step of forming the second electrode by reducing the oxide exposed at the bottom of the contact hole. In the manufacturing method of the resistance change memory device according to claim 1,
A method of manufacturing a resistance change memory device, wherein the transition metal is nickel. The method of manufacturing a resistance change memory device according to claim 1,
The second electrode is grounded;
The method of manufacturing a resistance change memory device, wherein the first electrode is connected to a bit line to which a positive potential is applied through a transistor having a gate connected to a word line.

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