JP5363366B2 - Display system, input / output device, and display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display system capable of performing rewriting of setting information in a short period of time. <P>SOLUTION: The display system includes an input and output device in which video data and rewrite data of setting information are input and output, and a display device receiving the output data of the input and output device. The display device includes: a determination unit of determining whether an input signal from the input and output device is the video data or the rewrite data; a second selecting unit that outputs the input signal when the input signal is the video data and that does not output the input signal when the input signal is the rewrite data; and a write control unit that writes the rewrite data in a memory when the input signal is the rewrite data. <P>COPYRIGHT: (C)2011,JPO&amp;INPIT

Description

  The present invention relates to a display system for rewriting setting information, an input / output device, and a display device.

A field programmable gate array (FPGA) is an integrated circuit that allows a user to change circuit configuration information after manufacture, and is currently used in various devices.
For example, the FPGA is installed on a print (PT) board. When the FPGA is rewritten, the rewrite tool and the printed board having the FPGA are usually connected on a one-to-one basis.

FIG. 1 is a diagram illustrating a conventional FPGA rewriting method.
The display system 10 includes a display panel 11, a video input printed board 13, and a personal computer (PC) 14 for FPGA rewriting.

The display board 11 is connected to a video input printed board 13.
For example, video data is input to the video input printed board 13 via a DVI (Digital Visual Interface), HD-SDI (High Definition Serial Digital Interface), or the like from a PC (not shown), and is in a format suitable for the display board 11. And output to the display panel 11.

The display board 11 includes a plurality of printed boards 12-n (n = 1 to 4).
The printed board 12 controls the display board 11. The printed board 12 includes an FPGA.

  For example, when the user wants to rewrite the FPGA of the printed board 12-1, the user connects the PC 14 for FPGA rewriting to the printed board 12-1, transmits rewritten data, and rewrites the FPGA.

JP 2005-165435 A JP 2008-136184 A

  However, when rewriting a plurality of FPGAs, it is necessary to connect a PC and transmit the rewrite data of the FPGA to a printed board provided with each FPGA, and there is a problem that it takes much time and effort.

  An object of the present invention is to provide a display system capable of rewriting setting information in a short time.

  According to an aspect of the present invention, a display system includes an input / output device that inputs and outputs video data and setting information rewrite data, and a display device that receives output data of the input / output device.

The input / output device includes a first selection unit that outputs the video data or the rewrite data in response to a switching signal indicating presence / absence of the rewrite data.
The display device determines whether an input signal from the input / output device is the video data or the rewrite data, and outputs the input signal when the input signal is the video data. A second selection unit that does not output the input signal when the input signal is rewrite data, and a write control unit that writes the rewrite data to the memory when the input signal is rewrite data.

  According to the present invention, the setting information can be rewritten in a short time.

It is a figure which shows the conventional FPGA rewriting method. It is a figure which shows the block diagram of the display system at the time of the video display which concerns on 1st Embodiment. It is a figure which shows the block diagram of the display system at the time of FPGA rewriting which concerns on 1st Embodiment. It is a block diagram of the printed circuit board for video input which concerns on 1st Embodiment. It is a block diagram of the switching part of the printed circuit board for video inputs which concerns on 1st Embodiment. It is a figure which shows the state of the signal at the time of the video signal output of 1st Embodiment. It is a figure which shows the state of the signal at the time of FPGA rewriting of 1st Embodiment. It is a block diagram of the printed board of the display board which concerns on 1st Embodiment. It is a block diagram of the switching part of the printed board of the display board which concerns on 1st Embodiment. It is a block diagram of the switching part of the printed circuit board for video inputs which concerns on 2nd Embodiment. It is a figure which shows the state of the signal at the time of the video signal output of 2nd Embodiment. It is a figure which shows the state of the signal at the time of FPGA rewriting of 2nd Embodiment. It is a block diagram of the switching part of the printed board of the display board which concerns on 2nd Embodiment.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 2 is a diagram illustrating a configuration diagram of the display system at the time of video display according to the embodiment.
The display system 100 includes an image input printed board 101 and a display board 111.

  The video input printed board 101 is connected to a PC (personal computer) (not shown) that outputs video, a video sending device (not shown), or the like by DVI, HD-SDI, or the like. The video input printed board 101 is connected to the display board 111.

The video input printed board 101 converts a video signal input from a PC that outputs video into data of a format used by the display board 111 and outputs the data to the display board 111.
The display board 111 includes printed boards 112-1 and 112-2.

  A video signal is input from the video input print board 101 to the print board 112-1. Also, the printed board 112-1 outputs the video signal input from the video input printed board 101 to the printed board 112-2. In this way, the printed board 112 outputs the video signal to another printed board (next-stage printed board). That is, the signal input from the video input printed board 101 is input to all printed boards of the display board 111.

  The printed board 112 performs adjustment such as color tone correction and trimming on the video signal, and displays the video on the display panel 111. Adjustments such as color correction and trimming are performed by an FPGA provided in the printed board 112.

Note that the number of printed boards provided on the display board 111 is not limited to two, and may be an arbitrary number depending on the size of the display board.
FIG. 3 is a diagram showing a configuration diagram of the display system at the time of FPGA rewriting according to the embodiment.

In the following description, since the thing which attached | subjected the same code | symbol in drawing has the same thing and the same effect, description may be abbreviate | omitted.
The display system 100 includes a video input printed board 101, a display board 111, and an FPGA rewriting PC 121.

  The FPGA rewriting PC 121 is connected to the video input printed board 101. The FPGA rewrite PC 121 outputs a rewrite mode, a rewritten print board ID, rewrite data, a rewrite clock, a rewrite state signal, and a switching signal to the video input print board 101 when rewriting the FPGA.

The video input printed board 101 outputs the FPGA rewritten data, the rewritten printed board ID, and the like to the display board 111. At this time, the FPGA rewrite data is transmitted through the same signal line as the signal line that transmitted the above video signal.
Of the printed boards 112, the printed board 112 corresponding to the rewritten printed board ID rewrites the FPGA with the input FPGA rewritten data.

FIG. 4 is a configuration diagram of the video input printed board according to the first embodiment.
The video input printed board 101 includes a video input unit 201, a data receiving unit 202, a switching unit 203, a video memory 204, a setting switch 205, and a video output unit 206.
The video input unit 201 receives a video signal input from a PC that outputs video, and outputs the video signal to the switching unit 203.

The data receiving unit 202 receives the FPGA rewriting data, the switching signal, and the rewriting printed board ID input from the FPGA rewriting PC 121 and outputs them to the switching unit 203.
The switching unit 203 appropriately selects a video signal, FPGA rewrite data, or the like and outputs the video signal or FPGA rewrite data to the video output unit 206. Details of the switching unit 203 will be described later.

The video memory 204 is a memory that temporarily stores video signals.
The setting switch 205 outputs various setting data used by the switching unit 203 to the switching unit 203.
The video output unit 206 outputs the signal input from the switching unit 203 to the display panel 111.

FIG. 5 is a configuration diagram of the switching unit of the video input printed board according to the first embodiment.
In the first embodiment, the video signal is a 10-bit parallel signal for each color of RGB. Specifically, the red signal is R [0] to R [9], the green signal is G [0] to G [9], and the blue signal is B [0] to B [9]. It shall be represented by

  The switching unit 203 receives R [0] to R [9] and G [0] to G as video signals from a PC (not shown) that outputs video and a video transmission device (not shown) via the video input unit 201. [9], B [0] to B [9], vertical synchronization signal VSYNC, horizontal synchronization signal HSYNC, and video clock CLK are input.

  Further, the rewrite mode, rewrite printed board ID, rewrite data, rewrite clock, rewrite status signal, and switch signal are input to the switching unit 203 from the FPGA rewriting PC 121 via the data receiving unit 202.

The rewrite mode is information indicating that the FPGA is rewritten.
The rewritten printed board ID is information for identifying a printed board on which the FPGA is rewritten.
The rewrite data is, for example, FPGA configuration information.

The rewrite clock is a clock signal indicating timing at the time of FPGA rewriting.
The rewrite state signal is a signal indicating the rewrite state of the FPGA, for example, during rewrite or after rewrite.

The switching signal is a signal that is turned on when the FPGA is rewritten and turned off for video display.
The switching unit 203 includes a data conversion unit 301, a selector 302, a selector 303-p (p = 0 to 3), and a buffer 304.

  The data conversion unit 301 converts the rewrite mode and rewrite printed board ID respectively input from the FPGA rewrite PC 121 into continuous serial signals (hereinafter, rewrite mode + ID), and outputs them to the selector 302.

The selector 302 receives a rewrite mode + ID, a blank signal BLANK, and a vertical synchronization signal VSYNC. The blank signal BLANK is generated by the setting switch 205, for example.
The selector 302 selects the rewrite mode + ID when VSYNC is off (blank period), selects BLANK when VSYNC is on (other than the blank period), and outputs it to the selector 303-0.

  The selector 303-0 receives the switching signal, the signal R [0], and the output signal of the selector 302. The selector 303-0 selects the output signal of the selector 302 when the switching signal is on, selects the signal R [0] when the switching signal is off, and outputs the signal R [0] to the video output unit 206. .

  The selector 303-1 receives a switching signal, a signal R [1], and rewrite data. The selector 303-1 selects the rewrite data when the switching signal is on, selects the signal R [1] when the switching signal is off, and outputs it to the video output unit 206 as the signal R [1].

  The selector 303-2 receives the switching signal, the signal R [2], and the rewrite clock. The selector 303-1 selects the rewrite clock when the switching signal is on, selects the signal R [2] when the switching signal is off, and outputs the signal R [2] to the video output unit 206.

The selector 303-3 receives the switching signal, the signal R [3], and the rewrite state signal. The selector 303-1 selects the rewrite state signal when the switching signal is on, selects the signal R [3] when the switching signal is off, and outputs the signal R [3] to the video output unit 206.
The signals R [4] to R [9], G [0] to G [9], B [0] to B [9], the vertical synchronization signal VSYNC, the horizontal synchronization signal HSYNC, and the video clock CLK pass through the buffer 304. To the video output unit 206.

FIG. 6 is a diagram illustrating a signal state when the video signal is output according to the first embodiment.
In FIG. 6, signals R [0] to R [9], signals G [0] to G [9], and signals B [0] to B [9] are collectively shown. Here, R [0] to R [9] are combined into R [0..9], G [0] to G [9] are combined into G [0..9], B [0] to B [ 9] are collectively represented as B [0..9].

When the video signal is output, R [0..9] becomes a blank signal when VSYNC is off (blank period) and red video data when VSYNC is on.
When the video signal is output, G [0..9] is a blank signal when VSYNC is off and green video data when VSYNC is on.

When the video signal is output, B [0..9] is a blank signal when VSYNC is off and blue video data when VSYNC is on.
When outputting a video signal, CLK is a video clock and HSYNC is a horizontal synchronization signal.

FIG. 7 is a diagram illustrating a signal state when the FPGA is rewritten according to the first embodiment.
FIG. 7 shows the states of signals used as signals R [0] to R [3] at the time of VSYNC and video signal output, and R [4] to R [9] (hereinafter R [4..9]). ), B [0..9], G [0..9], CLK, and HSYNC are omitted.

At the time of FPGA rewriting, the signal R [0] is a rewriting mode + ID when VSYNC is off and a blank signal when VSYNC is on.
When rewriting the FPGA, the signal R [1] is a blank signal when VSYNC is off and rewritten data when VSYNC is on.

During FPGA rewrite, the signal R [2] is a blank signal when VSYNC is off and a rewrite clock when VSYNC is on.
During FPGA rewrite, the signal R [3] is a blank signal when VSYNC is off and a rewrite status signal when VSYNC is on.
When the FPGA is rewritten, the signals R [4..9], B [0..9], G [0..9], CLK, and HSYNC become blank signals.

FIG. 8 is a configuration diagram of a printed board of the display board according to the first embodiment.
The printed board 112-1 includes a reception unit 401, a switching unit 402, a configuration memory 403, an FPGA 404, a setting switch 405, a transmission driver 406, and a display control output unit 407.

The receiving unit 401 receives a signal from the video input printed board 101 and outputs the signal to the switching unit 402 and the transmission driver 406.
The switching unit 402 outputs an input signal to the PFGA 404 and the configuration memory 403. Details of the switching unit 402 will be described later.

The configuration memory 403 stores configuration information of the FPGA 404 circuit.
The FPGA 404 reads configuration information of the FPGA circuit from the configuration memory 403 when the printed board 112-1 is activated, and operates based on the configuration information. The FPGA 404 performs adjustment such as color tone correction and trimming, for example.

  Note that the rewriting of the FPGA means the rewriting of the configuration memory when the configuration memory storing the configuration information of the FPGA circuit is provided as in the present embodiment. Further, when the configuration memory is not provided on the printed board, the FPGA configuration information is rewritten to the FPGA. Therefore, the FPGA rewriting means rewriting to the FPGA.

The setting switch 405 outputs data used in the switching unit 402 or the FPGA to the switching unit 402 and the FPGA.
The transmission driver 406 outputs an input signal to the other printed board 112-2.
The display control output unit 407 displays data on a display unit (not shown) of the display panel 111.

FIG. 9 is a configuration diagram of the switching unit of the printed board of the display board according to the first embodiment.
The switching unit 402 includes a mode determination unit 501, a selector 502, a write control unit 503, and a buffer 504.

The vertical synchronization signal VSYNC, horizontal synchronization signal HSYNC, and video clock CLK are input to the FPGA 404 via the buffer 504.
The mode determination unit 501 receives signals R [0..9], G [0..9], B [0..9], and a vertical synchronization signal VSYNC. Hereinafter, the signals R [0..9], G [0..9], and B [0..9] are collectively expressed as signals RGB [0..9].

  Further, the printed circuit board setting ID is input from the setting switch 405 to the mode determination unit 501. The printed board setting ID is a number or symbol assigned to each printed board to identify the printed board.

  The mode determination unit 501 outputs the signal RGB [0..9] to the selector 502 and the write control unit 503, the mode switching signal to the selector 502, and the rewrite permission signal to the write control unit 503.

The mode determination unit 501 checks the signal R [0] when the vertical synchronization signal VSYNC is off (blank period).
When the signal R [0] is a blank signal, since the input signal is video data, the mode switching signal and the rewrite permission signal are turned off.

  When the signal R [0] is the rewrite mode + ID, the ID included in the rewrite mode + ID is compared with the printed board setting ID to check whether they match. When the ID included in the rewrite mode + ID of the signal R [0] matches the printed board setting ID, the mode switching signal and the rewrite permission signal are turned on because the printed board is the target of rewriting. When the ID included in the rewrite mode + ID of the signal R [0] does not match the printed board setting ID, the mode switching signal is turned on and the rewrite permission signal is turned off.

  The selector 502 receives black display data from a switch (not shown). The black display data is data for displaying a black screen on the display board. The selector 502 receives the signal RGB [0..9] and the mode switching signal from the mode determination unit 501.

  The selector 502 selects black display data and outputs it to the FPGA 404 when the mode switching signal is on. As a result, when the FPGA is rewritten, the display panel is displayed in black. When the mode switching signal is off, the selector 502 outputs the signal RGB [0..9] (the signal RGB [0..9] is video data because the mode switching signal is off) to the FPGA 404. In this embodiment, the black display data is selected when the mode switching signal is on. However, the present invention is not limited to this. Also good.

The write control unit 503 writes the rewrite data (signal R [1]) to the configuration memory 405 according to the rewrite clock (signal R [2]) when the rewrite permission signal is on.
The write controller 503 does not write to the configuration memory 405 when the rewrite permission signal is off.

Next, a second embodiment in which the video signal is a serial signal will be described.
In the second embodiment, the configuration of the display system, the video input printed board, the display board, and the printed board of the display board is the same as that of the first embodiment, and the description thereof will be omitted.

FIG. 10 is a configuration diagram of the switching unit of the video input printed board according to the second embodiment.
In the second embodiment, the video signal is a 10-bit serial signal for each color of RGB. Specifically, the switching unit 207 corresponds to the switching unit 203 in FIG. 4, assuming that the red signal is represented by R, the green signal is represented by G, and the blue signal is represented by 10 bits of each color.

The switching unit 207 receives signals R, G, B, a vertical synchronization signal VSYNC, and a video clock CLK as video signals from a PC that outputs video via the video input unit 201.
Also, the rewrite mode, rewrite printed board ID, rewrite data, rewrite clock, rewrite status signal, and switch signal are input to the switching unit 207 from the FPGA rewriting PC 121 via the data receiving unit 202.

The rewrite mode is information indicating that the FPGA is rewritten.
The rewritten printed board ID is information for identifying a printed board on which the FPGA is rewritten.
The rewrite data is, for example, FPGA configuration information.

The rewrite clock is a clock signal indicating timing at the time of FPGA rewriting.
The rewrite state signal is a signal indicating the rewrite state of the FPGA, for example, during rewrite or after rewrite.

The switching signal is a signal that is turned on when the FPGA is rewritten and turned off for video display.
The switching unit 207 includes a data conversion unit 601, a selector 602, a selector 603-p (p = 0 to 3), and a buffer 604.

  The data conversion unit 601 converts the rewrite mode and rewrite printed board ID respectively input from the FPGA rewrite PC 121 into continuous serial signals (hereinafter, rewrite mode + ID), and outputs them to the selector 602.

The selector 602 receives a rewrite mode + ID, a blank signal BLANK, and a vertical synchronization signal VSYNC. BLANK is generated by the setting switch 205, for example.
The selector 602 selects the rewrite mode + ID when VSYNC is off (blank period), selects BLANK when VSYNC is on (other than the blank period), and outputs it to the selector 603-0.

  The selector 603-0 receives the switching signal, the signal R, and the output signal of the selector 602. The selector 603-0 selects the output signal of the selector 602 when the switching signal is on, selects the signal R when the switching signal is off, and outputs the selected signal R to the video output unit 206.

  The selector 603-1 is supplied with the switching signal, the signal G, and the rewrite data. The selector 603-1 selects the rewrite data when the switching signal is on, selects the signal G when the switching signal is off, and outputs the selected signal G to the video output unit 206.

  The selector 603-2 receives the switching signal, the signal B, and the rewrite clock. The selector 603-2 selects the rewriting clock when the switching signal is on, selects the signal B when the switching signal is off, and outputs the selected signal B to the video output unit 206.

The selector 603-3 receives the switching signal, the video clock CLK, and the rewrite status signal. The selector 603-3 selects the rewrite state signal when the switching signal is on, selects the video clock CLK when the switching signal is off, and outputs it to the video output unit 206 as the signal CLK.
The vertical synchronization signal VSYNC is output to the video output unit 206 via the buffer 604.

FIG. 11 is a diagram illustrating a signal state when the video signal is output according to the second embodiment.
When the video signal is output, the signal R is a blank signal when VSYNC is off (blank period) and red video data when VSYNC is on.

When the video signal is output, the signal G is a blank signal when VSYNC is off and green video data when VSYNC is on.
When the video signal is output, the signal B is a blank signal when VSYNC is off and blue video data when VSYNC is on.
When the video signal is output, the signal CLK becomes a video clock.

FIG. 12 is a diagram illustrating signal states at the time of FPGA rewriting according to the second embodiment.
At the time of FPGA rewriting, the signal R becomes a rewriting mode + ID when VSYNC is off and a blank signal when VSYNC is on.

At the time of FPGA rewriting, the signal G becomes a blank signal when VSYNC is off and rewrite data when VSYNC is on.
When rewriting the FPGA, the signal B is a blank signal when VSYNC is off and a rewrite clock when VSYNC is on.
At the time of FPGA rewriting, the signal CLK becomes a blank signal when VSYNC is off and a rewrite state signal when VSYNC is on.

FIG. 13 is a configuration diagram of the switching unit of the printed board of the display board according to the second embodiment.
The switching unit 408 includes a mode determination unit 701, a selector 702, a write control unit 703, and a buffer 704.
The switching unit 408 corresponds to the switching unit 402 in FIG.
The vertical synchronization signal VSYNC is input to the FPGA 404 via the buffer 704.

The mode determination unit 701 receives signals R, G, B, CLK, and the vertical synchronization signal VSYNC. Hereinafter, the signals R, G, and B are collectively referred to as a signal RGB.
Further, the printed board setting ID is input from the setting switch 405 to the mode determination unit 701. The printed board setting ID is a number or symbol assigned to each printed board to identify the printed board.

  The mode determination unit 701 outputs the signals RGB and CLK to the selector 702 and the write control unit 703, the mode switching signal to the selector 702, and the rewrite permission signal to the write control unit 703, respectively.

The mode determination unit 701 checks the signal R when the vertical synchronization signal VSYNC is in the blank period.
When the signal R is a blank signal, since the input signal is video data, the mode switching signal and the rewrite permission signal are turned off.

  When the signal R is the rewrite mode + ID, the ID included in the rewrite mode + ID is compared with the printed board setting ID to check whether they match. When the ID included in the rewrite mode + ID of the signal R matches the printed board setting ID, the mode switching signal and the rewrite permission signal are turned on because the printed board is the target of rewriting. When the ID included in the rewrite mode + ID of the signal R and the printed board setting ID do not match, the mode switching signal is turned on and the rewrite permission signal is turned off.

  The selector 702 receives black display data from a switch (not shown). The black display data is data for displaying a black screen on the display board. In addition, the selector 702 receives the signals RGB, CLK, and the mode switching signal from the mode determination unit 701.

  The selector 702 selects black display data and outputs it to the FPGA 404 when the mode switching signal is on. As a result, when the FPGA is rewritten, the display panel is displayed in black. The selector 702 outputs the signals RGB and CLK (the signal RGB is video data because the mode switching signal is off) to the FPGA 404 when the mode switching signal is off.

When the rewrite permission signal is on, the write control unit 703 writes rewrite data (signal G) to the configuration memory 405 according to the rewrite clock (signal B).
The write controller 503 does not write to the configuration memory 405 when the rewrite permission signal is off.

  In the display system of the embodiment, the FPGA rewrite data is usually transmitted through the video signal line for transmitting the video data. Therefore, since the FPGA rewriting PC only needs to be connected to the image input printed board, there is no need to connect to the printed board one by one and repetitive rewriting, and the work can be performed in a short time. Even when the printed board is installed on the wall or high place of the building, the FPGA rewriting PC only needs to be connected to the printed board for video input, so rewriting is easy.

DESCRIPTION OF SYMBOLS 100 Display system 101 Print board for video input 111 Display board 112 Print board 121 PC for FPGA rewriting
DESCRIPTION OF SYMBOLS 201 Video input part 202 Data receiving part 203 Switching part 204 Video memory 205 Setting switch 206 Video output part 207 Switching part 301 Data conversion part 302, 303 Selector 304 Buffer 401 Receiving part 402 Switching part 403 Configuration memory 404 FPGA
405 Setting switch 406 Transmission driver 407 Display control output unit 408 switching unit

Claims (6)

An input / output device for inputting / outputting video data and rewrite data of setting information
A display device for receiving output data of the input / output device;
In a display system comprising:
The input / output device is
A first selection unit that outputs the video data or the rewrite data in response to a switching signal indicating presence or absence of the rewrite data;
The display device
A determination unit that determines whether an input signal from the input / output device is the video data or the rewrite data;
A second selection unit that outputs the input signal when the input signal is the video data and does not output the input signal when the input signal is rewrite data;
When the input signal is rewrite data, a write control unit for writing the rewrite data into a memory ,
The display device receives a vertical synchronization signal,
The determination unit, a display system based on the state of the input signal in the blanking period of the vertical synchronizing signal, the input signal is characterized that you determine whether the rewrite data or the video data.   The display system according to claim 1, wherein predetermined video data is input to the second selection unit, and the predetermined video data is output when the input signal is rewrite data. In the video data and the rewrite data setting information is input, to connect the display device to write the displaying and the rewrite data the video data to the memory input-output device,
In accordance with a switching signal indicating the presence / absence of the rewrite data, a selection unit that outputs the video data or the rewrite data as an output signal to the display device ,
A vertical synchronization signal is input to the input / output device,
The input / output device , wherein the selection unit outputs a signal indicating whether the output signal is rewrite data or video data to the display device as the output signal during a blank period of the vertical synchronization signal . A vertical synchronization signal is input to the input / output device,
The selection unit, according to claim 3 Symbol placement of the input and output device and outputs a signal including an ID indicating the rewritten during the blank period of the vertical synchronizing signal. A determination unit for determining whether the input signal is video data or rewrite data;
When the input signal is the video data, the input signal is output, and when the input signal is rewrite data, the selection unit that does not output the input signal;
When the input signal is rewrite data, a write control unit that writes the rewrite data to a memory, and
The display device receives a vertical synchronization signal,
The display device according to claim 1, wherein the determination unit determines whether the input signal is video data or rewrite data based on a state of the input signal in a blank period of the vertical synchronization signal. The display device has identification information unique to the display device,
The determination unit compares the identification information with rewrite target information indicating a rewrite target included in the input signal in a blank period of the vertical synchronization signal,
The display device according to claim 5 , wherein the write control unit writes the rewrite data into the memory when the identification information matches the rewrite target information.

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