JP5367325B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a double gate formed by self-alignment.

  A MOSFET (Metal-Oxide-Field-Effect Transistor) having a double-gate structure in which two gates are formed using an SOI (Silicon On Insulator) substrate has an extremely thin channel to increase carrier mobility. Therefore, it is expected to be a next-generation transistor.

  In a conventional SOI-MOSFET having a double gate structure, a bottom gate is formed on an SOI substrate, and an Si gate and an upper gate are sequentially formed on the bottom gate (for example, see Non-Patent Document 1 and Non-Patent Document 2). .

S. Y. Lee, “VLSI Symp 2004”, p200 R. Wacqez, “SSDM 2006”, p-3-18

  A conventional SOI-MOSFET having a double gate structure causes the bottom gate and the upper gate to shift laterally due to the performance of the exposure apparatus, film stress and thermal distortion during the manufacturing process, and the bottom gate and It was difficult to form the upper gate with high positional accuracy. For this reason, the electric field generated by the two gates is applied to different channel regions, so that the desired performance cannot be exhibited. Conventionally, a double gate is formed with a large pattern.

  The present invention has been made to solve these problems, and it is an object of the present invention to provide a method for manufacturing a semiconductor device capable of forming a bottom gate electrode and an upper gate electrode with fine positional accuracy. To do.

In order to solve the above problems, a method of manufacturing a semiconductor device according to an embodiment of the present invention includes: (a) a step of forming a first protective film on an SOI (Silicon On Insulator) substrate; and (b) step. After (a), a step of forming a groove by etching from the surface of the first protective film to a predetermined position of the oxide film of the SOI substrate; (c) after step (b), at least the bottom surface of the groove; A step of forming a second protective film so as to cover the side surface; a step of (d) forming a first gate electrode on the bottom surface of the trench after step (c); and (e) a step of (d). Thereafter, a step of removing the second protective film formed on the side surface of the groove not covered with the first gate electrode, and leaving damage only on the first gate electrode at that time, and a step (e) (e) ) And then epitaxially grown from the silicon layer of the SOI substrate Forming a first gate oxide film on the first gate electrode on using silicon, (g) after step (f), the silicon on the first gate oxide film A is in the groove, the And a step of sequentially forming a second gate oxide film and a second gate electrode.

In one embodiment of the present invention, a pad oxide film and a SiN film are sequentially formed on Si, and a groove is formed by etching from the surface of the SiN film to a predetermined position of SiO ₂ of the SOI substrate. A protective film is formed so as to cover the bottom and side surfaces, a bottom gate electrode is formed on the bottom surface of the groove, and a protective film formed on the side surface of the groove that is not covered by the bottom gate electrode is removed. A bottom gate oxide film is formed on the bottom gate electrode using Si epitaxially grown from Si of the SOI substrate, leaving damage only on the electrode, and Si and upper gate oxide are formed on the bottom gate oxide film in the trench. film, in order to form the Upper gate electrode in this order, Bottom gate and Upper gate in minute dimensions It is possible to position accurately formed.

  Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a configuration diagram of an SOI-MOSFET according to an embodiment of the present invention. The SOI-MOSFET shown in FIG. 1 includes a bottom gate electrode 3 (on a SiO substrate ₂ made of a Si substrate 1, a buried oxide (BOX) oxide SiO ₂ 2, and a Si 5 (silicon layer). A first gate electrode) is formed, and a bottom gate oxide film 4 (first gate oxide film) is formed on the bottom gate electrode 3. An upper gate oxide film 6 (second gate oxide film) is formed to face the bottom gate oxide film 4 with Si5 (silicon) interposed therebetween, and an upper gate electrode 7 (second gate electrode) is formed on the upper gate oxide film 6. ) Is formed.

  As shown in FIG. 1, the present embodiment is characterized in that the bottom gate electrode and the upper gate electrode are formed with high positional accuracy. Hereinafter, the SOI-MOSFET in the present embodiment will be described in detail with reference to the manufacturing process diagrams shown in FIGS.

In FIG. 2, a pad oxide film 8, a SiN film 9 (first protective film) are sequentially formed on an SOI substrate made of Si substrate 1, SiO ₂ 2 and Si5. The SiN film 9 is used as a hard mask. After the formation of the SiN film 9, a trench groove (groove) is formed by etching to a predetermined position of SiO ₂ 2 using the resist 10 as a mask.

  Next, as shown in FIG. 3, a protective film 11 (second protective film) is thinly deposited so as to cover at least the bottom and side surfaces of the trench groove. In this embodiment, SiN is used as the protective film 11, but LP (Low Pressure) -TEOS (normal tetraethyl silicate) may be used. By forming the protective film 11, Si 3 that forms a channel later. Protects the exposure.

  After the formation of the protective film 11, a bottom gate electrode 3 is deposited as shown in FIG. In this embodiment, Poly-Si (polysilicon) is used as the bottom gate electrode 3 and the upper gate electrode 7, but any gate electrode material may be used.

In FIG. 5, the bottom gate electrode 3 is flattened on the surface of the protective film 11 using the SiN film 9 as a stopper by CMP (Chemical Mechanical Polishing) processing on the deposited bottom gate electrode 3, and the bottom gate electrode 3 is made to be SiO 2. _2. Etching is performed to near the interface between 2 and Si5. The bottom gate electrode 3 is etched to a desired position by wet etching with high temperature AMP (ammonia-hydrogen peroxide solution) that selectively etches only Si after etching by dry etching to some extent.

  Through the above steps, the bottom gate electrode 3 is formed on the bottom surface of the trench groove.

  After the formation of the bottom gate electrode 3, as shown in FIG. 6, the protective film 10 is etched back by dry etching and removed. During dry etching, damage is formed on the A surface of the bottom gate electrode 3. Thereafter, the protective film 11 remaining on the side surface of Si5 is removed by hot phosphoric acid. At this time, damage is further applied to the damage formed on the A surface of the Bottom gate electrode 3, and damage is also formed on the B surface of Si5.

  The damage on the B surface of Si5 formed when the protective film 10 is removed is removed by CDE (Chemical Dry Etching), but the damage on the A surface of the Bottom gate electrode 3 cannot be completely removed and remains. That is, the protective film 11 formed on the side surface of the trench groove that is not covered by the Bottom gate electrode 3 is removed, and at this time, damage is left only on the Bottom gate electrode 3.

  As a method different from the method for removing the protective film 10, the protective film 10 is etched back by dry etching until Si5 is exposed, as shown in FIGS. 7A and 7B. During dry etching, damage is formed on the A surface of the bottom gate electrode 3. Next, the damage on the A surface of the Bottom gate electrode 3 and the damage formed on the B surface of Si5 are removed by wet etching with high temperature APM. After that, damage is formed on the A surface of the Bottom gate electrode 3 by anisotropic plasma treatment or Si implantation using a gas system that does not etch Si5. At this time, the B surface of Si5 is not etched.

  After the removal of the protective film 10 by the above two methods, no damage is formed on the B surface of Si5, and damage is formed only on the A surface of the bottom gate electrode 3. Therefore, as shown in FIG. 8, Si can be selectively epitaxially grown from the B surface using Si5 as a seed. That is, Si is epitaxially grown on the bottom gate electrode 3 from Si5. At this time, Si does not grow epitaxially from the bottom gate electrode 3.

  In FIG. 7, when the protective film 10 is made of TEOS, the protective film 10 is removed by wet etching with HF (hydrofluoric acid). Since wet etching with HF causes little damage to the A surface of the Bottom gate electrode 3 and the B surface of Si5, damage is formed on the A surface of the Bottom gate electrode 3 by anisotropic plasma treatment or implantation of Si or the like. There is a need.

  As shown in FIG. 9, recess etching by dry etching is performed on a channel formation portion of Si5 selectively epitaxially grown from Si5. By this recess etching, Si5 is adjusted to a desired film thickness, but may be omitted if unnecessary.

  Next, as shown in FIG. 10, all Si5 adjusted to a desired film thickness is oxidized. Thereafter, as shown in FIG. 11, the oxidized Si5 is isotropically etched by dry etching and wet etching with HF, and the film thickness is adjusted to a desired gate oxide film thickness (Tox). Then, a Bottom gate oxide film 4 is formed. At this time, no oxide film remains on the exposed portion of Si5.

  As another method for forming the Bottom gate oxide film 4, in the case of recess etching as shown in FIG. 9, after etching to the vicinity of a desired gate oxide film thickness, oxidation is performed, followed by wet etching with HF. A bottom gate oxide film 4 having a thickness may be formed.

  Thus, since the Bottom gate oxide film 4 is formed by oxidizing Si epitaxially grown using Si5 as a seed, it is higher than the oxide film formed by oxidizing Poly-Si epitaxially grown from the Bottom gate electrode 3. Reliability can be expected. That is, the bottom gate oxide film 4 is formed on the bottom gate electrode 3 using Si5 epitaxially grown from the silicon layer of the SOI substrate.

  After the bottom gate oxide film 4 is formed, Si is selectively epitaxially grown using Si5 as a seed to form a channel, as shown in FIG. At this time, facets (crystal defects) are formed at the boundary portion of Si selectively epitaxially grown from the source side and the drain side of Si5.

  Next, as shown in FIG. 13, an extremely thin channel layer is formed by recess etching. The film thickness is about 2/3 of the gate length. Thereafter, channel implantation is performed as necessary. The activation annealing after channel implantation improves the facet formed at the aforementioned Si boundary portion. Then, as shown in FIG. 14, the upper gate oxide film 6 is formed by oxidizing the surface of the channel.

  After the upper gate oxide film 6 is formed, an upper gate electrode 7 is deposited as shown in FIG. The upper gate electrode 7 used in this embodiment is polysilicon. After the deposition, as shown in FIG. 16, the upper gate electrode 7 is flattened on the surface of the SiN film 9 by CMP using the SiN film 9 as a stopper. In this way, Si 5, Upper gate oxide film 4, and Upper gate electrode 7 are sequentially formed on the Bottom gate oxide film 4.

  Next, the SiN film 9 and the pad oxide film 8 are removed in the order of hot phosphoric acid and HF, and the upper gate electrode 7 is exposed as shown in FIG. At this time, the dimension of the upper gate electrode 7 can be adjusted by adjusting the film thickness of the SiN film 9. Then, as shown in FIG. 18, the upper gate electrode 7 is sacrificial oxidized, the oxide film is removed by wet etching using HF, and the width of the upper gate electrode 7 is made equal to the width of the bottom gate electrode 3. adjust.

  The structure shown in FIG. 17 is more effective than the conventional structure, but the structure shown in FIG. 18 provides a further effect.

  From the above, since the bottom gate electrode 3 and the upper gate electrode 7 are formed using the same groove, there is an effect of self-alignment, and the positions of both gate electrodes are formed with fine positional accuracy and without positional deviation. It is possible to form an SOI-MOSFET having a double gate structure.

  INDUSTRIAL APPLICABILITY The present invention can be used for high-speed and low-consumption applications in general IC (Integrated Circuit) and LSI (Large Scale Integration) products using CMOS (Complementary Metal Oxide Semiconductor) transistors.

It is a block diagram of SOI-MOSFET by embodiment of this invention. It is a manufacturing process diagram of SOI-MOSFET according to an embodiment of the present invention. It is a manufacturing process diagram of SOI-MOSFET according to an embodiment of the present invention. It is a manufacturing process diagram of SOI-MOSFET according to an embodiment of the present invention. It is a manufacturing process diagram of SOI-MOSFET according to an embodiment of the present invention. It is a manufacturing process diagram of SOI-MOSFET according to an embodiment of the present invention. It is a manufacturing process diagram of SOI-MOSFET according to an embodiment of the present invention. It is a manufacturing process diagram of SOI-MOSFET according to an embodiment of the present invention. It is a manufacturing process diagram of SOI-MOSFET according to an embodiment of the present invention. It is a manufacturing process diagram of SOI-MOSFET according to an embodiment of the present invention. It is a manufacturing process diagram of SOI-MOSFET according to an embodiment of the present invention. It is a manufacturing process diagram of SOI-MOSFET according to an embodiment of the present invention. It is a manufacturing process diagram of SOI-MOSFET according to an embodiment of the present invention. It is a manufacturing process diagram of SOI-MOSFET according to an embodiment of the present invention. It is a manufacturing process diagram of SOI-MOSFET according to an embodiment of the present invention. It is a manufacturing process diagram of SOI-MOSFET according to an embodiment of the present invention. It is a manufacturing process diagram of SOI-MOSFET according to an embodiment of the present invention. It is a manufacturing process diagram of SOI-MOSFET according to an embodiment of the present invention.

Explanation of symbols

1 Si substrate, 2 SiO ₂ , 3 Bottom gate electrode, 4 Bottom gate oxide film, 5 Si, 6 Upper gate oxide film, 7 Upper gate electrode, 8 Pad oxide film, 9 SiN film, 10 resist, 11 protective film.

Claims (7)

(A) forming a first protective film on an SOI (Silicon On Insulator) substrate;
(B) after the step (a), forming a groove by etching from the surface of the first protective film to a predetermined position of the oxide film of the SOI substrate;
(C) after the step (b), forming a second protective film so as to cover at least the bottom and side surfaces of the groove;
(D) after the step (c), forming a first gate electrode on the bottom surface of the trench;
(E) After the step (d), the second protective film formed on the side surface of the groove that is not covered with the first gate electrode is removed, and at that time, on the first gate electrode Only the process of leaving damage,
(F) after the step (e), forming a first gate oxide film on the first gate electrode using silicon epitaxially grown from the silicon layer of the SOI substrate;
(G) after the step (f), the silicon on the first gate oxide film A is within the groove, the second gate oxide film, forming a second gate electrode in this order,
A method for manufacturing a semiconductor device. The step (e)
(E-1) The semiconductor device according to claim 1, further comprising a step of removing damage to the silicon layer of the SOI substrate formed at the time of removing the second protective film by a CDE (chemical dry etching) process. Production method. The step (e)
(E-2) removing the damage on the silicon layer of the SOI substrate and the first gate electrode formed after the removal of the protective film by a high temperature APM (ammonia-hydrogen peroxide solution) treatment;
(E-3) forming damage only on the first gate electrode;
A method for manufacturing a semiconductor device according to claim 1, comprising: The step (f)
(F-1) After the step (e), a step of epitaxially growing silicon on the first gate electrode from a silicon layer of the SOI substrate;
(F-2) a step of oxidizing the silicon after the step (f-1);
(F-3) After the step (f-2), etching the oxidized silicon to a predetermined thickness;
The method for manufacturing a semiconductor device according to claim 1, comprising: The step (f)
(F-4) After the step (e), a step of epitaxially growing silicon on the first gate electrode from a silicon layer of the SOI substrate;
(F-5) After the step (f-4), etching the silicon to a predetermined thickness;
(F-6) After the step (f-5), a step of oxidizing the silicon;
The method for manufacturing a semiconductor device according to claim 1, comprising: 6. The method of manufacturing a semiconductor device according to claim 1, wherein the first gate electrode and the second gate electrode are polysilicon. 6. The method of manufacturing a semiconductor device according to claim 1, wherein the first protective film is formed by stacking a pad oxide film and a nitride film.

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