JP5371052B2 - High frequency power supply - Google Patents

Description

  The present invention relates to a high frequency power supply device that generates high frequency power to be supplied to a load such as a plasma processing apparatus.

  In order to supply electric power to a load such as a plasma processing apparatus that performs microfabrication on a semiconductor, a high frequency power supply apparatus is used. FIG. 5 shows a basic configuration of a high-frequency power supply apparatus. In FIG. 5, 1 is a high-frequency generator that generates a high-frequency signal, 2 is a power amplifier that amplifies a high-frequency signal obtained from the high-frequency generator 1, Reference numeral 3 denotes a high-frequency detection unit that demultiplexes a part of the output of the power amplification unit and outputs a traveling wave detection signal including traveling wave power information. 4 is a filter for removing unnecessary frequency components from the traveling wave detection signal obtained from the high frequency detection unit, 5 is a level detection unit for detecting the output of the filter 4 to detect the level of the traveling wave detection signal, and 6 is a level detection unit. The comparison of the level of the traveling wave detection signal detected by the unit 4 and the set level set by the level setting unit 7 is performed, and the traveling wave power output from the power amplification unit 2 is calculated based on the calculation result. It is a level control unit that controls the output level of the high frequency generator 1 so as to keep the set value.

  In this high frequency power supply device, the high frequency generation unit 3, the level detection unit 5, the level setting unit 7, and the level control unit 6 maintain the traveling wave power applied from the power amplification unit 2 to the load at a set value so as to maintain the set value. A control unit that performs ALC control (Auto Level Control) for controlling the output level of 1 is configured. This type of power supply device is disclosed in Patent Documents 1 to 3, for example.

  In this type of high-frequency power supply device, it is required that the high-frequency power has high purity (does not contain unnecessary frequency components). Therefore, various high frequency filters are arranged in each stage from the high frequency generator 1 to the output stage of the power amplifier 2 to remove unnecessary frequency components (spurious components) generated in the power amplifier. On the output side of the power amplifying unit 2, a low-pass filter is provided for removing harmonic components from the power supplied from the amplifying unit to the load. Further, an impedance matching device is provided between the output of the high-frequency power supply device and the load, and impedance matching is performed with respect to the load in a steady state, thereby preventing reflected wave power from being generated in the load. Therefore, when the load is in a steady state, the level of traveling wave power given from the power amplifier 2 to the load is kept stable, and the reflected wave power reflected by the load and returning to the high frequency power amplifier is minimum. .

  However, when starting up a load such as a plasma processing apparatus, the impedance of the load is in a non-linear state and fluctuates at a high speed. Therefore, the matching operation of the matching device cannot catch up, causing a mismatch state and reflecting the load as a node. A wave is generated. Further, inside the load, various new frequency components are generated as spurious components due to the frequency mixing effect caused by the nonlinearity, and these spurious components are superimposed on the reflected wave. The reflected wave power on which the spurious component is superimposed flows backward in the matching device, and the component (mainly the fundamental frequency component) that can pass through the low-pass filter provided on the output side of the high-frequency power amplifier is the power amplification. Return to the output stage. In this case, the power (load side power) given from the power amplification unit to the load is the power obtained by subtracting the reflected wave power from the traveling wave power detected on the output side of the power amplification unit.

  In the plasma processing apparatus, as shown in FIG. 6, two types of high frequency powers having different output frequencies may be simultaneously applied from two high frequency power supply apparatuses to the electrodes of the plasma generation apparatus. In FIG. 6, 11 is a first high-frequency power supply device, and 12 is a second high-frequency power supply device that outputs high-frequency power having a frequency lower than the output frequency of the first high-frequency power supply device. Outputs of the first high-frequency power supply device 11 and the second high-frequency power supply device 12 are supplied to a load 15 such as a plasma processing apparatus through a first matching device 13 and a second matching device 14, respectively.

  The high-frequency power given from the first high-frequency power supply device 11 to the load 5 is high-frequency power for plasma generation, and the high-frequency power given from the second high-frequency power supply device 12 to the load 15 draws ions in the plasma. This is high frequency power for bias. Usually, the frequency of the high frequency power for plasma generation has a high frequency of about several tens of MHz to several tens of MHz, and the frequency of the high frequency power for bias has a relatively low frequency of about several hundred KHz to several MHz. Yes.

  In such a system, since the impedance of the load changes in a complicated manner, impedance matching cannot be completely achieved by the impedance matching unit, and generation of a reflected wave in the load cannot be avoided. In this case, the reflected wave returning from the load to the amplification unit side of the first high-frequency power supply device 11 includes the fundamental frequency component of the second high-frequency power supply device 12 and the spurious frequency component in the vicinity thereof. Since the fundamental frequency of the second high-frequency power supply device 12 is lower than the fundamental frequency of the first high-frequency power supply device 11, the spurious component in the reflected wave from the load 15 toward the first high-frequency power supply device 11 is the first. Passes through the low-pass filter provided on the output side of the high frequency power supply device 11 and reaches the amplifying unit of the first high frequency power supply device. In addition, since the spurious component reaching the power amplification unit of the first high frequency power supply device 11 from the second high frequency power supply device 12 and the output of the first high frequency power supply device 11 are mixed, the first high frequency power supply device 11 Spurious components are also included in the traveling wave power toward the load.

  As an example, when the output frequency of the first high frequency power supply device 1 for generating plasma is 50 MHz and the output frequency of the second high frequency power supply device 2 for biasing is 2 MHz, the first high frequency power supply device 1 supplies a load. FIG. 7 and FIG. 8 schematically show the frequency spectrum in the vicinity of the fundamental frequency component (50 MHz) of the traveling wave power and the frequency spectrum in the vicinity of the fundamental frequency component (50 MHz) of the reflected wave power, respectively. In FIG. 8, the scale of the vertical axis is the same as the scale of the vertical axis of FIG. 7 for the sake of convenience, but the level of the reflected wave power is actually lower than the level of the traveling wave power.

  As described above, when the reflected wave power with the spurious component superimposed on the output side of the power amplifying unit 2 returns, the detection signal obtained from the high frequency detecting unit 3 also includes the spurious component. If a spurious component is included in the detection signal, the level detection unit cannot accurately detect the level of the traveling wave detection signal, and the ALC control of the output of the high frequency generator 1 cannot be performed accurately. For this reason, it is necessary to insert the filter 4 before the level detection unit 5 to remove spurious components from the signal input to the level detection unit 5.

  In general, the term “spurious” is often used to mean an unnecessary frequency that appears before and after the fundamental frequency and an unnecessary frequency that appears before and after each harmonic frequency. However, in this specification, for convenience of explanation. All of the unnecessary frequency components (usually components other than the fundamental frequency component) that are unnecessary as frequency components supplied to the load are called spurious components.

  As described above, if a spurious component is included in the detection signal, the level detection unit 5 cannot accurately detect the level of the traveling wave detection signal, and the ALC control of the output of the high frequency generation unit 1 can be performed accurately. I can't do it. In such a case, the spurious component may be removed by, for example, frequency conversion filtering as disclosed in Patent Document 4. Note that Patent Document 4 discloses a method for removing spurious noise from reflected wave power, but this may be applied to traveling wave power.

FIG. 9 is a configuration example of a conventional high-frequency power supply device that removes spurious components of traveling wave power by frequency conversion filtering.
The high frequency power supply device shown in FIG. 9 includes a first high frequency generator 21, a power amplifier 22, a high frequency detector 23, a second high frequency generator 24, a multiplier 25, a filter 26, and a difference frequency signal level detector 27. , A level setting unit 28, a level control unit 29, and crystal oscillators 31, 32, and 33.

  The crystal oscillator includes a crystal resonator inside, and is configured to perform frequency multiplication or frequency division, for example, in order to obtain a desired output frequency. In the first high-frequency generator 21 and the second high-frequency generator 24, the output signal of this crystal oscillator is used as a reference clock signal. In this example, the frequency of the reference clock signal output from the crystal oscillator 31 is 50 MHz, and the frequency of the reference clock signal output from the crystal oscillator 32 is 49.5 MHz.

  The first high frequency generator 21 is configured to amplify and output the reference clock signal output from the crystal oscillator 31. The output frequency of the first high frequency generator 21 is 50 MHz. The second high frequency generator 24 is configured to amplify and output the reference clock signal output from the crystal oscillator 32. The output frequency of the second high frequency generator 24 is 49.5 MHz.

  The high frequency signal (50 MHz) output from the first high frequency generation unit 21 is amplified by the power amplification unit 22, and the traveling wave detection signal including the traveling wave power information is detected by the high frequency detection unit 23. The traveling wave detection signal and the high frequency signal (49.5 MHz) output from the second high frequency generation unit 24 are input to the multiplication unit 25. That is, the output frequency of the first high frequency generator 21 and the output frequency of the second high frequency generator 24 have a difference frequency of 0.5 MHz.

  As is well known, when two signals are multiplied by the multiplication unit, a signal including not only the frequency component of the frequency difference between the two signals but also the frequency component of the sum of the frequencies of the two signals is obtained. For example, in the system shown in FIG. 6, the case where the basic frequency of the first high-frequency power supply device 11 (the frequency f1 of the first high-frequency signal S1) is 50 MHz and the basic frequency of the second high-frequency power supply device 12 is 2 MHz. Then, components such as 46, 48, 52, and 54 MHz as spurious components flow into the vicinity of the fundamental frequency of 50 MHz through the output transmission system to the output terminal of the high frequency power supply device 11. In this case, the output frequency of the second high frequency generator 24 (frequency f2 of the second high frequency signal S2) is set to 49.5 MHz, the difference frequency from the basic frequency 50 MHz is 0.5 MHz, and the sum frequency is 99.5 MHz. Similarly, the difference frequencies for the above spurious components are 3.5, 1.5, 2.5, and 4.5 MHz, and the sum frequencies are 95.5, 97.5, 101.5, and 103.5 MHz.

  Therefore, if a filter 26 that passes a component having a difference frequency of 0.5 MHz with respect to the fundamental frequency and removes a frequency component that is equal to or higher than the difference frequency of the spurious component (for example, a filter having a characteristic with a cutoff frequency of 1 MHz) is used. The component of frequency 0.5MHz can be extracted with high accuracy.

  Thereafter, the level of the signal extracted by the filter 26 is detected by the difference frequency signal level detection unit 27. The level control unit 29 compares the detected level with the set level set by the level setting unit 28, and gives an amplitude command to the first high frequency generator 21 so that the detected level approaches the set level. It is done.

  That is, since the spurious component can be removed by frequency conversion filtering, it is possible to improve the problem that the output ALC control, which is caused by the spurious component being included in the detection signal, cannot be performed accurately. .

JP-A-5-63627 JP-A-6-6144 Japanese Patent Laid-Open No. 11-233294 JP 2008-276966 A

  In the above configuration, the filter 26, the difference frequency level detection unit 27, the first level control unit 29, and the like can be configured by digital circuits. The digital circuit can be easily configured by using a gate array such as an FPGA (Field Programmable Gate Array) that can appropriately define and change an internal logic circuit. In this case, a digital clock (for example, FPGA) is also supplied with a reference clock signal (for example, a signal of 100 MHz) from the external crystal oscillator 33, and the digital circuit performs various processes using the frequency of the reference clock signal as a reference clock. In many cases, the frequency of the reference clock signal is the sampling frequency in the digital circuit.

  However, the output frequency of the crystal oscillator has individual errors due to variations in parts, changes in voltage, temperature, and the like. For this reason, as described above, if individual crystal oscillators are used for each high-frequency generator and the digital circuit that performs signal processing, an error occurs in the signal processing result in the digital circuit.

  That is, in the digital circuit, since the input signal is normalized by “input frequency / sampling frequency”, if the errors occurring in “input frequency” and “sampling frequency” are not in the same ratio, “input” with / without error The value of “frequency / sampling frequency” is different. As a result, an error occurs in the signal processing result in the digital circuit. In the present specification, a numerical value represented by “input frequency / sampling frequency” is referred to as “normalized frequency”.

  For example, the output frequency of the crystal oscillator 31 has an error of α times (α = 1.01 when the error is + 1%), and the output frequency of the crystal oscillator 32 has an error of β times (an error of + 1%). , Β = 1.01), and the output frequency of the crystal oscillator 33 has a γ-fold error (γ = 1.01 when the error is + 1%).

  In this case, the output frequency of the first high frequency generator includes the same error as the error of the output frequency of the crystal oscillator 31, and thus is 50 × α MHz. Similarly, the output frequency of the second high frequency generator includes 49.5 × β MHz because the same error as the output frequency error of the crystal oscillator 32 is included. Therefore, the difference frequency passing through the multiplier 25 is 50 × α−49.5 × β [MHz]. This frequency becomes the input frequency of the filter 26.

  Further, since the frequency of the reference clock signal for the digital circuit is 100 × γ MHz, the sampling frequency of the digital circuit is also 100 × γ MHz.

  If the filter 26 is configured as a digital filter (digital circuit), the filter 26 performs signal processing at a sampling frequency of 100 × γ MHz. Therefore, the normalized frequency is “input frequency / sampling frequency” = (50 × α−49.5 × β) / 100 × γ.

  On the other hand, when there is no error in the output frequency of each crystal oscillator, α = β = γ = 1, so the normalized frequency is 0.005. That is, if an error occurs in the output frequency of each crystal oscillator, the normalized frequency becomes a value deviating from 0.005.

  Therefore, for example, if the filter 26 is a band-pass filter having a very narrow filter pass frequency band, the signal level is not attenuated (or hardly attenuated) when the normalized frequency is 0.005. Designed to pass through a bandpass filter. In this case, the signal level is greatly attenuated by merely shifting the normalized frequency slightly from 0.005.

  The difference frequency level detection unit 27 detects the level of the output signal of the difference frequency signal output from the filter 26. The difference frequency level detection unit 27 also detects a signal normalized by “input frequency / sampling frequency”. It is processed. For this reason, as in the case where the filter 26 is configured as a digital filter (digital circuit), there arises a problem due to the deviation of the normalized frequency.

Moreover, as described above, the output frequency of the crystal oscillator has individual errors due to variations in parts, changes in voltage, temperature, etc., so the above α, β, γ are not constant, It depends on the individual crystal oscillator. That is, not only does an error occur in the signal processing result (calculation result) in the digital circuit, but also the error varies, and calibration is difficult.
As a result, since the detection accuracy of the traveling wave power detection signal is lowered, the traveling wave power control accuracy is lowered.

  Although not shown, when the reflected wave power is detected, a multiplication unit or the like may be provided in the same manner as the traveling wave power and detected by frequency conversion type filtering. However, as in the case of traveling wave power, a problem due to an error in the output frequency of the crystal oscillator occurs.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a high frequency power supply apparatus that can perform power control with high accuracy even if there is an error in the output frequency of a crystal oscillator that generates a reference clock.

The high frequency power supply device provided by the first invention is
A reference clock generation unit that generates a plurality of reference clock signals using a single crystal oscillator;
The reference clock signal generated by the reference clock generation unit is used to generate a high-frequency signal having an output frequency commanded by a frequency command and an output amplitude level commanded by an amplitude level command. First and second high frequency generators for generating different first high frequency signals and second high frequency signals, respectively;
A frequency command unit that gives the frequency command to the first and second high frequency generation units so as to keep a difference between the frequency of the first high frequency signal and the frequency of the second high frequency signal constant;
A power amplifier for amplifying the first high-frequency signal;
A high frequency detection unit for detecting a traveling wave detection signal including information on traveling wave power from the power amplification unit toward the load;
Multiplying the traveling wave detection signal obtained by the high-frequency detection unit and the second high-frequency signal includes a frequency component of a difference between the frequency of the first high-frequency signal and the frequency of the second high-frequency signal. A multiplier for obtaining a signal;
A filter that extracts a difference frequency signal having a frequency component of a difference between the frequency of the first high-frequency signal and the frequency of the second high-frequency signal from the output of the multiplier;
A difference frequency signal level detection unit for detecting a level of the difference frequency signal extracted by the filter;
The first high-frequency generation is performed so that the level detected by the difference frequency signal level detection unit is compared with a set level and the traveling wave power from the power amplification unit to the load is maintained at a set value based on the calculation result. A level control unit for giving the amplitude level command to the unit;
It is characterized by having.

The high frequency power supply device provided by the second invention is
An output level detector for detecting an output level of the second high frequency generator;
The level detected by the output level detection unit is compared with a second set level, and the second high frequency generation unit is maintained at a set constant value based on the calculation result. A second level control unit for giving an amplitude command to the high frequency generation unit of
Is further provided.

The high frequency power supply device provided by the third invention is
In the first and second aspects of the invention, at least one of the filter and the difference frequency signal level detection unit is configured by a digital circuit.

The high frequency power supply device provided by the fourth invention is
A reference clock generation unit that generates a plurality of reference clock signals using a single crystal oscillator;
The reference clock signal generated by the reference clock generation unit is used to generate a high-frequency signal having an output frequency commanded by a frequency command and an output amplitude level commanded by an amplitude level command. First and second high frequency generators for generating different first high frequency signals and second high frequency signals, respectively;
A frequency command unit that gives the frequency command to the first and second high frequency generation units so as to keep a difference between the frequency of the first high frequency signal and the frequency of the second high frequency signal constant;
A power amplifier for amplifying the first high-frequency signal;
A high frequency detection unit for detecting a traveling wave detection signal including information on traveling wave power from the power amplification unit toward the load and a reflected wave detection signal including information on reflected wave power from the load side toward the power amplification unit;
Multiplying the traveling wave detection signal obtained by the high-frequency detection unit and the second high-frequency signal includes a frequency component of a difference between the frequency of the first high-frequency signal and the frequency of the second high-frequency signal. A first multiplier for obtaining a signal;
A first filter for extracting a first difference frequency signal having a frequency component of a difference between the frequency of the first high frequency signal and the frequency of the second high frequency signal from the output of the first multiplication unit;
A first difference frequency signal level detection unit for detecting a level of the first difference frequency signal extracted by the first filter;
Multiplication of the reflected wave detection signal obtained by the high-frequency detection unit and the second high-frequency signal includes a frequency component of a difference between the frequency of the first high-frequency signal and the frequency of the second high-frequency signal. A second multiplier for obtaining a signal;
A second filter for extracting a second difference frequency signal having a frequency component of a difference between the frequency of the first high frequency signal and the frequency of the second high frequency signal from the output of the second multiplication unit;
A second difference frequency level detection unit for detecting a level of the second difference frequency signal extracted by the second filter;
A level obtained by subtracting the level detected by the second difference frequency signal level detection unit from the level detected by the first difference frequency signal level detection unit is compared with a set level, and based on the calculation result, A level control unit that gives the amplitude command to the first high-frequency generation unit so as to keep the power supplied from the power amplification unit to the load at a set value;
It is characterized by having.

The high frequency power supply device provided by the fifth invention provides:
The level detected by the output level detection unit is compared with a second set level, and the second high frequency generation unit is maintained at a set constant value based on the calculation result. A second level control unit for giving an amplitude command to the high frequency generation unit of
Is further provided.

The high frequency power supply device provided by the sixth invention provides:
In the fourth and fifth inventions, at least one of the first filter, the first difference frequency signal level detection unit, the second filter, and the second difference frequency signal level detection unit is a digital circuit. It is characterized by being composed.

The high frequency power supply device provided by the seventh invention provides
In the first to sixth inventions, the first and second high-frequency generators are DDS (Direct Digital Synthesizer) type high-frequency generators.

  According to the present invention, when spurious components are removed by frequency conversion filtering, not only the fundamental frequency components can be accurately extracted, but also problems caused by errors in the output frequency of the crystal oscillator can be improved. As a result, it is possible to provide a high-frequency power supply device that can perform accurate power control even if there is an error in the output frequency of the crystal oscillator that generates the reference clock.

It is the block diagram which showed the structure of the 1st Embodiment of this invention. It is the block diagram which showed the structure of the 2nd Embodiment of this invention. 3 is a block diagram illustrating a configuration example of a filter 109. FIG. It is a figure which shows an example of the frequency characteristic of a digital band pass filter. It is the block diagram which showed the structure of the conventional high frequency power supply device. It is the block diagram which showed the structure of the system which supplies electric power from two high frequency power supply devices from which output frequency differs to loads, such as a plasma processing apparatus. 7 is a frequency spectrum showing an example of a frequency distribution of traveling wave power detected on the output side of the power amplifier in the system shown in FIG. 6. 7 is a frequency spectrum showing an example of a frequency distribution of reflected wave power detected on the output side of the power amplifier in the system shown in FIG. 6. It is an example of a structure of the conventional high frequency power supply device which removes the spurious component of traveling wave electric power by filtering of a frequency conversion system.

[First Embodiment]
Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 shows a configuration of a first embodiment of a high-frequency power supply device according to the present invention. In the figure, reference numeral 101 denotes a first high frequency signal S1 that generates a first high frequency signal S1 having an output frequency commanded by a first frequency command Cf1 and an output amplitude level commanded by a first amplitude level command Ca1. A generating unit 102 generates a second high frequency signal S2 having an output frequency commanded by the second frequency command Cf2 and an output amplitude level commanded by the second amplitude level command Ca2. It is. In the present embodiment, the first high-frequency generator 101 and the second high-frequency generator 102 are configured by a known DDS (Direct Digital Synthesizer).

  Further, the first high frequency generator 101 and the second high frequency generator 102 use the reference clock signal output from the reference clock signal generator described later to generate the first high frequency signal S1 and the second high frequency signal S2. generate.

If the first high-frequency generator 101 and the second high-frequency generator 102 are DDS high-frequency generators, the first high-frequency signal S1 and the second high-frequency signal having the same frequency as the input reference clock signal are used. In addition to generating S2, it is possible to synthesize a desired frequency using the reference clock signal. For example, even if the frequency of the reference clock signal input to the first high-frequency generator 101 is 50 MHz or 100 MHz, if the output frequency commanded by the first frequency command Cf1 is 50.5 MHz, the first The high frequency generator 101 can generate a first high frequency signal S1 having a frequency of 50.5 MHz. The same applies to the second high-frequency generator 102.
Of course, the first high-frequency generator 101 and the second high-frequency generator 102 are not DDS high-frequency generators as long as they have a function capable of synthesizing a desired frequency using the reference clock signal. May be.

  Reference numeral 104 denotes frequency commands Cf1 and Cf2 to the first and second high frequency generators 101 and 102 so as to keep the difference delta f between the frequency f1 of the first high frequency signal S1 and the frequency f2 of the second high frequency signal S2 constant. Is a frequency command section for respectively giving.

  The frequency command unit 104 used in the present embodiment uses a predetermined frequency or a frequency input from a host controller or the like as a first frequency f1, and a frequency having a certain difference delta f with respect to the first frequency f1. Is a second frequency f2, and a first frequency command Cf1 for instructing to generate a first high-frequency signal S1 having a first frequency f1 and a second high-frequency signal S2 having a second frequency f2 are generated. By simultaneously providing the first high frequency generator 101 and the second high frequency generator 102 with the second frequency command Cf2 for instructing to perform the operation, the frequency f1 of the first high frequency signal and the frequency of the second high frequency signal are respectively provided. The first high-frequency generator 101 and the second high-frequency generator 102 are controlled so that the difference from f2 is always kept at a constant value delta f (= | f1-f2 |). The frequency f2 of the second high-frequency signal S2 may be lower or higher than the frequency f1 of the first high-frequency signal S1. Note that the frequency f1 of the first high-frequency signal S1 (the output frequency of the first high-frequency generator 101) matches the basic frequency of the first high-frequency power supply device 11.

  In the reference clock generation unit 116 described later, the first frequency command Cf1 and the second frequency command Cf2 may be used. In this case, the first frequency command Cf1 and the second frequency command Cf2 are output to the reference clock generator 116.

Reference numeral 105 denotes a power amplifying unit including a known power amplifying circuit, which amplifies the first high-frequency signal S1 and outputs high-frequency power applied to the load. The output of the power amplifier 105 is supplied to a load such as a plasma processing apparatus through an impedance matching device (not shown). In some cases, the impedance matching device is not used.

  Reference numeral 106 denotes a high frequency detection unit inserted between the output terminal of the power amplification unit 105 and an impedance matching device (not shown). The high-frequency detection unit is formed of, for example, a directional coupler, and demultiplexes a part of traveling wave power from the power amplification unit 105 toward the load to generate a traveling wave detection signal Sp including information on the traveling wave power. Output.

  Note that the frequency component of the traveling wave detection signal obtained by the high-frequency detection unit 106 includes the frequency f1 of the first high-frequency signal S1 as a main component, but also includes spurious frequency components. The spurious frequency also changes in accordance with the change in the frequency f1 of the first high-frequency signal S1.

  Reference numeral 107 denotes a multiplication unit to which the traveling wave detection signal Sp obtained by the high frequency detection unit and the second high frequency signal S2 output from the second high frequency generation unit 102 are input. The multiplication unit detects the traveling wave. By multiplying the signal Sp by the second high-frequency signal S2, a signal Sfp ′ including the frequency component of the difference between the frequency f1 of the first high-frequency signal S1 and the frequency f2 of the second high-frequency signal S2 is output.

  As is well known, when two signals are multiplied by the multiplication unit, a signal including not only the frequency component of the frequency difference between the two signals but also the frequency component of the sum of the frequencies of the two signals is obtained. For example, in the system shown in FIG. 6, the case where the basic frequency of the first high-frequency power supply device 11 (the frequency f1 of the first high-frequency signal S1) is 50 MHz and the basic frequency of the second high-frequency power supply device 12 is 2 MHz. Then, components such as 46, 48, 52, and 54 MHz as spurious components flow into the vicinity of the fundamental frequency of 50 MHz through the output transmission system to the output terminal of the high frequency power supply device 11. In this case, when the output frequency of the second high frequency generator 102 (frequency f2 of the second high frequency signal S2) is set to 49.5 MHz and the desired difference frequency is 0.5 MHz, the difference frequency with respect to the basic frequency 50 MHz is 0.5MHz, the sum frequency is 99.5MHz. Similarly, the difference frequencies for the above spurious components are 3.5, 1.5, 2.5, and 4.5 MHz, and the sum frequencies are 95.5, 97.5, 101.5, and 103.5 MHz.

  As described above, since the difference between the frequency f1 of the first high-frequency signal S1 and the frequency f2 of the second high-frequency signal S2 is controlled to be always kept at a constant value delta f, the first high-frequency power supply device is assumed. Even when the 11 fundamental frequency (frequency f1 of the first high-frequency signal S1) is changed from 50 MHz to 50.5 MHz, the difference frequency with respect to the fundamental frequency 50 MHz is constant at 0.5 MHz. Further, since the spurious frequency also changes in accordance with the change in the fundamental frequency (the frequency f1 of the first high-frequency signal S1), the difference frequency with respect to the spurious component does not change from the relationship shown above.

  Therefore, if a filter 109 that passes a component having a difference frequency of 0.5 MHz with respect to the fundamental frequency and removes a frequency component equal to or higher than the difference frequency of the spurious component (for example, having a characteristic with a cutoff frequency of 1 MHz), the difference with respect to the fundamental frequency is used. The component of frequency 0.5MHz can be extracted with high accuracy. That is, the fundamental frequency component can be accurately extracted from the signal output from the high frequency detector 106.

  When the fundamental frequency of the first high frequency power supply device 11 is changed from 50 MHz to 50.5 MHz, the sum frequency with respect to the fundamental frequency 50 MHz is 100.5 MHz, which is different from the relationship shown above. Further, the sum frequency for the spurious component is also different from the relationship shown above. However, since these frequency components are objects to be removed by the filter 109, they do not have an influence.

The filter 109 is a filter that extracts a desired difference frequency signal Sfp from the output of the multiplication unit 107. This filter may consist of an analog filter (pand pass filter or low pass filter) or a digital filter (a digital filter is constituted by a digital circuit, that is, a digital filter is a kind of digital circuit). Good.
The filter 109 may be a combination of an analog filter and a digital filter that digitally processes the output of the analog filter and extracts a difference frequency signal. In other words, if filtering is performed by the digital filter after removing the unnecessary frequency component by passing the output of the multiplier through the analog filter, there is an advantage that signal processing in the digital filter is facilitated.

  The digital circuit can be easily configured by using a gate array such as an FPGA (Field Programmable Gate Array) that can appropriately define and change an internal logic circuit. In this embodiment, not only the filter 109 but also a differential frequency level detection unit 110, a first level control unit 112, and a reference clock signal generation unit 116, which will be described later, are configured by digital circuits (for example, FPGA).

  The difference frequency signal Sfp extracted by the filter 109 is given to the difference frequency level detection unit 110. The difference frequency level detection unit 110 is a part that detects the level of the difference frequency signal Sfp by performing analog processing or digital processing on the difference frequency signal Sfp. In the present embodiment, the difference frequency level detection unit 110 is composed of a digital circuit, and outputs a level detection signal Spa indicating the level of the difference frequency signal Sfp by digitally processing the difference frequency signal Spf.

  In this embodiment, since analog circuits and digital circuits are mixed, an A / D converter and a D / A converter are used as necessary, but the illustration is omitted in FIG. For example, when the filter 109 is an analog filter and the difference frequency level detection unit 110 is a digital circuit, an A / D converter may be inserted between them.

  The level detection signal Spa obtained from the difference frequency signal level detection unit 110 is input to the first level control unit 112 together with the first level setting signal Spas output from the first level setting unit 111. The first level control unit 112 compares the level detected by the difference frequency signal level detection unit 110 with the first set level set by the first level setting unit 111, and based on the calculation result This is a portion that gives an amplitude command Ca1 to the first high-frequency generator 101 so as to keep the traveling wave power from the power amplifier 105 toward the load at a set value.

  Note that the first setting level set by the first level setting signal Spas is the first high-frequency generation unit 101 necessary for making the power value of the traveling wave power output from the power amplification unit 105 equal to the setting value. Output level.

  The first level control unit 112 may be composed of an analog circuit or a digital circuit. In this embodiment, it consists of a digital circuit (for example, FPGA).

  Reference numeral 116 denotes a reference clock generator that generates a plurality of reference clock signals using a single crystal oscillator 117. A reference clock signal (for example, a signal of 100 MHz) used in the digital circuit is given from the reference clock generator 116, and the digital circuit performs various processes using the reference clock signal. In many cases, the frequency of the reference clock signal is the sampling frequency in the digital circuit. As described above, in this embodiment, since the filter 109 and the difference frequency level detection unit 110 are configured by digital circuits (for example, FPGA), the reference clock signal generated by the reference clock generation unit 116 is the filter. 109 and the difference frequency level detection unit 110.

  Further, the reference clock generator 116 generates a reference clock signal having a frequency (for example, 50 MHz) corresponding to the frequency command given from the frequency command unit 104 to the first high frequency generator as a reference clock signal used in the first high frequency generator. A reference clock signal having a frequency (for example, 49.5 MHz) corresponding to a frequency command given from the frequency command unit to the second high frequency generation unit is generated as a reference clock signal used in the second high frequency generation unit.

That is, it is necessary to correspond to the first frequency command Cf1 given from the frequency command unit 104 to the first high frequency generation unit 101 and the second frequency command Cf2 given from the frequency command unit 104 to the second high frequency generation unit 102. If necessary, the first frequency command Cf1 and the second frequency command Cf2 output from the frequency command unit 104 may be input.
Of course, the frequency (for example, 50 MHz) corresponding to the first frequency command Cf1 given from the frequency command unit 104 to the first high frequency generation unit, and the second frequency command Cf2 given from the frequency command unit to the second high frequency generation unit. If the corresponding frequency (for example, 49.5 MHz) is a constant value (fixed value), it is not necessary to input the first frequency command Cf1 and the second frequency command Cf2 output from the frequency command unit 104, for example, a memory (Not shown) may be provided to store the frequency.

  If the first high frequency generator 101 and the second high frequency generator 102 have a function capable of synthesizing a desired frequency, such as a DDS high frequency generator, the first high frequency generator 116 generates a first high frequency from the reference clock generator 116. The frequency of the reference clock signal supplied to the unit 101 and the second high frequency generation unit 102 does not need to correspond to the first frequency command Cf1 and the second frequency command Cf2. Therefore, the frequency of the reference clock signal supplied to the first high frequency generator 101 may be set to a constant value (for example, 50 MHz or 100 MHz). Similarly, the frequency of the reference clock signal supplied to the second high frequency generator 102 may be set to a constant value (for example, 49.5 MHz, 100 MHz). Further, as in the above example, the frequency of the reference clock signal supplied to the first high frequency generator and the second high frequency generator can be made the same as the output frequency of the crystal oscillator 117. In this case, the reference clock generator 116 may supply the output of the crystal oscillator 117 to the first high frequency generator 101 and the second high frequency generator 102 as they are.

  In this embodiment, since digital processing is performed using a digital circuit (for example, FPGA), a plurality of reference clock signals can be generated using the output signal of a single crystal oscillator 117. In the digital circuit, since the frequency is normalized by “input frequency / sampling frequency”, when configured as in this embodiment, both “input frequency” and “sampling frequency” are the same as the output frequency of the crystal oscillator. A percentage error is included. As a result, the error in the output frequency of the crystal oscillator is canceled out, so that a problem caused by the error in the output frequency of the crystal oscillator does not occur. In the present embodiment, the filter 109 and the difference frequency signal level detection unit 110 have the effects as described above. Hereinafter, the reason will be described.

<Effect in filter>
FIG. 3 is a block diagram illustrating a configuration example of the filter 109. As described above, the filter 109 may be an analog filter as shown in FIG. 3A, or may be a digital filter as shown in FIG. 3B. Moreover, as shown in FIG.3 (c), you may consist of a combination of an analog filter and the digital filter which digitally processes the output of an analog filter, and extracts a difference frequency signal.

  In recent years, digitalization of signal processing has progressed, and advanced signal processing has been performed using the above-described FPGA or the like. Therefore, as shown in FIGS. 3B and 3C, the digital filter is often included. Of these, the configuration shown in FIG. In addition, as such a digital filter, a band pass filter having a very narrow pass frequency band tends to be used.

  For example, as described above, the frequency of the first high frequency signal S1 output from the first high frequency generator 101 is 50 MHz, and the frequency of the second high frequency signal S2 output from the second high frequency generator 102 is 49. If it is .5 MHz, the difference frequency passing through the multiplication unit 107 is a signal including a frequency component of 0.5 MHz. This 0.5 MHz is the reference frequency. The filter 109 is desired to have a characteristic that allows a frequency component of 0.5 MHz, which is a reference frequency, to pass therethrough but removes other frequency components. Therefore, a digital bandpass filter having characteristics as shown in FIG. 4 is used.

  FIG. 4 is a diagram illustrating an example of frequency characteristics of the digital bandpass filter. In FIG. 4, the horizontal axis represents a normalized frequency represented by “input frequency / sampling frequency”, and the vertical axis represents the output level [dB] of the digital bandpass filter.

  In the above example, the frequency of the output signal Sfp ′ of the multiplier 107 becomes the input frequency, and the frequency of the reference clock signal used in the digital circuit becomes the sampling frequency. That is, if there is no error in the output frequency of the crystal oscillator 117, the input frequency is 0.5 MHz, and the frequency of the reference clock signal used in the digital circuit is 100 MHz, so the normalized frequency is 0.005.

  Referring now to FIG. 4, when the normalized frequency is 0.005, it is shown that the signal level is designed to pass through a digital bandpass filter with no attenuation (or little attenuation). ing. However, it can be seen that if the normalized frequency deviates slightly from 0.005, the signal level is greatly attenuated.

  Since the reference clock generator 116 generates a plurality of reference clock signals using a single crystal oscillator as in the present embodiment, the frequency of the plurality of reference clock signals to be generated is also different from that of the crystal oscillator 117. The same percentage error as the output frequency is included. Using the reference clock signal generated by the reference clock generator 116, the first high frequency generator 101 and the second high frequency generator 102 generate the first high frequency signal S1 and the second high frequency signal S2. Therefore, the two signals input to the multiplication unit 107 also contain the same ratio of errors. For this reason, the signal Sfp 'including the frequency component of the difference between the frequency f1 of the first high-frequency signal S1 and the frequency f2 of the second high-frequency signal S2 output from the multiplier 107 also includes the same ratio of errors.

  Here, assuming that the output frequency of the crystal oscillator 117 has an α-fold error (α = 1.01 when the error is + 1%), the frequency of the reference clock signal for the digital circuit is 100 × α MHz. Become. In addition, since the reference clock generator 116 generates a plurality of reference clock signals using a single crystal oscillator, the frequency of the reference clock signal for the first high frequency generator and the second high frequency generator The above α times error also occurs in the frequency of the reference clock signal. That is, the frequency of the reference clock signal for the first high frequency generator is 50 × α MHz, and the frequency of the reference clock signal for the second high frequency generator is 49.5 × α MHz. Therefore, the difference frequency passing through the multiplication unit 107 is 50 × α−49.5 × α = 0.5 × α MHz. In addition, since the above-mentioned α times error also occurs in the frequency of the reference clock signal for the digital circuit, it becomes 100 × α MHz.

  Then, the normalized frequency represented by “input frequency / sampling frequency” is 0.5 × α [MHz] / 100 × α [MHz] = 0.005. That is, even if there is an α-fold error in the output frequency of the crystal oscillator 117, the result is the same as when there is no error in the output frequency of the crystal oscillator, so that no error is apparently included. Therefore, the conventional problem can be improved.

  When an analog filter is used as the filter 109, it is difficult to design a bandpass filter having a very narrow pass frequency band as described above. On the contrary, due to an error in the output frequency of the crystal oscillator 117, the frequency component of the difference between the frequency f1 of the first high-frequency signal S1 output from the multiplier 107 and the frequency f2 of the second high-frequency signal S2 is included. Even if an error is included in the signal Sfp ′, there is almost no influence.

<Effect in the difference frequency signal level detection unit>
As described above, the difference frequency signal level detection unit 110 detects the level of the output signal of the difference frequency signal Spf output from the filter 109. Further, since the difference frequency signal Spf is a signal having a frequency component of, for example, 0.5 MHz, the signal level can be detected by calculating the amplitude of the signal.

As is well known, the sine wave signal can be expressed by equation (1). Thus, the frequency of the sine wave signal is also normalized by “input frequency / sampling frequency”. The same applies to a cosine wave signal described later.
Asin (2π · fin / fsample · (t)) (1)
A: Amplitude fin: Frequency of measurement signal fsample: Sampling frequency

Further, the sine wave signal can be expressed by Expression (2).
Acos (2π · fin / fsample · (t)) (2)

Here, it is well known that a sine wave is differentiated into a cosine wave, and since the differentiation is expressed by a slope between two points, Expression (2) can be expressed as Expression (3). .
Acos (2π · fin / fsample · (t))
= (Asin (2π · fin / fsample · (t + 1))-Asin (2π · fin / fsample · (t-1))) / (2 · sin (2π · fin / fsample)) (3)

  In the above equation (3), the value of the sampling data at the reference point is Asin (2π · fin / fsample · (t)), and the value of the sampling data immediately before the reference point is Asin (2π · fin / Fsample · (t−1)), and the value of the sampling data immediately after the reference point is Asin (2π · fin / fsample · (t + 1)). Further, the above equation (3) can be easily obtained from the trigonometric function formula (sin α−sin β = 2 cos ((α + β) / 2) · sin ((α−β) / 2)).

  That is, if the slope of the digital signal waveform at the reference point is calculated using the sampling data at one point before and after the reference point in the sampling data at the plurality of points constituting the digital signal waveform, the differential value at the reference point is obtained. The corresponding value can be determined.

If the sine wave value and the cosine wave value at the same time are known, the amplitude of the digital signal waveform can be calculated by equation (4).
A = √ (S ² + C ² ) (4)
S: Sampling data value at the reference point (sine wave value)
C: Differential value of digital signal waveform at reference point (cosine wave value)

  Therefore, if the data of the reference point and the sampling data of one point before and after each of the sampling data at a plurality of points constituting the digital signal waveform are known (a total of three points of data), the amplitude of the digital signal waveform can be calculated.

  That is, since the difference frequency signal level detection unit 110 also normalizes the input signal at “input frequency / sampling frequency”, if configured as in this embodiment, both the “input frequency” and “sampling frequency” are crystal oscillators. Error of the same rate as the output frequency of. However, since the error of the output frequency of the crystal oscillator is canceled as described above, the problem caused by the error of the output frequency of the crystal oscillator does not occur.

  Therefore, as described in the present embodiment, when the spurious component is removed by frequency conversion filtering, not only the fundamental frequency component can be accurately extracted but also due to an error in the output frequency of the crystal oscillator. The problem can also be improved. As a result, it is possible to provide a high-frequency power supply device that can perform accurate power control even if there is an error in the output frequency of the crystal oscillator that generates the reference clock.

  As described above, since both the filter 109 and the difference frequency signal level detection unit 110 are effective, even if both the filter 109 and the difference frequency signal level detection unit 110 are not configured by digital circuits, only one of them is provided. Even if it is constituted by a digital circuit, problems caused by errors in the output frequency of the crystal oscillator can be improved.

<Other effects>
In the present embodiment, an output level detector 113 for detecting the output level of the second high frequency generator 102 is also provided, and the output signal S2a is output from the second level setting unit 114 as a second level. The signal is input to the second level controller 115 together with the setting signal S2as. The second level control unit 115 compares the output level of the second high frequency generation unit 102 detected by the output level detection unit 113 with the second set level set by the second level setting unit 114. Based on the calculation result, an amplitude command Ca2 is given to the second high-frequency generator 102 so as to keep the level of the second high-frequency signal S2 output from the second high-frequency generator 102 at the second set level. In the present embodiment, the second level control unit 115 is composed of a digital circuit, and the level detection signal S2a obtained from the output level detection unit 113 is given to the second level control unit 115 through the A / D converter. The second level control unit 115 calculates the level of the second high-frequency signal S2 necessary for making the level of the level detection signal S2a equal to the first set level, and calculates the second high-frequency signal of the calculated level. An amplitude command Ca2 is given to the second high frequency generator 102 so that S2 is generated from the second high frequency generator 102.

In the high frequency power supply device of the present embodiment, the frequency command unit 104 is provided in the first and second high frequency generation units so as to keep the difference between the frequency of the first high frequency signal and the frequency of the second high frequency signal constant. Since the frequency commands Cf1 and Cf2 are given simultaneously, the difference delta f between the frequency f1 of the first high-frequency signal S1 and the frequency f2 of the second high-frequency signal S2 is always constant. The power amplifier 105 amplifies the first high-frequency signal S1 obtained from the first high-frequency generator 101 and outputs high-frequency power supplied to the load. The traveling wave power given to the load from the power amplifier 105 is detected by the high frequency detector 106. The traveling wave detection signal Sp obtained from the high frequency detection unit 106 is input to the multiplication unit 107 together with the second high frequency signal S2. The multiplier 107 multiplies the traveling wave detection signal and the second high-frequency signal S2, and the frequency of the difference delta f (= f1-f2) between the frequency of the first high-frequency signal and the frequency of the second high-frequency signal. A signal Sfp ′ including the component is output. The filter 109 removes a spurious component from the signal Sfp ′ to extract a difference frequency signal Sfp having a frequency component that is a difference between the frequency of the first high-frequency signal and the frequency of the second high-frequency signal. Sfp is given to the difference frequency signal level detection unit 110. The difference frequency signal level detection unit 110 detects the level by detecting the difference frequency signal Sfp, and provides the detected level to the first level control unit 112. The first level control unit 112 compares the level detected by the difference frequency signal level detection unit 110 with the first set level set by the first level setting unit 111, and based on the calculation result Since the amplitude command Ca1 is given to the first high frequency generator 101 so that the traveling wave power from the power amplifier 105 toward the load is kept at the set value, the high frequency power given from the power amplifier 105 to the load is kept at the set value. It is.

  As described above, in the present invention, the first and second high-frequency generators 101 and 102 maintain the difference between the frequency f1 of the first high-frequency signal S1 and the frequency of the second high-frequency signal S2. Since the difference between the frequency of the first high-frequency signal and the frequency of the second high-frequency signal is kept constant by giving the frequency command, the first high-frequency power is changed to change the frequency of the high-frequency power applied to the load. Correspondence between the power value of the output of the power amplifier 105 and the level detected by the difference frequency signal level detector 110 when the frequency of the high frequency power applied to the load is changed even if the output frequency of the generator 101 is changed A high frequency that can prevent the relationship from changing and can arbitrarily change the frequency of the high-frequency power without losing any precision in the control of the power value of the high-frequency power supplied to the load. It can be obtained the power supply.

  Further, in the high frequency power supply device of the present embodiment, the second level control unit 115 compares the output level of the second high frequency generation unit 102 detected by the output level detection unit 113 with the second set level. In order to give an amplitude command to the second high-frequency generator 102 so as to keep the output level of the second high-frequency generator 102 (the signal level of the second high-frequency signal S2) at a set constant value based on the calculation result. The output level of the second high frequency generator can always be kept at a constant level (second set level). Therefore, the output level of the multiplication unit 108 varies due to the variation of the output level of the second high frequency generation unit, and the power value of the output of the power amplification unit 105 and the level detected by the difference frequency signal level detection unit 110 It is possible to prevent the correspondence relationship from changing.

  Therefore, according to this embodiment, when the spurious component is removed by frequency conversion filtering, not only the fundamental frequency component can be accurately extracted, but also a problem caused by an error in the output frequency of the crystal oscillator. Can improve. Furthermore, the output of the multiplier fluctuates due to the fluctuation of the output level of the second high frequency generator, and the correspondence between the power value of the output of the power amplifier 105 and the level detected by the difference frequency signal level detector 110 changes. Therefore, the control for keeping the power value of the high-frequency power at the set value can be performed with higher precision.

  As in the above embodiment, it is desirable to control the output level of the second high-frequency power generation unit 102 to be constant, but when the expected fluctuation in the output of the second high-frequency power generation unit 102 is slight, The control system for controlling the output level of the second high-frequency power generator 102 can be omitted. Therefore, in the basic configuration of the high-frequency power supply device according to the present invention, the output level detection unit 113, the second level control unit 115, and the second level setting unit 114 of the embodiment shown in FIG. it can.

  In the embodiment shown in FIG. 1, the first and second high frequency generators 101 and 102 are independent DDSs, but these are also digital circuits (for example, FPGA) together with the first level controller 112 and the like. It may be configured.

[Second Embodiment]
FIG. 2 shows the configuration of the second embodiment of the high-frequency power supply device according to the present invention. In this embodiment, the high-frequency detection unit 106 includes a traveling wave detection signal Sp including information on traveling wave power from the power amplification unit 105 toward the load and a reflected wave including information on reflected wave power from the load side toward the power amplification unit 105. The detection signal Sr is output. In the first embodiment shown in FIG. 1, the amplitude command is given to the first high frequency generator 101 so as to keep the traveling wave power output from the power amplifier 105 at a set value. In the second embodiment, an amplitude command is given to the first high-frequency generator 101 so that the power given from the power amplifier 105 to the load (the power obtained by subtracting the reflected wave power from the traveling wave power) is maintained at the set value. It is configured as follows. Hereinafter, a description will be given focusing on differences from the first embodiment.

  In the embodiment shown in FIG. 2, the multiplication unit 107, the filter 109, and the difference frequency signal level detection unit 110 shown in FIG. 1 are replaced with the first multiplication unit 107, the first filter 109, and the first difference frequency signal level, respectively. The detection unit 110 is used. Further, in addition to the configuration shown in FIG. 1, a second multiplication unit 121, a second filter 123, and a second difference frequency signal level detection unit 124 are further provided. The first level setting unit 111 and the first level control unit 112 have functions different from those shown in FIG. 1 as described later, but the same reference numerals are used for convenience.

  The second multiplication unit 121 multiplies the reflected wave detection signal Sr obtained by the high frequency detection unit 106 and the second high frequency signal S2 output from the second high frequency generation unit 102 to obtain the first high frequency signal S1. The signal Sfr ′ including the frequency component of the difference between the frequency f1 of the second and the frequency f2 of the second high-frequency signal S2 is output.

  The second filter 123 removes a spurious component from the output of the second multiplier 122 and has a second difference having a frequency component that is the difference between the frequency of the first high-frequency signal and the frequency of the second high-frequency signal. The frequency signal Sfr is extracted, and the extracted second difference frequency signal Sfr is supplied to the second difference frequency signal level detection unit 124. The second filter 123 has a configuration similar to that of the first filter 109.

  In the embodiment shown in FIG. 2, the second filter 123 may be an analog filter or a digital filter. The second filter 123 may be a combination of an analog filter and a digital filter. In the present embodiment, the second filter 123 is configured by a digital filter or a combination of an analog filter and a digital filter. In other words, in the present embodiment, at least a part of the second filter 123 is configured by a digital circuit.

  The second difference frequency signal level detection unit 124 detects the level of the second difference frequency signal Sfr, and provides the frequency control unit 104 with a second level detection signal Sra indicating the detected level. The second difference frequency signal level detection unit 124 has the same configuration as that of the first difference frequency signal level detection unit 110.

  Further, the second difference frequency signal level detection unit 124 may be composed of an analog circuit (for example, a detection circuit) or a digital circuit. In the present embodiment, the second difference frequency signal level detection unit 124 is formed of a digital circuit, and outputs a level detection signal Sra indicating the level of the difference frequency signal Sfr by digitally processing the difference frequency signal Spr.

  In the present embodiment, as described above, the second filter 123 and the second difference frequency signal level detection unit 124 are not only configured by a digital circuit (for example, FPGA), but also in the first embodiment. Similarly, the first filter 109, the first difference frequency signal level detection unit 110, and the first level control unit 112 are configured by digital circuits (for example, FPGA).

  The level detection signal Sra obtained from the second difference frequency signal level detection unit 124 is given to the first level control unit 112 together with the level detection signal Spa output from the second difference frequency signal level detection unit 110. . The first level control unit 112 of the present embodiment is obtained by subtracting the level detected by the second difference frequency signal level detection unit 124 from the level detected by the first difference frequency signal level detection unit 110. The level is compared and calculated with the first set level set by the first set level setting unit 111, and the power given from the power amplification unit 105 to the load based on the calculation result (the reflected wave power is calculated from the traveling wave power). An amplitude command is given to the first high frequency generator so as to keep the subtracted power at a set value.

  Since the reference clock generator 116 generates a plurality of reference clock signals using a single crystal oscillator, the frequency of the plurality of reference clock signals to be generated also has an error in the same proportion as the output frequency of the crystal oscillator 117. Is included. Using the reference clock signal generated by the reference clock generator 116, the first high frequency generator 101 and the second high frequency generator 102 generate the first high frequency signal S1 and the second high frequency signal S2. Therefore, the two signals respectively input to the first multiplier 107 and the second multiplier 121 include the same ratio of errors. For this reason, the signal Sfp ′ including the frequency component of the difference between the frequency f1 of the first high-frequency signal S1 and the frequency f2 of the second high-frequency signal S2 output from the first multiplier 107 also includes an error of the same ratio. It is. Further, the signal Sfr 'including the frequency component of the difference between the frequency f1 of the first high-frequency signal S1 and the frequency f2 of the second high-frequency signal S2 also includes the same ratio error.

<Effect in filter and difference frequency signal level detection unit>
Further, as described above, in the present embodiment, the first filter 109, the first difference frequency signal level detection unit 110, the second filter 123, and the second difference frequency signal level detection unit 124 are digital circuits (for example, Therefore, the reference clock signal generated by the reference clock generator 116 is supplied to the first filter 109 and the like.
Therefore, as described in the first embodiment, even if the first filter 109 and the first difference frequency signal level detection unit 110 are configured by digital circuits, the error of the output frequency of the crystal oscillator is canceled out. The problem caused by the error of the output frequency of the crystal oscillator does not occur.
Further, for the same reason as the first filter 109, even if the second filter 123 is configured by a digital circuit, the error in the output frequency of the crystal oscillator is canceled out, resulting in the error in the output frequency of the crystal oscillator. There is no problem.
Further, for the same reason as the first difference frequency signal level detection unit 110, even if the second difference frequency signal level detection unit 124 is configured by a digital circuit, the error of the output frequency of the crystal oscillator is canceled. Problems caused by errors in the output frequency of the crystal oscillator do not occur.

  Therefore, as described in the present embodiment, when the spurious component is removed by frequency conversion filtering, not only the fundamental frequency component can be accurately extracted but also due to an error in the output frequency of the crystal oscillator. The problem can also be improved. As a result, it is possible to provide a high-frequency power supply device that can perform accurate power control even if there is an error in the output frequency of the crystal oscillator that generates the reference clock.

  As described above, each of the filter 109, the difference frequency signal level detection unit 110, the second filter 123, and the second difference frequency signal level detection unit 124 is effective, so the filter 109, the difference frequency signal level detection unit 110, the second filter 123, and the second difference frequency signal level detection unit 124 are not configured by a digital circuit, but at least one of the second filter 123 and the second difference frequency signal level detection unit 124 is configured by a digital circuit. Can be improved.

<Other effects>
Further, when configured as in the present embodiment, the correspondence between the power value of the traveling wave power and the level detected by the first difference frequency signal level detection unit 110 and the reflected wave, regardless of the frequency of the high frequency power. The correspondence between the power value of the power and the level detected by the second difference frequency signal level detection unit 124 is prevented from being distorted, and the first and second frequency fluctuations are caused by fluctuations in the output level of the second high frequency generation unit. The outputs of the multipliers 108 and 122 vary, and the correspondence between the power value of the traveling wave power and the level detected by the first difference frequency level detection unit, and the power value of the reflected wave power and the second difference frequency level. Since it is possible to prevent the correspondence relationship with the level detected by the detection unit from changing, it is possible to precisely perform control for keeping the power value of the difference between the traveling wave power and the reflected wave power at the set value. Therefore, according to the present embodiment, the precision of the control for maintaining the power value of the difference between the traveling wave power given from the power amplification unit to the load and the reflected wave power returning from the load to the power amplification unit side at the set value is A high-frequency power supply device that can change the frequency of the high-frequency power without damaging it can be obtained.

DESCRIPTION OF SYMBOLS 101 1st high frequency generation part 102 2nd high frequency generation part 103 Frequency setting part 104 Frequency command part 105 Power amplification part 106 High frequency detection part 107 Multiplication part (1st multiplication part)
109 filter (first filter)
110 Difference frequency signal level detector (first difference frequency signal level detector)
111 Second level setting unit 112 First level control unit 113 Output level detection unit 114 Second level setting unit 115 Second level control unit 116 Reference clock signal generation unit 117 Crystal oscillator 120 Reflected wave reference level setting unit 121 Second multiplier 123 Second filter 124 Second difference frequency signal level detector

Claims (7)

A reference clock generation unit that generates a plurality of reference clock signals using a single crystal oscillator;
The reference clock signal generated by the reference clock generation unit is used to generate a high-frequency signal having an output frequency commanded by a frequency command and an output amplitude level commanded by an amplitude level command. First and second high frequency generators for generating different first high frequency signals and second high frequency signals, respectively;
A frequency command unit that gives the frequency command to the first and second high frequency generation units so as to keep a difference between the frequency of the first high frequency signal and the frequency of the second high frequency signal constant;
A power amplifier for amplifying the first high-frequency signal;
A high frequency detection unit for detecting a traveling wave detection signal including information on traveling wave power from the power amplification unit toward the load;
Multiplying the traveling wave detection signal obtained by the high-frequency detection unit and the second high-frequency signal includes a frequency component of a difference between the frequency of the first high-frequency signal and the frequency of the second high-frequency signal. A multiplier for obtaining a signal;
A filter that extracts a difference frequency signal having a frequency component of a difference between the frequency of the first high-frequency signal and the frequency of the second high-frequency signal from the output of the multiplier;
A difference frequency signal level detection unit for detecting a level of the difference frequency signal extracted by the filter;
The first high-frequency generation is performed so that the level detected by the difference frequency signal level detection unit is compared with a set level and the traveling wave power from the power amplification unit to the load is maintained at a set value based on the calculation result. A level control unit for giving the amplitude level command to the unit;
A high-frequency power supply device. An output level detector for detecting an output level of the second high frequency generator;
The level detected by the output level detection unit is compared with a second set level, and the second high frequency generation unit is maintained at a set constant value based on the calculation result. A second level control unit for giving an amplitude command to the high frequency generation unit of
The high frequency power supply device according to claim 1, further comprising:   The high frequency power supply device according to claim 1, wherein at least one of the filter and the difference frequency signal level detection unit is configured by a digital circuit. A reference clock generation unit that generates a plurality of reference clock signals using a single crystal oscillator;
The reference clock signal generated by the reference clock generation unit is used to generate a high-frequency signal having an output frequency commanded by a frequency command and an output amplitude level commanded by an amplitude level command. First and second high frequency generators for generating different first high frequency signals and second high frequency signals, respectively;
A frequency command unit that gives the frequency command to the first and second high frequency generation units so as to keep a difference between the frequency of the first high frequency signal and the frequency of the second high frequency signal constant;
A power amplifier for amplifying the first high-frequency signal;
A high frequency detection unit for detecting a traveling wave detection signal including information on traveling wave power from the power amplification unit toward the load and a reflected wave detection signal including information on reflected wave power from the load side toward the power amplification unit;
Multiplying the traveling wave detection signal obtained by the high-frequency detection unit and the second high-frequency signal includes a frequency component of a difference between the frequency of the first high-frequency signal and the frequency of the second high-frequency signal. A first multiplier for obtaining a signal;
A first filter for extracting a first difference frequency signal having a frequency component of a difference between the frequency of the first high frequency signal and the frequency of the second high frequency signal from the output of the first multiplication unit;
A first difference frequency signal level detection unit for detecting a level of the first difference frequency signal extracted by the first filter;
Multiplication of the reflected wave detection signal obtained by the high-frequency detection unit and the second high-frequency signal includes a frequency component of a difference between the frequency of the first high-frequency signal and the frequency of the second high-frequency signal. A second multiplier for obtaining a signal;
A second filter for extracting a second difference frequency signal having a frequency component of a difference between the frequency of the first high frequency signal and the frequency of the second high frequency signal from the output of the second multiplication unit;
A second difference frequency level detection unit for detecting a level of the second difference frequency signal extracted by the second filter;
A level obtained by subtracting the level detected by the second difference frequency signal level detection unit from the level detected by the first difference frequency signal level detection unit is compared with a set level, and based on the calculation result, A level control unit that gives the amplitude command to the first high-frequency generation unit so as to keep the power supplied from the power amplification unit to the load at a set value;
A high-frequency power supply device. An output level detector for detecting an output level of the second high frequency generator;
The level detected by the output level detection unit is compared with a second set level, and the second high frequency generation unit is maintained at a set constant value based on the calculation result. A second level control unit for giving an amplitude command to the high frequency generation unit of
The high frequency power supply device according to claim 4, further comprising:   At least one of the first filter, the first difference frequency signal level detection unit, the second filter, and the second difference frequency signal level detection unit is configured by a digital circuit, The high frequency power supply device according to claim 4 or 5.   7. The high frequency power supply device according to claim 1, wherein the first and second high frequency generators are DDS (Direct Digital Synthesizer) type high frequency generators.

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