JP5375680B2 - Single phase differential converter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a low-noise single phase differential converter. <P>SOLUTION: A low-noise single phase differential converter has: a non-inverting amplifier circuit including a first output load resistor and a first amplifying transistor provided between a power source and a reference voltage, the first amplifying transistor receiving a single phase input signal, and including a first output terminal provided at a node on the first amplifying transistor of the first output load resistor; an inverting amplifier circuit including a second output load resistor and a second amplifying transistor provided between the power source and the reference voltage, the second amplifying transistor receiving the single phase input signal, and including a second output terminal provided at a node on the second amplifying transistor of the second output load resistor; and an additional current source commonly provided at the first and second output terminals via first and second impedance means having high impedance in a frequency band of the single phase input signal. <P>COPYRIGHT: (C)2011,JPO&amp;INPIT

Description

  The present invention relates to a single-phase differential converter.

  The single-phase differential converter is a converter that amplifies a single-phase input signal and converts it into a differential output signal. For example, a single-phase differential converter converts a high-frequency signal received from an antenna from a single phase to a differential as a low noise amplifier provided at the front end of a reception circuit of a wireless communication device. Single-phase differential converters that are used in this way are required to have low noise and low distortion characteristics. In particular, at the front end of the receiving circuit, if the noise of the single-phase differential converter itself is superimposed or distorted and amplified on a small received signal, the subsequent detecting circuit or demodulating circuit can appropriately detect or demodulate. Can not.

  The single-phase differential converter is described in Non-Patent Document 1 below, for example.

  The single-phase differential converter includes an inverting amplifier circuit that inverts and amplifies a single-phase input signal, and a non-inverting amplifier circuit that amplifies the signal without inversion. These inverting amplifier circuits and non-inverting amplifier circuits are constituted by an output load circuit and an amplification transistor. In general, the noise power generated by the semiconductor element itself is larger in the MOS transistor than in the resistance element, and the resistance element has a linear characteristic. Therefore, there is no resistance element in the output load circuit of the above inverting amplifier circuit or non-inverting amplifier circuit. Adopted.

  When a resistive element is used for the output load, the voltage drop of the resistive element of the output load varies according to the increase / decrease of the DC current of the amplification transistor as the gain increases / decreases, and the operating point (DC level) of the output signal also varies. The fluctuation of the output operating point fluctuates the drain-source voltage of the amplifying transistor, and the proper operation of the amplifying transistor is not guaranteed. For example, if the drain-source voltage becomes too small, the amplification transistor cannot operate in the saturation region.

  Therefore, in order to control the output operating point, it has been proposed to provide an additional current source for each output load of both amplifier circuits so that the load current flowing through the resistance element of the output load does not become excessively large. For example, Non-Patent Document 1.

R. Bagheri et al, “An 800MHz to 5GHz Software-Defined Radio Receiver in 90nm CMOS”, ISSCC Dig. Tech. Papers, pp.1932-1941, Feb, 2006

  However, if an additional current source as described above is provided at each output terminal, the noise generated by the additional current source is added to the output noise of the single-phase differential converter, which violates the requirement for low noise.

  Therefore, an object of the present invention is to provide a low-noise single-phase differential converter.

The first aspect of the single-phase differential converter is that a first output load resistor and a first amplification transistor are provided between a power supply and a reference voltage, and a single-phase input signal is supplied to the first amplification transistor. A non-inverting amplifier circuit in which a first output terminal is provided at a node on the first amplification transistor side of the first output load resistor;
A second output load resistor and a second amplification transistor are provided between the power source and a reference voltage, and the single-phase input signal is supplied to the second amplification transistor, and the second output load resistor An inverting amplifier circuit in which a second output terminal is provided at a node on the second amplifier transistor side;
The first and second output terminals have an additional current source provided in common via first and second impedance means having high impedance in the frequency band of the single-phase input signal.

  According to the first aspect, it is possible to reduce the influence of noise caused by the additional current source on the output signal of the output terminal.

It is a circuit diagram of the single phase differential converter relevant to this Embodiment. It is a circuit diagram of the single phase differential converter in this Embodiment. It is a figure which shows the model of the noise of an additional current source. It is a figure which shows the noise voltage in a voltage source model, and the noise current in a current source model. It is a figure explaining the cancellation effect of the noise of an additional current source. It is a figure explaining the noise reduction effect in a non-equilibrium state. It is a block diagram of the radio | wireless communication receiving circuit which has an in-phase differential converter of this Embodiment. It is a block diagram of the in-phase differential converter in this Embodiment. It is a block diagram of the in-phase differential converter in this Embodiment. It is a block diagram of the in-phase differential converter in this Embodiment. It is a figure which shows the specific example of an in-phase differential converter.

  FIG. 1 is a circuit diagram of a single-phase differential converter related to the present embodiment. The single-phase differential converter 10 amplifies the single-phase input signal IN and generates differential output signals OP and ON. The single-phase input signal is, for example, an AC signal in a certain frequency band, and the differential output signal is also an AC signal. This differential output signal is input to the differential circuit 20 at the next stage.

  The single-phase differential converter 10 includes an N-channel first amplification transistor N1 that amplifies an input signal at the input terminal IN, and a first output load resistor provided between the power supply VDD and the first amplification transistor N1. A non-inverting amplifier circuit composed of R1, an N-channel second amplifier transistor N2 for amplifying the input signal of the input terminal IN, and a second output provided between the power supply VDD and the second amplifier transistor N2. An inverting amplifier circuit including a load resistor R2.

  A current source I10 is provided between the drain of the first amplifying transistor N1 and the ground GND, and the first amplifying transistor N1 has a gate ground to which the bias voltage Vb1 is supplied to the gate and the input signal IN is supplied to the source. This is an amplifier circuit 11. When the voltage of the input signal IN changes, the current I3 of the common-gate transistor N1 increases or decreases accordingly, the current I1 of the output load resistor R1 also increases or decreases, and the output voltage Vout1 of the output terminal OP changes. As shown in the formula, Vout1 = VDD-R1 · I1. This output voltage Vout1 is in phase with the input signal IN.

  On the other hand, the gate of the second amplifying transistor N2 is provided with a capacitor Cin and a resistor Rin constituting an impedance matching circuit, and a bias voltage Vb2 is supplied through the resistor Rin. The second amplification transistor N2 is a common source amplifier circuit 12 in which an AC voltage of the input signal IN is applied to the gate. When the voltage of the input signal IN fluctuates, the current I4 of the common source transistor N2 increases or decreases correspondingly, the current I2 of the output load resistor R2 also increases or decreases, and the output voltage Vout2 of the output terminal ON changes. It is as shown in the equation, Vout2 = VDD-R2 · I2. This output voltage Vout2 has a phase opposite to that of the input signal IN.

  As described above, the output voltages Vout1 and Vout2 vary according to the currents I3 and I4 of the respective amplification transistors N1 and N2. Therefore, when the mutual conductance gm of the amplification transistors N1 and N2 is variably controlled in order to control the gain of the single-phase differential converter, the currents I3 and I4 fluctuate greatly accordingly, and the operating point of the output voltage, that is, AC The DC component voltage of the output signal fluctuates. In that case, when the transconductance gm is increased and the transistor currents I3 and I4 are increased, the output voltage operating point is lowered, the drain-source voltages of the amplification transistors N1 and N2 are compressed, and the transistor is saturated. Operation is not guaranteed.

Therefore, the single-phase differential converter of FIG. 1 is provided with additional current sources I7 and I8 at the output terminals OP and ON, respectively. By providing the additional current sources I7 and I8, the currents I1 and I2 flowing through the output load resistors R1 and R2 are
I1 = I3-I7
I2 = I4-I8
become. The current value of the additional current sources I7 and I8 is increased or decreased in conjunction with the increase or decrease of the currents I3 and I4 of the amplification transistors N1 and N2, thereby suppressing fluctuations in the currents I1 and I2 of the output load resistors R1 and R2. The voltage at the operating point of the output voltages Vout1 and Vout2 can be suppressed or the voltage at the operating point can be made constant. As a result, it is possible to control the drain-source voltage of each of the amplification transistors N1 and N2 so that the operation in the saturation region is maintained.

  The single-phase differential converter of FIG. 1 has additional current sources I7 and I8 respectively connected to the output terminal OP of the non-inverting amplifier circuit having the common gate transistor N1 and the output terminal ON of the inverting amplifier circuit having the common source transistor N2. Provided. The additional current sources I7 and I8 can be constituted by transistors and resistor elements, but the noise generated by each is added to the output noise of the respective output terminals OP and ON. Moreover, since the noise generated by the additional current sources I7 and I8 has no correlation, the noises of the additional current sources I7 and I8 are added to the differential output signal between the output voltages Vout1 and Vout2.

FIG. 2 is a circuit diagram of the single-phase differential converter according to the present embodiment. As in FIG. 1, the single-phase differential converter 10 amplifies the single-phase input signal IN to generate differential output signals OP and ON. The single-phase input signal IN is, for example, an AC signal in a certain frequency band, and the differential output signal V _OP -V _ON is also an AC signal. This differential output signal is input to the differential circuit 20 at the next stage.

In the single-phase differential converter 10, the first output load resistor R1 and the first amplification transistor N1 are provided between the power supply VDD and the reference voltage GND, and the single-phase input signal IN is supplied to the first amplification transistor. And a non-inverting amplifier circuit having a first output terminal OP provided at a node on the first amplifier transistor N1 side of the first output load resistor R1. As a result, the output voltage V _OP generated at the first output terminal OP is in phase with the input signal IN.

Further, in the single-phase differential converter 10, the second output load resistor R2 and the second amplification transistor N2 are provided between the power supply VDD and the reference voltage GND, and the single-phase input signal is supplied to the second amplification transistor N2. An inverting amplifier circuit is provided in which IN is supplied and a second output terminal ON is provided at a node on the second amplifier transistor N2 side of the second output load resistor R2. As a result, the output voltage V _ON generated at the second output terminal ON has a phase opposite to that of the input signal IN.

  The single-phase differential converter 10 is connected to the first and second output terminals OP and ON via first and second impedance means Z1 and Z2 having high impedance in the frequency band of the single-phase input signal IN. It has an additional current source I5 provided in common. The current of the additional current source I5 flows to the output terminals OP and ON in inverse proportion to the impedances ZN and ZP seen from the node n5 toward the output terminals OP and ON. In response to the increase or decrease of the DC currents I2 and I4 accompanying the variable control of the mutual inductance gm of the amplification transistors N1 and N2, the current value of the common additional current source I5 is increased or decreased to flow through the output load resistors R1 and R2. It is possible to suppress fluctuations in the DC currents I1 and I2 or make the DC currents I1 and I2 constant, thereby suppressing fluctuations in the operating point of the output voltage or controlling the voltage at the operating point to be constant.

The first and second impedance means Z1, Z2 have, for example, inductances L1, L2 as shown in the figure. The first and second impedance means Z1 and Z2 desirably have impedances high enough to generate differential components of the output voltages V _OP and V _ON of the output terminals OP and ON. For example, in the frequency band of the input signal IN, it is desirable that the first and second impedance means Z1 and Z2 have a larger impedance (or resistance) than the output load resistors R1 and R2. As a result, the single-phase differential converter has a sufficient amplification function.

  First, an additional current source I5 is provided at the differential output terminals OP and ON of a single-phase differential converter whose output load is composed of resistors R1 and R2 through impedance means Z1 and Z2 that are high impedance at a desired frequency. Therefore, the DC currents I1 and I2 that flow through the output load resistors R1 and R2 of the single-phase differential converter are the currents that the DC currents I3 and I4 that the amplification transistors N1 and N2 of the single-phase differential converter flow and the additional current source I5 flow. The current value is determined by I5. As described with reference to FIG. 1, the output operating point is determined by the resistance values of the output load resistors R1 and R2, the current values I1 and I2 of the DC current flowing through the output load resistors, and the power supply voltage VDD. In the single-phase differential converter of FIG. 2, the DC current values I1 and I2 flowing through the output load resistor can be controlled by controlling the currents I3 and I4 flowing through the amplification transistor and the current value I5 of the additional current source. As a result, the output operating point can be controlled.

  For example, when the mutual inductance gm of the amplification transistors N1 and N2 is variably controlled and their DC currents I3 and I4 increase or decrease, the output load resistance R1 is increased or decreased accordingly. Therefore, the fluctuation of the DC currents I1 and I2 of R2 can be suppressed or the current value can be made constant. As a result, the output operating point of the output signal can be controlled.

  Second, the additional current source I5 and each output terminal OP, ON of the single-phase differential converter are connected by the impedance means Z1, Z2 having high impedance at a desired frequency, so that the single-phase difference from the additional current source I5 is obtained. A filter circuit and a low-pass filter circuit are respectively formed between the output terminals OP and ON of the dynamic converter. Accordingly, the noise generated by the additional current source I5 is reduced by the attenuation characteristics of the filter at the output terminals OP and ON of the single-phase differential converter, and the contribution of noise by the additional current source to the output noise of the single-phase differential converter The rate is reduced. The desired frequency is preferably in the frequency band of the input signal.

Third, by providing a common additional current source at the output terminals OP and ON of the single-phase differential converter via impedance means Z1 and Z2, the noise caused by the additional current source I5 is reduced to each output terminal of the single-phase differential converter. It occurs in the same phase at OP and ON. Therefore, in the differential output signal V _OP -V _ON , the in-phase noise is canceled out, and the contribution ratio of the noise by the additional current source I5 to the output noise is reduced. In particular, if it is set to R1 = R2, Z1 = Z2, additional current source I5 due to noise equals the output terminal OP, so generated to ON, the noise due to the additional current source differential output signal V _OP -V _ON is Completely offset.

The third point is that even if R1 = R2 and Z1 = Z2 are not set, or even if the attenuation characteristics of the filter by the impedance means Z1 and Z2 are unbalanced, the noise caused by the additional current source I5 Appears in the same phase at the output terminals OP and ON, so that noise due to the additional current source appearing in the differential output signal V _OP -V _ON is suppressed. As a result, the increase in output noise due to the additional current source is smaller than in the case of FIG.

  The control of the first output operating point will be described in detail below. As shown in FIG. 2, the single-phase differential converter 10 is provided with first and second impedance means Z1, Z2 between output terminals OP, ON. Therefore, when the impedances of the second impedance means Z1 and Z2 are equal, the DC currents I3 and I4 of the amplification transistors N1 and N2 are specific to the output load resistors R1 and R2 depending on the ratio of the resistance values R1 and R2. Flows in inverse proportion. Similarly, the current (minus current) of the additional current source I5 also flows to the output terminals OP and ON, specifically inversely proportional to the ratio of the resistance values R1 and R2. When these currents I3, I4 and additional current source I5 obtain DC currents I1, I2 flowing through output load resistors R1, R2 by superposition logic, the following equation (1) is obtained.

The voltage at the operating point, which is the DC component of the output voltages V _OP and V _ON , is a value obtained by multiplying the DC currents I 1 and I 2 of Equation (1) by the resistors R 1 and R 2 and subtracting from the power source VDD. ).

From this equation (2), it is clear that the operating point of the output voltage can be controlled if the additional current source I5 is variably controlled corresponding to the variable control of the DC currents I3 and I4 of the differential transistors N1 and N2. It is.

  Next, the noise attenuation effect by the second filter will be described. Consider the noise at the output terminal due to the additional current source I5 in FIG.

FIG. 3 is a diagram illustrating a noise model of the additional current source. For simplicity, only one side of the single-phase differential converter of FIG. 2 is modeled. The upper diagram of FIG. 3 is a model in which the additional current source I5 is connected to the output terminal OUT via the inductance L, and the input impedance of the model 30 of the additional current source I5 is assumed to be Rn. The lower part of FIG. 3 shows the noise of this additional current source modeled by a noise voltage source. Since the noise is random but its power can be regarded as constant, the model 32 shows the input impedance Rn and the noise voltage source power | Vnx | ² .

In the case of the model 32 in FIG. 3, when the output impedance of the output terminal OUT is Zout, the noise voltage V _{n, OUT} of the noise source appearing at the output terminal _OUT is the input impedance Rn, inductor L, and output impedance of the additional current source 32. Determined by the impedance ratio of Zout. That is, the average value of the power of the noise voltage V _{n, OUT} is as shown in the following equation (3).

In this case, since the inductance L at a desired frequency is large, the output impedance Zout can be approximated by the output load resistance Rout, and the average value of the power of the noise voltage V _{n, OUT} is expressed by the following equation (4).

According to the above equation (4), it can be seen that a low-pass filter LPF having a time constant L / (Rn + Rout) is formed. That is, noise generated by the additional current source appears at the output terminal OUT through the low-pass filter composed of Rn, L, and Rout. If the inductance L of the impedance means Z1 and Z2 has a high impedance at a desired frequency, the average value of the power of the noise voltage V _{n, OUT} at the output terminal OUT of Equation (4) becomes small, and the additional current source Noise can be attenuated.

  FIG. 4 is a diagram illustrating the noise voltage in the voltage source model and the noise current in the current source model. In the voltage source model, models in the case of the resistance element R and the case of the MOS transistor are shown, and the respective noise voltages are shown. The current source model also shows models for the resistor element R and the MOS transistor, and the respective noise currents are shown. Here, k is a Boltzmann constant, T is an absolute temperature, R is a resistance value, γ is a noise coefficient, and gm is a transconductance of the transistor.

Referring to FIG. 4, the power of the noise voltage V _{n, OUT} at the output terminal in the model of FIG. 3 in which the noise source 32 is connected to the output terminal OUT without passing through the inductance L (equivalent to FIG. 1). The average value is calculated as follows.

Here, the desired frequency is 2.5 GHz, the output load resistance Rout is 60Ω, the output impedance Rn of the current source is 50Ω (assuming N-channel MOS, gm = 20mS), the absolute temperature T is 290K, and the Boltzmann constant k is 1.38 × 10 ^-23 , the noise coefficient γ was set to 1.

Furthermore, when the average value of the power of the noise voltage V _{n, OUT} at the output terminal in the model of FIG. 3 is obtained by calculation according to Equation (4), the noise power is 0.785 × 10-19. However, inductance L is It was. That is, the noise at the output terminal caused by the additional current source is reduced by 67% compared to the model equivalent to FIG. This is due to the attenuation effect of the low-pass filter due to the inductance L of the impedance means Z1 and Z2.

  Next, the noise canceling effect by the third differential output will be described. FIG. 5 is a diagram illustrating the noise canceling effect of the additional current source. FIG. 5A is a circuit diagram showing a voltage model of an additional current source when an additional current source is provided at each of the output terminals OP and ON as shown in FIG. 1, and FIG. FIG. 6 is a circuit diagram showing an additional current source in a case where a common additional current source is provided for the output terminals OP and ON as shown in FIG. 2 using a voltage model and a current model.

In the model of FIG. 5A, the noises that appear at the output terminals OP and ON due to the respective additional current sources are noises that are not correlated with each other. Therefore, the noise appearing at the differential output V _OP -V _ON is the sum of the noises appearing at the respective output terminals OP, ON, as shown in the following equation (6).

On the other hand, in the model of FIG. 5 (B), noises appearing at the output terminals OP and ON due to the common additional current source are in phase. Therefore, the noise appearing at the differential output V _OP -V _ON is the difference between the noises appearing at the respective output terminals OP, ON. To determine the noise at the output terminal in the model of FIG. 5B, consider a circuit in which an additional current source I5, which is a noise signal source shown on the right side, is modeled with a current source. In this case, the noise current power | Inx | ² of the additional current source I5 is proportional to the admittance Y when the output terminals OP and ON are viewed from the additional current source I5 (inversely proportional to the impedance). Therefore, the power of the noise current generated at each output terminal OP, ON is expressed by the following equation (7).

From the above equation (7), the noise voltage power | V _{n, OP} | ² , | V _{n, OP} | ² of the output terminals OP and ON is obtained by multiplying the noise current by the output load resistors R1 and R2, respectively. The following equation (8).

The noise that appears in the differential output V _OP -V _ON is the difference of equation (8). Compared to the above equation (6), if the output load resistance is R1 = R2, the average noise power of the model in FIG. 5 (A) is 7.11 × 10 ^-19 ( V2 / Hz), the average noise power at each output terminal of the model of FIG. 5B is the same from equation (8), and the difference is almost zero. Each parameter was the same as described above. Even if R1> R2, even if R1> R2, the noise in the differential output becomes small because of the difference in in-phase noise in equation (7).

  The above point is that, in the model of FIG. 5B, even if the filter by the inductance L of the impedance means Z1 and Z2 has no attenuation characteristic, if the output load resistance is R1 = R2, the differential output VOP-VON This means that the noises generated in are canceled out and become zero. When the attenuation characteristics of the filter work, the noise appearing at each output terminal OP, ON is attenuated in the first place.

  Next, the noise reduction effect when the output load resistors R1 and R2 of the single-phase differential converter of this embodiment are not equal and the output impedances at the output terminals OP and ON are in an unbalanced state will be described.

  FIG. 6 is a diagram for explaining the noise reduction effect in a non-equilibrium state. First, a case where the frequency band is low and a case where the frequency band is high will be described based on the above equation (8). In equation (8), jω = s is replaced. Since any noise voltage has the second order in the denominator and the first order in the numerator, the transfer function as a whole has the frequency characteristics of the second order LPF.

  When the frequency band is low, since sL = 0, the power of the noise voltage appearing at both output terminals OP and ON becomes equal as shown in the following equation (9).

The meaning of this equation can be explained as follows. That is, when L = 0, the current (negative current) of the additional current source I5 flows to the output load resistance in inverse proportion to the resistance values of the output load resistances R1 and R2. On the other hand, the voltage at each output load resistor R1, R2 is obtained by multiplying the resistance value R1, R2 by the current value flowing in inverse proportion to the resistance value of R1, R2. Therefore, the voltages at both resistors R1 and R2 are equal. Therefore, the noise voltage in the differential signal V _OP -V _ON is canceled by the equal noise in the equation (9).

  On the other hand, when the frequency band is high, s = ∞, and in Equation (9), since the second-order s exists in the denominator, the power of the noise voltage appearing at both output terminals OP and ON becomes zero. That is, the noise current does not flow to the output terminals OP and ON due to the low-pass filter, but most of the noise current only flows through the resistor Rn in the additional current source.

As shown in FIG. 6, when the output load resistors R1 and R2 are not equal and R1> R2, the output impedance at the output terminals OP and ON is different, and the pole of the low-pass filter between the additional current source and the output terminal OP (Cut-off frequency f _cOP ) is lower than the pole of the low-pass filter (cut-off frequency f _cON ) between the additional current source and the output terminal ON. As a result, when the frequency is low, the noise appearing at both output terminals OP and ON is in phase and the noise voltage is equal, as described above, and the noise appearing at the differential output VOP-VON cancels each other and is reduced (cancelled). . On the other hand, when the frequency is high, the noise of the additional current source is reduced by the respective low-pass filters, and the noise is not generated at the output terminals OP and ON.

In the case of an intermediate frequency between the poles of both filters (cut-off frequencies f _cOP , f _cON ), noise that has not been completely attenuated by the filter appears at the output terminal OP, but attenuates at the output terminal ON. Noise appears instead. However, since both noises are in phase, the noise voltage of the differential output VOP-VON becomes the difference between these noise voltages, and is reduced accordingly. In other words, the noise cancellation effect is weakened by the difference in noise voltage.

  FIG. 7 is a configuration diagram of a wireless communication receiving circuit having the in-phase differential converter of the present embodiment. The in-phase differential converter 10 is provided as a low noise amplifier that amplifies a reception signal received by the antenna AT. Then, the differential output of the in-phase differential converter 10 is input to the reception signal processing circuit 40, and down-conversion, quadrature detection, demodulation, error correction, and the like are performed. Further, variable control of the gain of the in-phase differential converter 10 is performed by the control signal CONT from the reception signal processing circuit 40.

  FIG. 8 is a configuration diagram of the in-phase differential converter according to the present embodiment. As in the configuration diagram of FIG. 2, an additional current source I5 is provided at the output terminals OP and ON via impedance means Z1 and Z2. A control signal CONT for controlling the gain shown in FIG. 7 is supplied to the common-gate amplifier circuit 11 and the common-source amplifier circuit 12. Control of the gains of the amplifier circuits 11 and 12 by the control signal CONT includes a method for increasing and decreasing the number of transistors N1 and N2, and a method for increasing and decreasing the bias voltages Vb1 and Vb2. By configuring the transistors N1 and N2 with a plurality of parallel unit transistors and increasing the number of parallel unit transistors, the amount of current increases and the gain increases. Further, if the bias voltages Vb1 and Vb2 are increased, the driving capabilities of the transistors N1 and N2 are increased, the amount of current is increased, and the gain is increased.

Corresponding to the current increase / decrease in the amplification transistors N1, N2, the current amount of the additional current source I5 is also controlled to increase / decrease by the control signal CONT. As a result, the load current flowing through the output load resistors R1 and R2 can be made constant or suppressed, and fluctuations in the operating points of the output voltages V _OP and V _ON at the output terminals OP and ON are eliminated or suppressed. be able to.

  FIG. 9 is a configuration diagram of the in-phase differential converter according to the present embodiment. In FIG. 9, a P-channel MOS transistor P5 is provided as an additional current source I5. The other configuration is the same as that of FIG. In order to control the current value of the additional current source I5 by the transistor P5 by the control signal CONT, the current value can be increased or decreased by providing a plurality of unit transistors in parallel with the transistor P5 and increasing or decreasing the number thereof. Alternatively, the current amount can be increased by lowering the bias voltage Vb5 applied to the gate of the transistor P5, and the current amount can be decreased by increasing the bias voltage Vb5.

  FIG. 10 is a configuration diagram of the in-phase differential converter according to the present embodiment. In FIG. 10, impedance means Z1 and Z2 between the additional current source I5 and the output terminals OP and ON are circuits in which inductances L1 and L2 and capacitors C1 and C2 are respectively connected in parallel. The impedance means Z1 and Z2 may be only the inductances L1 and L2 as shown in FIG. In any circuit, the impedance means Z1 and Z2 have high impedance in the high frequency band and have a function of a low-pass filter that attenuates the high frequency signal.

FIG. 11 is a diagram illustrating a specific example of the in-phase differential converter. FIG. 11 shows an example (A) in which each of the two output terminals OP and ON in FIG. 1 is provided with another additional current source, and an additional current source common to the two output terminals OP and ON in FIG. An example (B) is shown. However, in the example of FIG. 11, the common-gate transistor is a cascode connection example including transistors N1-1 and N1-2, and the common-gate transistor N2-2 whose gate is biased is cascode-connected to the common-source transistor N2. This is an example. In this specific example, the noise current of the additional current source is 1.60 × 10 ^-23 (A ² / Hz) for both (A) and (B), and the additional current source I5 is a P-channel transistor (gm = 0.5 mS, noise coefficient γ = 2 ) And absolute temperature T = 290K. The data of each element is as shown in the figure. The output load resistance value is unbalanced at 100Ω and 600Ω.

For the above specific example, the circuit performance at a frequency of 2.5 GHz is shown in FIG. The S-parameters in examples (A) and (B) are the values shown in the figure, and this is a characteristic that can be used for the front-end amplifier of the wireless communication circuit. The output noise power of Example (A) and (B) is 3.93 × 10 ^-17 in Example (A) and 4.18 × 10 ^-18 in Example (B), and is reduced by about an order of magnitude in Example (B). ing. This is because the increase in output noise power due to the additional current source is smaller in Example (B). When the output load resistance values are equal, the output noise power in the example (B) is further reduced.

  As described above, the single-phase differential converter according to the present embodiment includes the common additional current source I5 at both output terminals OP and ON via high impedance means, so that the current of the transistor in the amplification stage increases or decreases. Even so, it is possible to control the fluctuation of the current flowing through the output load resistors R1 and R2 and to reduce the influence of noise generated by the additional current source itself on the output terminal.

  The above embodiment is summarized as follows.

(Appendix 1)
A first output load resistor and a first amplification transistor are provided between a power supply and a reference voltage, and a single-phase input signal is supplied to the first amplification transistor, and a first of the first output load resistors is provided. A non-inverting amplifier circuit in which a first output terminal is provided at a node on the amplifier transistor side,
A second output load resistor and a second amplification transistor are provided between the power source and a reference voltage, and the single-phase input signal is supplied to the second amplification transistor, and the second output load resistor An inverting amplifier circuit in which a second output terminal is provided at a node on the second amplifier transistor side;
Single-phase differential conversion having an additional current source provided in common through first and second impedance means having high impedance in the frequency band of the single-phase input signal at the first and second output terminals vessel.

(Appendix 2)
In Appendix 1,
The first and second impedance means are single-phase differential converters having an impedance higher than the first and second output load resistors in the frequency band.

(Appendix 3)
In Appendix 1 or 2,
The first and second impedance means are single phase differential converters which are either a circuit having an inductance element or a circuit in which an inductance element and a capacitance element are connected in parallel.

(Appendix 4)
In any of Supplementary Notes 1, 2, and 3,
The additional current source is a single phase differential converter having a current source transistor having a drain connected to the power source and a source connected to the first and second impedance means.

(Appendix 5)
In any of Supplementary Notes 1, 2, and 3,
A single-phase differential converter in which the amount of current of the additional current source is also variably controlled in accordance with variable control of the mutual conductance of the first and second amplification transistors.

(Appendix 6)
In Appendix 5,
The first and second amplification transistors each have a plurality of unit amplification transistors provided in parallel,
The additional current source has a plurality of unit current source transistors provided in parallel,
The variable control of the mutual conductance of the first and second amplification transistors is performed by variably controlling the number of the plurality of unit amplification transistors, and the variable control of the current amount of the additional current source is performed by the plurality of units. A single-phase differential converter performed by variably controlling the number of current source transistors.

(Appendix 7)
In Appendix 5,
The additional current source comprises a current source transistor;
The variable control of the mutual conductance of the first and second amplification transistors is performed by variably controlling the gate bias voltage of the first and second amplification transistors, and the variable control of the current amount of the additional current source is performed. A single-phase differential converter which is performed by variably controlling the gate bias voltage of the current source transistor.

(Appendix 8)
In any of Supplementary Notes 1, 2, and 3,
The first amplification transistor is a gate-grounded transistor, and the second amplification transistor is a source-grounded transistor.

(Appendix 9)
The single-phase differential converter according to any one of appendices 1 to 8,
A receiving antenna for providing a received signal to the single-phase differential converter;
A wireless communication circuit device comprising: a reception signal processing circuit that inputs a differential output of the single-phase differential converter.

R1, R2: First and second output load resistors N1, N2: Amplifier transistors
IN: Input terminal, input signal OP, ON: Output terminal
VOP, VON: Output voltage I5: Additional current source
Z1, Z2: Impedance means

Claims (5)

A first output load resistor and a first amplification transistor are provided between a power supply and a reference voltage, and a single-phase input signal is supplied to the first amplification transistor, and a first of the first output load resistors is provided. A non-inverting amplifier circuit in which a first output terminal is provided at a node on the amplifier transistor side,
A second output load resistor and a second amplification transistor are provided between the power source and a reference voltage, and the single-phase input signal is supplied to the second amplification transistor, and the second output load resistor An inverting amplifier circuit in which a second output terminal is provided at a node on the second amplifier transistor side;
Single-phase differential conversion having an additional current source provided in common through first and second impedance means having high impedance in the frequency band of the single-phase input signal at the first and second output terminals vessel. In claim 1,
The first and second impedance means are single-phase differential converters having an impedance higher than the first and second output load resistors in the frequency band. In claim 1 or 2,
The first and second impedance means are single phase differential converters which are either a circuit having an inductance element or a circuit in which an inductance element and a capacitance element are connected in parallel. In any one of claims 1, 2, and 3,
A single-phase differential converter in which the amount of current of the additional current source is also variably controlled in accordance with variable control of the mutual conductance of the first and second amplification transistors. A single-phase differential converter according to any one of claims 1 to 4,
A receiving antenna for providing a received signal to the single-phase differential converter;
A wireless communication circuit device comprising: a reception signal processing circuit that inputs a differential output of the single-phase differential converter.

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