JP5376151B2 - A / D converter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a high-accuracy A/D converter that adaptively calibrates characteristic variations among circuits of a plurality of A/D conversion circuits that operate in a time-interleaved manner and reduces a conversion error of the A/D converter as a whole, and a calibrating method thereof. <P>SOLUTION: The A/D converter includes: N (N is an integer of two or more) A/D conversion circuits for main signal which operate in a time-interleaved manner; one redundant A/D conversion circuit; a calibrating signal generator; and a calibrating control circuit for using a calibration signal from the calibrating signal generator to adjust and calibrate a parameter of the redundant A/D conversion circuit. The A/D conversion circuits for main signal A/D converts an input signal by an interleave operation, and the redundant A/D conversion circuit is calibrated by an adjustment signal from the calibrating control circuit. Further, any of the A/D conversion circuits for main signal is replaced by the redundant A/D conversion circuit, and the new A/D conversion circuit for main signal operates in a time-interleaved manner to calibrate the new redundant A/D conversion circuit. <P>COPYRIGHT: (C)2011,JPO&amp;INPIT

Description

  The present invention relates to an A / D converter that converts an analog signal into a digital signal. In particular, the present invention relates to a time-interleaved (time-interleaved) A / D conversion apparatus that performs analog-digital conversion in which a plurality of low-speed A / D conversion circuits are operated in parallel in a predetermined order, and calibration thereof.

  In recent years, the development of digital technology has been remarkable, and accordingly, there has been an increasing demand for higher speed and higher accuracy of A / D conversion devices that convert analog signals into digital signals. As one technique for realizing high-speed A / D conversion devices, a plurality of A / D conversion circuits that perform low-speed sampling operations are operated in a predetermined order so that the plurality of A / D conversion circuits as a whole There is a time interleaving method that equivalently realizes high-speed sampling. However, in an A / D conversion apparatus that performs processing by a plurality of A / D conversion circuits, error components (variation) such as gain and offset between the conversion circuits increase noise and distortion, and the A / D conversion apparatus as a whole There is a problem of deteriorating conversion accuracy.

  As means for calibrating the gain and offset error components between circuits, for example, there is a technique disclosed in Patent Document 1. The calibration method of Patent Document 1 includes means for generating a sine wave as a training signal for calibration, and uses this sine wave signal to sign a series of conversion data for each of a plurality of A / D conversion means. Curve fitting is performed to obtain calibration values such as gain and offset and store them in the calibration memory. During normal A / D conversion, the data is calibrated according to the calibration value stored in the calibration memory. However, in such a circuit configuration, for example, in order to cope with a change in circuit characteristics due to power supply fluctuation, use temperature change, aging change, etc., the normal A / D conversion process is temporarily stopped and the calibration is performed. It is not suitable for a device that needs to be provided with a period and whose accuracy needs to be continuously secured, such as a communication device. That is, for use in a communication device or the like, a means for adaptive calibration (in the background) is required without stopping the original A / D conversion operation.

  Further, as a method for adaptively calibrating an A / D conversion circuit that performs time interleave operation, for example, there is a technique disclosed in Patent Document 2. In Patent Document 2, a high-speed and coarse-precision A / D conversion circuit that operates at the same speed as the equivalent sampling speed obtained at the time interleaving is prepared separately from the A / D conversion circuit that performs the time interleaving operation. A means for correcting the output value of an A / D conversion circuit that performs time interleave operation by calculating a complement coefficient by adaptive signal processing using the output of the separately prepared A / D conversion circuit as a reference signal (teacher signal) is introduced. ing. However, one of the main reasons for adopting the interleave method is that the A / D converter circuit alone cannot achieve the desired high speed, and therefore the time interleave method is adopted. In many cases, it is difficult to realize a high-speed A / D conversion circuit that operates at the same speed as the equivalent sampling speed obtained during time interleaving. Even if it can be done, power consumption will increase significantly in order to achieve high-speed operation.

JP 2003-133554 A JP 2007-150640 A

  The present invention has been made in view of the above-described background, and an object of the present invention is to adaptively calibrate characteristic errors (characteristic variations) between a plurality of A / D conversion circuits that perform time interleave operation, and to perform A / D conversion. It is intended to reduce the conversion error of the entire apparatus and improve the accuracy. Furthermore, it is to provide means / method for realizing calibration of the A / D converter in the background while suppressing an increase in circuit scale and power consumption.

  According to one aspect of the present invention, N (N is an integer of 2 or more) main signal A / D conversion circuits that perform time interleaving operations, each of which converts to a digital signal at different sampling timings, and one redundancy An A / D conversion circuit, a calibration signal generator, and a calibration control circuit that adjusts and calibrates the parameters of the redundant A / D conversion circuit using a calibration signal generated from the calibration signal generator. The A / D conversion circuit for the main signal and the redundant A / D conversion circuit have substantially the same A / D conversion characteristics, and the A / D conversion circuit for the main signal performs a time interleaving operation to convert the input signal to A The redundant A / D conversion circuit is calibrated by an adjustment signal from the calibration control circuit, and one of the main signal A / D conversion circuits and the redundant A / D conversion circuit Replace , N main signal A / D conversion circuits and one redundant A / D conversion circuit are newly allocated, and the newly allocated main signal A / D conversion circuit performs time interleaving operation to convert the input signal to A / D. In addition to the conversion, the newly assigned redundant A / D conversion circuit is calibrated by the adjustment signal from the calibration control circuit, and this is sequentially repeated to calibrate all the A / D conversion circuits periodically or not. An A / D conversion device that performs periodically can be obtained.

  According to another aspect of the present invention, N (N is an integer of 2 or more) main signal A / D conversion circuits that perform time interleaving operations, each of which converts to a digital signal at different sampling timings, and one A redundant A / D conversion circuit, a calibration signal generator, and a calibration control circuit that adjusts and calibrates the parameters of the redundant A / D conversion circuit using a calibration signal generated from the calibration signal generator The main signal A / D conversion circuit and the redundant A / D conversion circuit have substantially the same A / D conversion characteristics, and the main signal A / D conversion circuit performs a time interleaving operation to receive an input signal. A first calibration step in which A / D conversion is performed and the redundant A / D conversion circuit is calibrated by an adjustment signal from the calibration control circuit; one of the main signal A / D conversion circuits; Redundant A / D The switching circuit is replaced, N main signal A / D conversion circuits and one redundant A / D conversion circuit are newly allocated, and the newly allocated main signal A / D conversion circuit performs time interleaving operation to input signals. A second calibration step in which the newly assigned redundant A / D conversion circuit is calibrated by the adjustment signal from the calibration control circuit, and the main signal in the first calibration step. And a third calibration step that repeats the second calibration step until all of the A / D conversion circuits assigned to the A / D conversion circuit are calibrated. .

  According to the present invention, an A / D converter capable of performing a calibration operation in the background while performing a time interleave operation as the A / D converter can be obtained. A plurality of low-speed A / D conversion circuits can be sequentially converted into digital signals at different sampling timings to increase the sampling speed equivalently. It is possible to adaptively calibrate the characteristic error (characteristic variation) between the circuits of each A / D conversion circuit, to reduce the conversion error of the entire A / D conversion apparatus, and to achieve high accuracy.

  Furthermore, since only one redundant A / D conversion circuit is added, the A / D conversion apparatus can be calibrated in the background while suppressing an increase in circuit scale and an increase in power consumption. In particular, an A / D conversion device having a large number of time interleaves such as an ultra-high-speed A / D conversion circuit has a smaller overhead ratio of the redundant A / D conversion circuit and its calibration circuit, and the effect of the present invention increases. .

1 is a block diagram showing the configuration of an A / D conversion device that explains the principle of the present invention. FIG. 2 is a timing chart diagram of a four-phase clock in FIG. 1. 1 is a configuration block diagram of an A / D conversion device in a first embodiment of the present invention. It is a timing chart figure which shows the connection state of each switch in this invention. It is another timing chart figure which shows the connection state of each switch in this invention. It is a block diagram of the configuration of the A / D converter in the second embodiment of the present invention.

(First embodiment)
As the first embodiment, the principle content of the time interleave type A / D converter of the present invention will be described. FIG. 1 shows a block diagram of the basic A / D converter of the present invention, and FIG. 2 shows a timing chart of four-phase clocks (CLK1 to CLK4) in the time interleaved A / D converter.

  The A / D converter shown in FIG. 1 includes N + 1 (N is an integer of 2 or more) low-speed A / D converter circuits, a digital processing unit, a calibration signal generator, a calibration control circuit, and each A It is composed of a switch group for switching input / output signals to / from the / D conversion circuit. In FIG. 1 of the present invention, the number of A / D conversion circuits performing time interleaving operation is shown as N = 4, but the number (N) of A / D conversion circuits performing time interleaving operation is particularly limited. It is not a thing.

  In FIG. 1, assuming that N = 4, a total of five low-speed A / D converters including four A / D conversion circuits 101 to 104 that perform time interleaving operation and one redundant A / D conversion circuit 105 that performs further calibration operation. 1 shows a time-interleaved A / D converter equipped with a D converter. The digital processing unit 200 bundles the A / D conversion outputs 151 to 154 from the A / D conversion circuits in the time interleave operation, and outputs the A / D conversion output 150 as one A / D conversion result. The calibration signal generator 300 generates a calibration signal 301 for calibration and outputs it to the redundant A / D conversion circuit 105 for calibration operation. The redundant A / D conversion circuit 105 samples the known calibration signal 301 and passes the A / D conversion output 155 to the calibration control circuit 400.

  The calibration control circuit 400 compares the known calibration signal 301 with the A / D conversion output 155. Here, for example, the calibration control circuit 400 stores digital data obtained by correctly converting the known calibration signal 301, and compares the stored digital data of the calibration signal 301 with the A / D conversion output 155. You just have to do it. Each adjustment parameter (for example, gain, offset, band) of the redundant A / D conversion circuit 105 for calibration operation is adjusted so that the error between the two compared is minimized, and an adjustment signal for calibrating with high accuracy is redundant A. Output to / D conversion circuit.

  The switch switches input / output signals and control signals to each of the A / D conversion circuits 101 to 105, and assigns each A / D conversion circuit for time interleave operation or calibration operation. The input signal switches 111 to 115 are input signal switches that are switched to the input signal 100 or the calibration signal 301 as inputs to the A / D conversion circuits 101 to 105. The output signal switches 121 to 125 are output signal switches that switch and output the outputs from the A / D conversion circuits 101 to 105 to the digital processing unit 200 or the calibration control circuit 400. The clock switches 131 to 135 switch and input one of the four-phase clocks (CLK1 to CLK4) as a clock to each of the A / D conversion circuits 101 to 105. The adjustment signal switches 141 to 145 are connected to output the adjustment signal from the calibration control circuit 400 to the redundant A / D conversion circuit for the calibration operation, and are not output to the A / D conversion circuit for the time interleave operation. It is a signal switch that switches to unconnected (open).

  First, as shown in FIG. 1, the A / D conversion circuits 101 to 104 are assigned as A / D conversion circuits that perform an interleave operation, and the A / D conversion circuit 105 is assigned as a redundant A / D conversion circuit that performs a calibration operation. The input signal switch, output signal switch, clock switch, and adjustment signal switch of the A / D conversion circuits 101 to 104 that perform the interleave operation are connected as follows. The input signal switches 111 to 114 are connected to the input signal 100 side. The output signal switches 121 to 124 are connected to the digital processing unit 200 side. The clock switches 131 to 134 are sequentially connected to the CLK1, CLK2, CLK3, and CLK4 sides of the four-phase clock. The adjustment signal switches 141 to 144 are not connected and are open.

  The input signal switch, the output signal switch, the clock switch, and the adjustment signal switch of the A / D conversion circuit 105 assigned as the redundant A / D conversion circuit that performs the calibration operation are connected as follows. The input signal switch 115 is connected to the calibration signal 301 side. The output signal switch 125 is connected to the calibration control circuit 400 side. The clock switch 135 is connected to the CLK1 side of the four-phase clock. The adjustment signal switch 145 connects the adjustment output 165 from the calibration control circuit 400 to the A / D conversion circuit 105.

  The A / D conversion circuits 101 to 104 are connected to the input signal 100 and the digital processing unit 200 by the above connection of the switches, and perform an interleave operation with four-phase clocks (CLK1 to CLK4) having different phases. As the four-phase clocks (CLK1 to CLK4), clocks having different phases by 90 degrees can be used as shown in FIG. Then, the A / D conversion outputs 151 to 154 can be bundled by the digital processing unit 200 so that the four A / D conversion circuits as a whole can be operated as a time interleaved A / D conversion device having a fourfold sampling frequency.

  However, at this stage, the A / D conversion circuits 101 to 104 have different characteristics as A / D conversion circuits such as gain, offset, and bandwidth due to circuit variations at the time of LSI manufacture. Not only the accuracy as a single unit is not guaranteed, but also the accuracy of the entire time interleaved A / D converter is deteriorated.

  On the other hand, the redundant A / D conversion circuit 105 that performs the calibration operation is connected to the calibration signal generator 300 and the calibration control circuit 400. The redundant A / D conversion circuit 105 samples the known calibration signal 301 generated from the calibration signal generator 300 instead of sampling the input signal, and uses the conversion result as an A / D conversion output 155 for the calibration control circuit. Pass to 400. The calibration control circuit 400 compares the data of the known calibration signal 301 with the A / D converted A / D conversion output 155, and outputs an adjustment signal 165 so that the error is minimized. The A / D conversion circuit 105 can adjust each adjustment parameter (for example, gain, offset, band) of the A / D conversion circuit 105 by the adjustment signal 165 and calibrate with high accuracy. The A / D conversion circuit 105 holds the calibrated state.

  Next, the A / D conversion circuit 101 that is time-interleaved is assigned as a redundant A / D conversion circuit, and the calibrated A / D conversion circuit 105 is assigned as an A / D conversion circuit that is time-interleaved. Switch the connection with.

  The input signal switch, output signal switch, clock switch, and adjustment signal switch of the A / D conversion circuit 101 newly assigned to the redundant A / D conversion circuit are switched and connected as follows. The input signal switch 111 is connected to the calibration signal 301 side. The output signal switch 121 is connected to the calibration control circuit 400 side. The clock switch 131 delays the phase of the clock and is connected to the CLK2 side of the four-phase clock. The adjustment signal switch 141 connects the adjustment output 161 from the calibration control circuit 400 to the A / D conversion circuit 101.

  The input signal switch, output signal switch, clock switch and adjustment signal switch of the A / D conversion circuit 105 newly assigned to the A / D conversion circuit for time interleaving operation are switched and connected as follows. The input signal switch 115 is connected to the input signal 100 side. The output signal switch 125 is connected to the digital processing unit 200 side. The clock switch 135 remains connected to the CLK1 side of the four-phase clock. The adjustment signal switch 145 is not connected and is open.

  As described above, the input / output of the A / D conversion circuit is switched by the switch, and the A / D conversion circuits 102 to 105 that perform the time interleave operation, the redundant A / D conversion circuit 101 that performs the calibration operation, and the respective A / D conversion circuits are assigned. . The A / D conversion circuits 102 to 105 perform a time interleave operation, and the A / D conversion circuit 101 performs a calibration operation. Then, this time, the A / D conversion circuit 101 becomes a redundant A / D conversion circuit, and in the same manner as the A / D conversion circuit 105 described above, the A / D conversion circuit 101 uses the calibration signal from the calibration signal generator and the calibration control circuit. The conversion circuit 101 is calibrated. The A / D conversion circuit 101 holds the calibrated state.

  Then, this time, the A / D conversion circuit 102 that is time-interleaved is assigned as a redundant A / D conversion circuit, and the calibrated A / D conversion circuit 101 is assigned as an A / D conversion circuit that is time-interleaved. Switch the input / output connection with a switch.

  The switch of the A / D conversion circuit 102 assigned to the redundant A / D conversion circuit is switched. The input signal switch 112 is connected to the calibration signal 301 side. The output signal switch 122 is connected to the calibration control circuit 400 side. The clock switch 132 delays the phase of the clock and is connected to the CLK3 side of the four-phase clock. The adjustment signal switch 142 connects the adjustment output 161 from the calibration control circuit 400 to the A / D conversion circuit 101.

  The switches of the A / D conversion circuit 101 assigned to the A / D conversion circuit for time interleave operation are connected as follows. The input signal switch 111 is connected to the input signal 100 side. The output signal switch 121 is connected to the digital processing unit 200 side. The clock switch 131 is directly connected to the CLK2 side of the four-phase clock. The adjustment signal switch 141 is not connected and is open.

  As described above, the A / D conversion circuits 101 and 103 to 105 for switching the input / output of the A / D conversion circuit by the switch and performing the time interleave operation, the redundant A / D conversion circuit 102 for performing the calibration operation, and the respective A / D conversion circuits. Is assigned. Then, this time, the A / D conversion circuit 102 becomes a redundant A / D conversion circuit, and the A / D conversion circuit 102 is calibrated using the calibration signal from the calibration signal generator and the calibration control circuit in the same manner as described above. By repeating this, the A / D conversion circuit 103, the A / D conversion circuit 104, and the five A / D conversion circuits are sequentially calibrated. Each calibrated A / D conversion circuit maintains its calibrated state until it is calibrated by the adjustment signal next time.

  As described above, the plurality of A / D conversion circuits are freely assigned to the A / D conversion circuit that performs the time interleave operation by switching the connection switch and the redundant A / D conversion circuit that performs the calibration operation. Therefore, it is desirable to design and arrange the plurality of A / D conversion circuits so as to be A / D conversion circuits having the same A / D conversion characteristics or substantially the same A / D characteristics. Here, the same characteristic or substantially the same characteristic means that for one input analog signal value, the digital conversion signals output from the respective A / D conversion circuits have the same digital signal value, and It means that the value is the same as the normal known value. That is, it has a characteristic of outputting the same digital signal value to an analog signal within a certain voltage value.

  As described above, according to the present invention, it is possible to calibrate the five A / D conversion circuits in the background without stopping the A / D conversion operation of the input signal, and the characteristic deterioration due to the LSI manufacturing variation or the like. An improved and highly accurate time interleaved A / D converter can be obtained. Further, according to the present invention, in an apparatus in which accuracy represented by communication equipment needs to be continuously secured, it is always in the background against fluctuations such as power supply fluctuations, temperature fluctuations, and aging deterioration. Since calibration is possible, a highly accurate A / D conversion device can be obtained.

(First embodiment)
Next, specific embodiments of the present invention will be described in detail with reference to the drawings. FIG. 3 is a block diagram showing the configuration of the A / D converter according to the first embodiment of the present invention. 4 and 5 show examples of timing charts of connection states of the switches of the A / D conversion circuit according to the present invention. Here, the configuration of the A / D converter shown in FIG. 3 is the same as the configuration of the A / D converter shown in FIG. 1 and the four-phase clock to be used. Is more concrete. Therefore, the A / D conversion device shown in FIG. 3 uses the same reference numerals as those in the configuration block diagram of the A / D conversion device of FIG. 4 and 5 show the operation state of each A / D conversion circuit and the connection state of each switch. Each interval of the timing charts shown in FIGS. 4 and 5 shows the time interleave operation state as a solid line and the calibration operation state as a broken line. Further, each interval of the timing chart is not particularly limited, and can be arbitrarily set.

  Input / output of the A / D conversion circuits 101 to 105 is switched by input signal switches 111 to 115, output signal switches 121 to 125, clock switches 131 to 135, and adjustment signal switches 141 to 145, and the time interleave operation state (A). Alternatively, the calibration operation state (B) is entered. The input signal switches 111 to 115 are connected to the input signal 100 side in the time interleave operation state and to the calibration signal 301 side in the calibration operation state. The output signal switches 121 to 125 are connected to the digital processing unit 200 side in the time interleave operation state and to the calibration control circuit 400 side in the calibration operation state. The clock switches 131 to 135 select the four-phase clocks CLK1 to CLK4, and advance the clock phase when switched to the calibration operation state. In the time interleave operation state, the clock phase is kept as it is, the calibrated clock is used, the calibration state is held, and A / D conversion is performed. The adjustment signal switches 141 to 145 are open (not connected: open) in the time interleave operation state, and are connected to the calibration control circuit 400 side in the calibration operation state, and calibrate the A / D conversion circuit by the adjustment signal.

  In the first example, as in the above-described embodiment, in the first interval, the A / D conversion circuits 101 to 104 are A / D conversion circuits for time interleave operation, and the A / D conversion circuit 105 is for calibration operation. The redundant A / D conversion circuit is assigned. In the next interval, the A / D conversion circuit 101 is assigned to the redundant A / D conversion circuit for calibration operation, and the remaining A / D conversion circuits 102 to 105 are used for time interleaving operation. In this way, the redundant A / D conversion circuits are sequentially switched from A / D conversion circuit 105 → 101 → 102 → 103 → 104, and all five A / D conversion circuits are calibrated. A time-interleaved A / D conversion apparatus can be configured by using all calibrated A / D conversion circuits.

  First, switch connection states in the A / D conversion circuits 101 to 104 that perform time interleaving will be described. The input signal switches 111 to 114 are connected to the input signal 100 side, the output signal switches 121 to 124 are connected to the digital processing unit 200 side, and the clock switches 131 to 134 are connected to CLK1, CLK2, CLK3, and CLK4, respectively. 144 is open. By these connections, the A / D conversion circuits 101 to 104 operate in a time interleave manner, and the A / D conversion of the input signal 100 constitutes an A / D conversion device having a sampling frequency four times the clock frequency as a whole. To do.

  Next, the switch connection state in the redundant A / D conversion circuit 105 for calibration operation will be described. The input signal switch 105 is connected to the calibration signal 301 side of the adjustment signal generator, the output signal switch 125 and the adjustment signal switch 145 are connected to the calibration control circuit 400 side, the clock switch 135 is connected to CLK1, and the A / D conversion circuit 105 is connected. Are operated as redundant A / D conversion. A sine wave generator is used as the calibration signal generator 300 to generate a known sine wave and send it to the A / D conversion circuit 105 as a calibration signal 301. The A / D conversion circuit 105 samples the calibration signal 301 at the timing of CLK1, performs A / D conversion, and transfers the result to the calibration control circuit 400 as an A / D conversion output 155.

  The calibration control circuit 400 receives the A / D conversion output 155 from the A / D conversion circuit 105, and performs fast Fourier transform (FFT) to divide it into a frequency component and a distortion component of the calibration signal 301, and generates all harmonics. The distortion characteristics of the A / D conversion circuit 105 typified by distortion rate (THD) or spurious free dynamic range (SFDR) are obtained. Then, the calibration control circuit 400 adjusts the parameters (for example, gain, offset, band, etc.) of the A / D conversion circuit 105 so that the distortion characteristic is minimized (best), and the A / D conversion circuit 105 is adjusted. Calibrate.

  There are several methods as these calibration methods. For example, the calibration control circuit 400 records and saves the standard digital conversion data of the calibration signal 301 and the parameter calibration method for the difference between the standard digital conversion data in advance in order to adjust the parameters of the A / D conversion circuit. Yes. The standard digital conversion data and the A / D conversion output 155 are compared, and the parameter of the A / D conversion circuit 105 can be calibrated using a parameter calibration method for the difference between the two. If the calibration signal 301 is a sine wave and the frequency is a known single frequency, the parameters of the A / D conversion circuit 105 can be calibrated using the frequency spectrum.

  As described above, the A / D conversion circuits 101 to 104 perform time interleave operation, and the A / D conversion circuit 105 is calibrated in the background. The A / D conversion circuit 105 holds this calibrated state until the next calibration.

  In the next interval, the A / D conversion circuit 105 and the A / D conversion circuit 101 are exchanged, and the A / D conversion circuit 101 is calibrated to an A / D conversion circuit that performs a time interleave operation. Assigned to redundant A / D conversion circuit. For the A / D conversion circuit 101, the input signal switch 111 is directed to the calibration signal 301 from the calibration signal generator, the output signal switch 121 and the adjustment signal switch 141 are directed to the calibration control circuit 400, and the clock switch 131 is CLK2. Switch to. For the A / D conversion circuit 105, the input signal switch 115 is switched to the input signal 100 side, the output signal switch 125 is switched to the digital processing unit 200 side, and the adjustment signal switch 145 is switched to open.

  By switching these switches, the A / D conversion circuit 101 becomes a redundant A / D conversion circuit, and the A / D conversion circuit 105 becomes an A / D conversion circuit that performs a time interleave operation. The A / D conversion circuits 102, 103, 104, and 105 perform a time interleave operation, and the A / D conversion operation of the input signal 100 is continuously performed. In the background, the calibration operation of the A / D conversion circuit 101 is performed. By repeatedly performing such an A / D conversion circuit switching operation, the A / D conversion assigned to each redundant A / D conversion circuit is continued in the background while continuing the A / D conversion operation of the input signal. The circuit can be calibrated. Thus, as shown in the timing chart of FIG. 4, five A / D conversion circuits can be calibrated at five intervals.

  If the A / D conversion circuit that is time-interleaved with the redundant A / D conversion circuit cannot be replaced instantaneously, the time interleaving period may be included in a part of the calibration operation period. FIG. 5 shows the timing chart. As a result, the two A / D conversion circuits can be exchanged smoothly without interrupting the conversion operation of the input signal.

  In the timing chart shown in FIG. 5, the switch switching timing of the A / D conversion circuit is partially different from that in FIG. The redundant A / D conversion circuit for the calibration operation switches the input signal switch and the adjustment signal switch to the connection for the time interleave operation at the time when the calibration operation is completed during the calibration period. After the time T1, each switch is switched so that one A / D conversion circuit for time interleave operation becomes a redundant A / D conversion circuit for calibration operation. At the same time, the remaining output signal switch and clock switch of the redundant A / D conversion circuit for calibration operation are switched to the connection for time interleave operation.

  The redundant A / D conversion circuit during the calibration operation is switched to the input signal 100 side and the adjustment signal switch is opened at time T1 before switching to the time interleave operation, and the A / D of the input signal 100 is switched to the open state. Start conversion. As described above, the A / D conversion circuit that is switched from the calibration operation to the time interleave operation is switched in advance to prepare for the time interleave operation. Therefore, the correct A / D conversion output of the input signal 100 can be instantaneously output at the timing when the assignment of the A / D conversion circuit is changed.

  The A / D conversion operation of the A / D conversion device needs to be continued without interruption even immediately. However, the calibration operation performed as the background of the A / D conversion operation can be interrupted by holding the calibration state after being calibrated once. Therefore, in the timing chart of FIG. 5, in the second half of the calibration period in which the calibration operation is completed, the input signal is switched to the A / D conversion operation and the instantaneous A / D conversion circuit can be replaced. . Since other operations are the same as those in FIG. 4 and can be understood, description thereof is omitted. Thus, also in the timing chart shown in FIG. 5, all the A / D conversion circuits can be calibrated by sequentially assigning them as redundant A / D conversion circuits for calibration operation.

  The A / D conversion apparatus according to the present embodiment includes N (N is 4 in this embodiment) main signal A / D conversion circuits that perform time interleaving operation, and one redundant A / D conversion circuit. . The main signal A / D conversion circuit performs time interleaving operation to A / D convert the input signal, and in the background, the redundant A / D conversion circuit is calibrated by the adjustment signal from the calibration control circuit. Further, any one of the main signal A / D conversion circuits and the redundant A / D conversion circuit are switched, and the allocation of the A / D conversion circuit is switched. The newly assigned N main signal A / D conversion circuits perform time interleaving operation to A / D convert the input signal, and the newly assigned redundant A / D conversion circuit is calibrated. This can be repeated sequentially to calibrate all of the A / D conversion circuits. If all the A / D conversion circuits are calibrated, as a result, the accuracy of the entire A / D conversion device that performs time interleaving operation is calibrated, and a high-speed and high-precision A / D conversion device can be realized. .

  In addition, since only one redundant A / D conversion circuit is added, the circuit area and power consumption of the A / D conversion apparatus as a whole will not be extremely increased. In particular, an A / D conversion device having a large number of time interleaves such as an ultra-high-speed A / D conversion circuit has a smaller overhead ratio of the redundant A / D conversion circuit and its calibration circuit, and the effect of the present invention is increased. In the description of this drawing, the number of time interleaves is 4 for the sake of simplicity, but the configuration of the present invention is not limited to N = 4.

  The calibration operation does not need to be performed at all times, and can be performed as needed. The period (interval) for switching each A / D conversion circuit may be either regular or irregular. The order of switching circuits is not particularly limited (rotation may be used or random switching may be used). Furthermore, the redundant A / D conversion circuit, the calibration signal generator, and the calibration control circuit can be electrically separated from the power source when not operating, thereby suppressing power consumption.

(Second embodiment)
Next, a second embodiment will be described in detail with reference to the drawings. FIG. 6 is a block diagram showing the configuration of the A / D conversion apparatus according to the second embodiment of the present invention. The A / D converter shown in FIG. 6 differs from the A / D converter shown in FIGS. 1 and 3 in the specific circuit configuration that constitutes the calibration signal generator 300 and the calibration control circuit 400. However, the purpose is the same, and the same symbols are used as the same components. Also in the second embodiment, as in the first embodiment, the A / D conversion is performed according to the four-phase clock in FIG. 2 and the timing charts in FIGS. 4 and 5 and assigned for the time interleave operation and the calibration operation. It is assumed that the circuit order is also the same.

  The A / D conversion apparatus shown in FIG. 6 is configured as a calibration signal generator 300 from a D / A conversion circuit with higher accuracy than the A / D conversion circuits 101 to 105. The digital calibration signal 302 is input to the high-precision D / A conversion circuit, and the analog calibration signal 301 obtained by D / A conversion is output to the redundant A / D conversion circuit 105. Since this D / A conversion circuit is highly accurate, the accuracy of the analog calibration signal 301 is high, the accuracy of the digital conversion output 155 from the redundant A / D conversion circuit is also high, and the calibration operation can be performed more accurately. Become.

  In the first embodiment, a sine wave is used as the calibration signal. In the second embodiment, the D / A conversion circuit is used to generate the analog conversion calibration signal 301 of the digital calibration signal 302 and the digital calibration signal. 302 is directly input to the calibration control circuit 400 as a reference signal for comparison. Therefore, the calibration control circuit 400 does not need the standard digital conversion data of the calibration signal 301, and does not need to store the known standard digital conversion data in advance. Therefore, a free signal pattern can be adopted as the calibration signal. Thus, when a D / A conversion circuit is used as the calibration signal generator 300 (depending on the performance of the D / A conversion circuit), a more actual signal such as a pseudo random bit string (PRBS) pattern is used. By calibrating using a signal similar to, it is possible to perform calibration with higher accuracy than calibration with a single sine wave.

  The calibration control circuit 400 receives the digital calibration signal 302 as a reference signal and the A / D conversion output 155 converted by the redundant A / D conversion circuit 105. In the calibration control circuit 400, the input digital calibration signal 302 is compared with the A / D conversion output 155, and the difference is detected. The calibration control circuit 400 stores and saves a database of parameter calibration methods for adjusting the parameters of the A / D conversion circuit, and compares the digital calibration signal 302 with the A / D conversion output 155, The parameters of the redundant A / D conversion circuit are adjusted so that the difference is minimized. Therefore, the calibration control circuit 400 does not need to perform complicated calculations such as FFT, and only stores a parameter calibration method database.

  The second embodiment is different from the first embodiment only in the calibration signal generator 300 and the calibration control circuit 400, and the operations of the different parts are as described above. As in the first embodiment, other operations are performed by connecting switches and assigning A / D conversion circuits for time interleave operation and calibration operation. Redundant A / D conversion circuits for calibration operation can be assigned sequentially, and all A / D conversion circuits can be calibrated. Since these operations are the same as those in the first embodiment, the description thereof is omitted.

  According to this embodiment, a D / A conversion circuit is used as a calibration signal generator, and the calibration control circuit receives an adjustment signal by receiving a digital calibration signal and an output signal from the redundant A / D conversion circuit. The redundant A / D conversion circuit can be generated and calibrated. In this way, an A / D conversion device capable of performing a calibration operation in the background while performing a time interleave operation as the A / D conversion device is obtained.

  The A / D conversion device of the present invention includes N main signal A / D conversion circuits that perform time interleave operation, and one redundant A / D conversion circuit. The main signal A / D conversion circuit performs time interleaving operation to A / D convert the input signal, and in the background, the redundant A / D conversion circuit is calibrated by the adjustment signal from the calibration control circuit. Further, any one of the main signal A / D conversion circuits and the redundant A / D conversion circuit are switched, and the allocation of the A / D conversion circuit is switched. The newly assigned N main signal A / D conversion circuits perform time interleaving operation to A / D convert the input signal, and the newly assigned redundant A / D conversion circuit is calibrated. This can be repeated sequentially to calibrate all of the A / D conversion circuits. If all the A / D conversion circuits are calibrated, as a result, the accuracy of the entire A / D conversion device that performs time interleaving operation is calibrated, and a high-speed and high-precision A / D conversion device can be realized. .

  According to the present invention, an A / D converter capable of performing a calibration operation in the background while performing a time interleave operation as the A / D converter can be obtained. A plurality of low-speed A / D conversion circuits can be sequentially converted into digital signals at different sampling timings to increase the sampling speed equivalently. It is possible to adaptively calibrate the characteristic error (characteristic variation) between the circuits of each A / D conversion circuit, to reduce the conversion error of the entire A / D conversion apparatus, and to achieve high accuracy.

  As mentioned above, although this invention was demonstrated as embodiment and an Example, this invention is not limited to said embodiment. Various changes can be made to the configuration and details of the present invention within the scope of the present invention.

100 Input signal 101, 102, 103, 104, 105 A / D converter circuit 111, 112, 113, 114, 115 Input signal switch 121, 122, 123, 124, 125 Output signal switch 131, 132, 133, 134, 135 Clock switch 141, 142, 143, 144, 145 Adjustment signal switch 150, 151, 152, 153, 154, 155 A / D conversion output 161, 162, 163, 164, 165 Adjustment signal 200 Digital processing unit 300 Signal generation for calibration 301 Calibration signal 302 Digital calibration signal 400 Calibration control circuit

Claims (9)

N (N is an integer greater than or equal to 2) main signal A / D conversion circuits, one redundant A / D conversion circuit, and a calibration signal, each of which performs a time interleaving operation for conversion into a digital signal at different sampling timing A generator and a calibration control circuit that adjusts and calibrates the parameters of the redundant A / D conversion circuit using a calibration signal generated from the calibration signal generator;
The main signal A / D conversion circuit and the redundant A / D conversion circuit have substantially the same A / D conversion characteristics, and the main signal A / D conversion circuit performs a time interleave operation so that the input signal is converted into an A / D The redundant A / D conversion circuit is calibrated by an adjustment signal from the calibration control circuit, and any one of the main signal A / D conversion circuits and the redundant A / D conversion circuit are connected. The N main signal A / D conversion circuits and one redundant A / D conversion circuit are newly allocated, and the newly allocated main signal A / D conversion circuit performs a time interleaving operation to convert the input signal to A / D. In addition to the D conversion, the newly allocated redundant A / D conversion circuit is calibrated by the adjustment signal from the calibration control circuit, and this is sequentially repeated to calibrate all the A / D conversion circuits periodically. Ku is A / D converting device, which comprises carrying out irregularly.   The calibration signal generator is a sine wave generator, and the calibration control circuit detects distortion by performing a fast Fourier transform (FFT) on the output result of the redundant A / D conversion circuit, and the redundant A / D conversion circuit. 2. The A / D converter according to claim 1, wherein the redundant A / D converter circuit is calibrated so that distortion characteristics are minimized.   The calibration signal generator is composed of a D / A conversion circuit with higher accuracy than the main signal A / D conversion circuit and the redundant A / D conversion circuit, and the calibration control circuit is an input of the D / A conversion circuit. 2. The digital calibration signal as described above and a digital conversion output from a redundant A / D conversion circuit are compared, and the redundant A / D conversion circuit is calibrated so that a difference between the two is minimized. A / D converter.   4. The A / D according to claim 2, wherein a gain, an offset, and a band are used as adjustment parameters for calibrating the main signal A / D conversion circuit and the redundant A / D conversion circuit. Conversion device.   5. The redundant A / D conversion circuit, the calibration signal generator, and the calibration control circuit are electrically separated from a power source when not operating. A / D converter. N (N is an integer greater than or equal to 2) main signal A / D conversion circuits, one redundant A / D conversion circuit, and a calibration signal, each of which performs a time interleaving operation for conversion into a digital signal at different sampling timings A generator and a calibration control circuit that adjusts and calibrates the parameters of the redundant A / D conversion circuit using a calibration signal generated from the calibration signal generator;
The main signal A / D conversion circuit and the redundant A / D conversion circuit have substantially the same A / D conversion characteristics, and the main signal A / D conversion circuit performs a time interleave operation so that the input signal is converted into an A / D conversion signal. A first calibration step in which the redundant A / D conversion circuit is calibrated by an adjustment signal from the calibration control circuit, as well as D conversion;
Replacing one of the main signal A / D conversion circuits and the redundant A / D conversion circuit, and newly assigning N main signal A / D conversion circuits and one redundant A / D conversion circuit, The newly assigned main signal A / D converter circuit performs time interleaving operation to A / D convert the input signal, and the newly assigned redundant A / D converter circuit is calibrated by the adjustment signal from the calibration control circuit. A second calibration step,
And a third calibration step that repeats the second calibration step until all of the A / D conversion circuits assigned to the main signal A / D conversion circuit are calibrated in the first calibration step. A method for calibrating an A / D conversion device.   7. The A / D converter calibration method according to claim 6, wherein the first, second, and third calibration steps are performed periodically or irregularly.   The replacement of one of the main signal A / D conversion circuits and the redundant A / D conversion circuit in the first, second, and third calibration steps is performed simultaneously. A method for calibrating an A / D converter according to claim 7.   The replacement of any one of the main signal A / D conversion circuits and the redundant A / D conversion circuit in the first, second, and third calibration steps is performed by the A / D assigned to the redundant A / D conversion circuit. 8. An input signal switch and an adjustment signal switch of the D conversion circuit are first switched, and then the remaining switching switches are switched at the same time so that the replacement is performed. A method for calibrating an A / D conversion device according to claim 1.

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