JP5383464B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

The present invention relates to a method of manufacturing a semi-conductor device and its.

  The demand for high performance and miniaturization of electronic application equipment typified by information communication equipment such as portable information equipment and small electronic equipment has increased. As a high-density mounting technology that connects semiconductor elements and electronic equipment, wafer level Package and chip size package technologies are attracting attention. In other words, a semiconductor wafer having a semiconductor integrated circuit is divided into individual wafer level packages (WLP) technology for packaging a semiconductor wafer in the form of a wafer by forming a redistribution layer or the like on the upper surface and the package of the semiconductor chip. Chip size package (CSP) technology has been developed and used. However, several problems have occurred with respect to the manufacturing technology of CSP that separates WLP. For example, there has been a problem related to dicing when obtaining a CSP that is singulated. When the WLP in which the semiconductor wafer is packaged is cut and separated, the semiconductor integrated circuit and the insulating layer or wiring in the rewiring layer stacked thereon are exposed in the cut and separated cross section. In some cases, problems such as adhesion of CSP to the CSP, separation of the surface of the semiconductor integrated circuit and the rewiring layer, or penetration of moisture into each layer may occur. In order to protect the CSP side surface and the like, conventionally, a method of sealing an insulating resin on the side surface of a semiconductor chip has been performed. By forming the rewiring layer, the pitch of the external connection terminals can be made larger than the pitch of the electrode pads on the semiconductor integrated circuit.

  FIG. 1 is a diagram illustrating the steps of a conventional CSP manufacturing method. FIG. 2 is a plan view illustrating a conventional semiconductor wafer. The diameter of a semiconductor wafer is generally referred to as “inch”, and wafers such as 6, 8, and 12 inches are used. 3A to 3D show typical states in the process (FIG. 1) of the conventional CSP manufacturing method, that is, the first insulating layer forming process (P1002), the WLP half dicing process (P1003), It is a figure which illustrates the state of a 2nd insulating layer formation process (P1004) and a CSP piece separation process (P1006). Each of the drawings (a) to (d) shows a cross section at a position corresponding to the cutting line XX of the semiconductor wafer of FIG.

  The outline of each process of the manufacturing method in FIG. 1 is as follows.

(P1001. Connection electrode forming step)
A connection electrode in which one end face of the columnar electrode (17 in FIG. 3A) is connected to the electrode pad on the semiconductor integrated circuit and the other end face is connected to the external connection terminal is formed by plating or the like. It is a process to do.

(P1002. First insulating layer forming step)
FIG. 3A shows a state in which a first insulating layer 12 is formed on a semiconductor wafer 10 having a plurality of semiconductor chips 11 using a sealing resin. The plurality of semiconductor chips 11 include a semiconductor integrated circuit 14 having electrode pads 13, and are provided adjacent to the semiconductor wafer 10. A connection electrode 17 is connected to the electrode pad 13. The electrode pad 13, the connection electrode 17, and the protective film 15 of the semiconductor chip 11 are covered with the first insulating layer 12.

(P1003. WLP half dicing process)
FIG. 3B shows a state in which a groove A having a width W1 is formed by half-dicing the semiconductor wafer 10 on which the first insulating layer 12 and the like are formed. Using the substrate cutting position C as a cutting position reference, the groove A is formed using a dicer apparatus or the like. At this time, the end portion of the joint surface 20 between the semiconductor integrated circuit 14 and the first insulating layer 12 is exposed on the surface of the groove A.

(P1004. Second insulating layer forming step)
FIG. 3C shows a state in which the second insulating layer 16 is formed on the formed groove A and the first insulating layer 12 using a sealing resin. The end portion of the joint surface 20 between the semiconductor integrated circuit 14 and the first insulating layer 12 is protected by the formed second insulating layer 16.

(P1005. External connection terminal connection)
The external connection terminal 17a (see FIG. 3D) is connected. The part on the surface 16a side of the second insulating layer 16 in FIG. 3C, that is, the part on the surface side of the rewiring layer 110 and the part thicker than the height of the connection electrode 17 of the first insulating layer 12 are: It is deleted by grinding or the like, the end face of the connection electrode 17 is exposed on the surface of the second insulating layer 12, and the external connection terminal 17a (see FIG. 3D) is formed.

(P1006. CSP singulation (second dicing) process)
FIG. 3D shows a state in which a plurality of CSPs 130 are obtained by dividing the WLP into pieces by cutting the cutting allowance W2. A groove B is formed in the portion of the second insulating layer 16b formed in the state of FIG. 2C using a dicer apparatus or the like with the substrate cutting position C as a cutting position reference. The width W2 of the groove B is narrower than the width W1 of the groove A (W2 <W1). In this way, the protective layer 16b is formed on the side surface of the CSP 130. Note that the cutting (dicing) processing of the semiconductor substrate using a dicer apparatus or the like requires two steps, WLP half dicing in the step (P1003) and second dicing in the present step (P1006).

  As described above, since the side surface of the semiconductor device is protected by the second insulating layer, etc., the occurrence of peeling or moisture permeation into each layer at the bonding surface between the upper surface of the semiconductor integrated circuit and the first insulating layer, etc. Can be reduced to some extent. An example of the method for manufacturing the semiconductor device is described in Patent Document 1, for example.

JP 2007-335424 A

  A conventional method of manufacturing a semiconductor device for protecting a side surface of a semiconductor chip of a wafer level package (WLP) requires a complicated process as shown in FIG. 1, for example, and the semiconductor chip of the WLP In some cases, the side protection effect was not sufficient.

The present invention was made in order to solve these problems, and provide a semiconductor device and its manufacturing method with improved reliability, and an object thereof is to simplify the process.

In one embodiment of the present semiconductor device, the semiconductor chip having an electrode pad, a connection electrode having one end surface connected to the electrode pad via a seed layer, and the other end surface of the connection electrode are exposed. A first insulating layer formed on the chip, a wiring formed on the first insulating layer, connected to the other end surface of the connection electrode, and laminated on the first insulating layer so as to cover the wiring, A second insulating layer exposing a part of the wiring, wherein the first insulating layer and the second insulating layer extend along a side surface of the semiconductor chip, and the first insulating layer and the first insulating layer corners 2 insulating layer is formed shall be the requirement that it is tapered.
In addition , the semiconductor device manufacturing method prepares a semiconductor substrate on which a plurality of semiconductor chips each having an electrode pad are arranged, and one end surface of the semiconductor chip is connected to the electrode pad via a seed layer on each electrode pad of each semiconductor chip. Forming a connected connection electrode; forming a semi-cured insulating layer on the semiconductor substrate to expose the other end surface of the connection electrode; and forming the semi-cured insulating layer on the semi-cured insulating layer. forming a wiring connected to the connection electrode, forming a second insulating layer in a semi-cured state covering the wiring on the insulating layer in a semi-cured state, the insulating layer and the semi-semi-cured Separating the semiconductor substrate on which the cured second insulating layer is formed, and forming a plurality of semiconductor chips having the semi-cured insulating layer and the semi-cured second insulating layer ; Semiconductor chip corner Using a mold having a tapered portion at a position corresponding to, by incorporated turning the insulating layer and the second insulating layer in a semi-cured state in a semi-cured state on the side surface of the semiconductor chip, the insulating layer and the first And a step of forming a protective layer formed of two insulating layers and in close contact with the side surface of the semiconductor chip.

Can provide a semiconductor device and its manufacturing method with increased reliability, also, it is possible to simplify the process.

It is a figure which illustrates the process of the manufacturing method of the conventional CSP. It is a figure which illustrates the conventional semiconductor wafer. It is a figure which illustrates the typical state in the process of the manufacturing method of the conventional CSP. It is a figure which illustrates the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is a figure which illustrates the typical state in the process of the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is a figure which illustrates the typical state in the process of the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. 1 is a diagram illustrating a semiconductor device according to a first embodiment of the invention. It is a figure which illustrates the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is a figure which illustrates the typical state in the process of the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is a figure which illustrates the typical state in the process of the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is a figure which illustrates the semiconductor device which concerns on the 2nd Embodiment of this invention. It is a figure which illustrates the manufacturing method of the semiconductor device which concerns on the 3rd Embodiment of this invention. It is a figure which illustrates the manufacturing method of the semiconductor device which concerns on the 4th Embodiment of this invention.

  The best mode for carrying out the present invention will be described below with reference to the drawings. In the description of each figure, the same components common to each figure are denoted by the same reference numerals, and the description thereof may be omitted when overlapping.

<First Embodiment>
FIG. 4 is a diagram illustrating a method for manufacturing the semiconductor device according to the first embodiment of the invention.

  5A and 5B are diagrams illustrating typical states in the steps of the method of manufacturing the semiconductor device according to the first embodiment of the invention. Hereinafter, a method for manufacturing a semiconductor device will be described step by step with reference to the form of the semiconductor device shown in FIGS. 5A and 5B.

  Each step of the manufacturing method includes a connection electrode forming step (S101), an insulating layer forming step (S102), an external connection terminal connecting step (S103), a CSP singulation (dicing) step (S104), and a side protection layer for each piece. Forming step (S105). A semiconductor wafer having a diameter of 6, 8, or 12 inches is used as the semiconductor substrate.

(S101. Connection electrode forming step)
This is a step of forming a columnar connection electrode having one end face connected to an electrode pad on a semiconductor integrated circuit and the other end face connected to an external connection terminal by plating or the like.

  (A) of FIG. 5A has shown the state in which the connection electrode 51 was formed by the electroplating process. One end surface 51a of the columnar connection electrode 51 is connected to the electrode pad 53 on the semiconductor integrated circuit 52 of the semiconductor wafer 50, and the other end surface 51b is used as an external connection terminal in the step (S103) described later. It becomes the terminal to be connected. The connection electrode 51 is formed by the following plating process or the like. That is, a seed layer 56 of a metal such as titanium or copper is formed on a surface of the semiconductor wafer 50 such as a protective film 54 and an electrode pad 53 on the semiconductor integrated circuit 52 by a sputtering apparatus or the like, and the seed layer 56 is used as a power feeding layer. Then, a plating metal such as copper is formed in the recess for the connection electrode provided in the photoresist layer 57. The photoresist layer 57 can be formed using a well-known technique of pasting a resist film, exposing, developing, and peeling. On the other end surface 51b of the connection electrode 51, a nickel layer and a palladium layer are formed in order to improve adhesion to an external connection terminal such as a solder ball, and a gold layer is formed on the surface layer connected to the external connection terminal. be able to. Also, a gold layer can be formed directly on the nickel layer. After the connection electrode 51 is formed, the photoresist layer 57 is peeled off using a sodium hydroxide aqueous solution or the like, and the seed layer 56 is removed by etching using sulfuric acid, hydrogen peroxide water, or the like.

(S102. Insulating layer forming step)
FIG. 5A (b) shows a state in which the insulating layer 59 is formed. The insulating layer 59 is formed so as to cover the semiconductor integrated circuit 52 having the electrode pad 53 and the protective film 54 and the portion excluding the end face 51 b of the connection electrode 51. As a material for the insulating layer 59, a film-like resin or the like can be used. The design of physical properties of a material such as a resin constituting the insulating layer includes the formation of a connection layer on the semiconductor substrate (semiconductor wafer) 50, that is, the formation of the insulating layer 59 and the external connection terminal 61, the separation of the CSP, In each step such as the formation of the side surface protection layer of the individual pieces, the material such as the resin of the insulating layer is kept in a semi-cured state. In particular, in the individual side surface protective layer forming step (S105), the quality of the product is improved by maintaining the semi-hardening state of the insulating layer material so that it can be tightly bonded to the side surface of the semiconductor chip. Can increase the sex.

  As a material of the insulating layer 59, for example, a thermosetting resin such as epoxy resin GX92 manufactured by AFT is used. The conditions for forming the insulating layer that maintains the semi-cured state of the resin in the above steps are, for example, when a film-like resin material is used, for example, a temperature of 80 ° C. to 130 ° C., a pressing force of 10 KN to 130 KN, and a formation time of 60 Second to 300 seconds. As the viscosity in a semi-cured state, for example, it is desirable to maintain a range of 100 poise to 100,000 poise at a temperature of 80 ° C. to 130 ° C.

(S103. External connection terminal connection step)
5C is a diagram of a state of the wafer level package (WLP) 200 in which the external connection terminal 61 is connected to the end face 51b of the connection electrode 51. The WLP 200 is connected to the semiconductor substrate (semiconductor wafer) 50. FIG. A connection layer 150 having the electrode 51, the insulating layer 59, the external connection terminal 61, and the like is formed. The external connection terminal 61 is used as a connection terminal when the CSP package separated in the next step (S104) is mounted on an external electronic application device (not shown). As a material of the external connection terminal, a metal ball using a solder such as tin, silver, or copper, a solder ball having copper as a core, or the like can be used. If the connection and fixing of the external connection terminal requires a high temperature due to the high melting point of the solder, etc., it is only temporarily attached in the step of S103, and after the step of forming the side surface protective layer (S105), the insulating layer After the resin is cured, the external connection terminals can be connected and fixed.

(S104. CSP singulation (dicing) process)
The entire package of the WLP 200 is cut (diced) using a dicer apparatus or the like using the substrate cutting position C shown in FIG. The WLP 200 is cut and divided by the cutting margin of the scribe line 63 to obtain each chip size package (CSP) 64 that is separated into pieces. At the time of dicing, the dicing tape 65 is attached to the surface of the WLP 200 opposite to the surface of the semiconductor integrated circuit 52, that is, the back surface 50b of the semiconductor wafer 50, and the entire WLP 200 is held by the dicing tape 65. After dicing, the separated CSP is held on the dicing tape 65.

(Cutting semi-cured insulation layer)
The method of manufacturing a semiconductor device according to the present invention uses a part of a resin or the like formed on a semiconductor wafer as an insulating layer as it is to seal the side surface of the semiconductor chip, and maintains the semi-cured state on the side surface of the semiconductor chip. It is characterized in that a press for forming a side surface protective layer for tight bonding is performed. Therefore, since the process of dicing the semi-cured insulating layer is performed, a technique for maintaining the shape of the insulating layer is particularly required for dicing. As conditions for dicing processing of the semi-cured insulating layer, for example, the following conditions can be used in a two-stage processing condition, that is, a step-cut method.

  The blade used in the dicer apparatus has an abrasive grain size of # 2000 and a concentration of 70 to 90%. In the first step of the step cut, the blade height position H1 ((c) in FIG. 5A) is set to a position 100 μm from the back surface 50b of the semiconductor wafer to the semiconductor integrated circuit side (upward), and the blade rotation speed is set to 40. , 000 rpm, and the feed rate is 30 mm / sec. In the second step of the step cut, the blade height position H2 is set to a position cut into a 30 μm dicing tape downward from the back surface 50b of the semiconductor wafer, the blade rotation speed is 3,000 rpm, and the feed speed is 30 mm / sec. And

  By using the above-described step-cut method or the like, the entire WLP package on which the semi-cured insulating layer or the like is formed is diced while maintaining its shape, and the CSP singulation process is performed. be able to.

(S105. Forming side surface protective layer of individual piece)
(D) of FIG. 5A has shown the state of CSP with which the insulating layer was side-pressed by press work etc. and the side surface of the piece was protected. A part of the insulating layer 59 is tightly bonded to the side surface 66b of the semiconductor chip 66 in the CSP 64 that has been separated. In the press working, using the press machine having the die 67, the corner part and the side part (broken line 68) of the semi-cured insulating layer 59 of the piece of the semiconductor substrate mounting body already diced are crushed. Then, a protective layer 69 in which the insulating layer 59 that has been deformed by being extended and protruded from the side surface 66b of the semiconductor chip 66 and turned around the side surface 66b of the semiconductor chip 66 is adhered to the side surface 66b of the semiconductor chip 66 is formed. Form and heat cure. When the die 67 is provided with a tapered portion T having an angle θ with respect to the vertical surface M inside the die (0 degree <θ <90 degrees) and subjected to press working, the insulating layer 59 is formed on the side surface of the semiconductor chip 66. 66b. When a resin is used for the insulating layer 59, for example, an epoxy resin GX92 manufactured by AFT can be used. The thermosetting conditions are a temperature of 170 ° C. to 200 ° C. and a curing condition of 1 hr to 2 hr. The protection of the protective layer 69 of the insulating layer can prevent mutual peeling of the semiconductor integrated circuit 52 of the CSP 64 having the connection layer 150, the protective film 54 on the semiconductor integrated circuit 52, the insulating layer 59, and the like.

  The insulating layer is pressed by, for example, operating a press machine provided with a pressing die by driving an air cylinder or the like. The pressing conditions are, for example, pressing with a force of 10 KN to 60 KN, holding at a temperature of 100 ° C., and a pressing time of 60 seconds. The press mold will be described later in <Third Embodiment>.

  (E) of FIG. 5B is a figure which illustrates CSP64 obtained by the manufacturing method of the above process.

  FIG. 6 is a diagram illustrating typical dimensions of a CSP obtained by the method for manufacturing a semiconductor device according to the first embodiment of the present invention in relation to the dimensions of a die of a press machine. D1 and D2 are the lengths of each side of the rectangle of the semiconductor chip, and are, for example, 3 mm to 5 mm. The thickness c1 of the semiconductor chip 66, which is a semiconductor substrate, is 100 μm to 300 μm, and a semiconductor wafer that has been subjected to back surface grinding in advance can be used. The thickness t1 of the insulating layer 59 on the surface layer of the semiconductor chip is 30 μm to 50 μm, the thickness t2 on the side surface is 50 μm to 100 μm, and the length p of the protective layer 69 of the insulating layer from the circuit surface 70 of the semiconductor integrated circuit on the side surface is , 50 μm to 100 μm. The height h1 of the external connection terminal 61 made of a material such as a solder ball is 100 μm to 300 μm, and the perspective view of the external connection terminal 61 viewed from the CSP stacking direction A is generally a circle, and the diameter b of the circle is 200 μm. ˜300 μm.

  The lengths D3 and D4 of the rectangular sides of the opening for pressing in the die 67 of the press machine are designed to be 100 μm to 200 μm longer than the lengths D1 and D2 of the sides of the semiconductor chip. A thickness t2 is secured. The dimension of each part of a metal mold | die is 150 micrometers-350 micrometers, E2 is 5 micrometers-25 micrometers, E3 is 50 micrometers-100 micrometers, E4 is 10 micrometers-100 micrometers.

  The results of the reliability test of the CSP package obtained by the manufacturing method of the present invention are as follows. As a reliability test, a temperature cycle test was performed, and 10 samples of a single CSP package having dimensions of 7 mm × 7 mm were placed in an environment of −65 ° C. (5 minutes) and 150 ° C. (5 minutes). After 500 cycles and 1000 cycles, the package was observed for details of whether or not the tight junction between the semiconductor chip and the insulating layer was peeled off. In any of the samples, peeling did not occur and other defects were generated. Confirmed that there is no. Therefore, it has been shown that the semiconductor device manufacturing method of the present invention is a highly reliable CSP manufacturing method.

<Effect of the first embodiment>
In the conventional process for forming the resin-sealed protective layer on the side surface of the semiconductor chip, the dicing process is repeated. However, according to the present invention, the second and subsequent dicing processes can be omitted. It is possible to provide a method of manufacturing a package with increased reliability by reducing the chance of occurrence of initial internal defects caused by processing. In addition, since the dicing process in the present invention is a process of cutting the semi-cured insulating layer, compared to the cutting of the cured resin in the conventional CSP package, chatter vibration during cutting, dust of resin, etc. Generation | occurrence | production etc. can be suppressed. Therefore, it is possible to provide a method for manufacturing a package that can suppress internal defects of the product, occurrence of chipping, and the like, and has improved reliability. Furthermore, since the dicing process can be limited to only one time, the process can be simplified.

<Second Embodiment>
FIG. 7 is a diagram illustrating a method for manufacturing a semiconductor device according to the second embodiment of the invention. FIG. 7A is a view showing a state of the wafer level package (WLP) immediately before separation. That is, the package 210 of the semiconductor substrate (semiconductor wafer) 50 provided with the rewiring layer 160 having the wiring 82 connected to the connection electrode 51 and formed on the insulating layer 81, the second insulating layer 86 and the external connection terminal 61 is provided. It is a figure which shows the formed state. FIG. 7B is a diagram illustrating a process of the semiconductor device manufacturing method.

  8A and 8B are diagrams illustrating typical states in the steps of the method of manufacturing a semiconductor device according to the second embodiment of the present invention. Hereinafter, a method for manufacturing a semiconductor device will be described step by step with reference to the form of the semiconductor device shown in FIGS. 8A and 8B.

  Each step of the manufacturing method includes a connection electrode formation step (S201), an insulation layer formation step (S202), a wiring layer formation step (S203), a second insulation layer formation step (S204), an external connection terminal connection step (S205), It includes a CSP separation (dicing) step (S206) and a side surface protective layer formation step (S207).

(S201. Connection electrode forming step)
This is a step of forming a columnar connection electrode having one end face connected to an electrode pad on a semiconductor integrated circuit and the other end face connected to an external connection terminal by plating or the like.

  FIG. 8A is a diagram illustrating a state in which the connection electrode 51 is formed on the semiconductor wafer 50. The details of the step (S201) are the same as the contents of the step (S101) in the first embodiment, and thus the description thereof is omitted.

(S202. Insulating layer forming step)
(B) of FIG. 8A is a figure which shows the state in which the insulating layer 81 was formed. As a material of the insulating layer 81, a film-like resin or the like can be used. In designing the physical properties, the physical properties that can maintain a semi-cured state are selected in the process of dividing into individual chip size packages (CSP), the process of forming the side surface protective layer of the individual pieces, and the like. Note that the details of the step (S202) are the same as the contents of the step (S102) in the first embodiment, and thus the description thereof is omitted.

(S203. Formation of wiring layer)
FIG. 8C is a diagram showing a state in which the wiring 82 is formed in the rewiring layer 160. The wiring 82 is made of a material such as copper, and can be formed by a known electrolytic plating method or the like. That is, a power supply seed layer 84 is formed on the end surface 51b exposed on the surface of the insulating layer 81 of the connection electrode 51 using a sputtering apparatus or the like, a photoresist layer 85 is provided on the seed layer 84, and exposure, Using development and peeling techniques, recesses for wiring formed by plating deposition are formed. A wiring made of copper or the like is formed in the formed recess by electrolytic plating. In order to improve the adhesiveness with the external connection terminals such as solder balls on the surface of the wiring 82, a nickel layer and a palladium layer can be formed, and a gold layer can be formed on the surface layer connected to the external connection terminals. Also, a gold layer can be formed directly on the nickel layer. After the wiring 82 is formed, the photoresist layer 85 is peeled off using a sodium hydroxide aqueous solution or the like, and the seed layer 84 is removed by etching using sulfuric acid, hydrogen peroxide solution, or the like.

  (D) of FIG. 8A is a figure which shows the state from which the photoresist layer and the seed layer were removed.

(S204. Formation of second insulating layer)
FIG. 8B (e) is a view showing a state in which the second insulating layer 86 is formed. The second insulating layer 86 is formed to cover the insulating layer 81 and the wiring 82, and an opening 87 for an external connection terminal to be connected in the next step (S205) is provided. For the second insulating layer, a material capable of maintaining a semi-cured state is used in steps such as CSP singulation and individual side surface protection layer formation. The details of the second insulating layer forming step are the same as the contents of the insulating layer forming step (S102) in the first embodiment except for the formation of the opening, and the description thereof is omitted. The second insulating layer 86 can be used as a solder resist layer on the surface layer of the CSP package.

(S205. External connection terminal connection step)
The external connection terminal 61 shown in (f) of FIG. 8B is used as a connection terminal when the CSP 88 package is mounted on an external electronic application device (not shown). Since the content of the external connection terminal connection step is the same as the content of the external connection terminal connection step (S103) in the first embodiment, the description thereof is omitted.

(S206. CSP singulation (dicing) process)
A scribe line 63 in (f) of FIG. 8B indicates a cutting allowance when the entire package of the WLP 210 is cut (diced) with the substrate cutting position C as a position reference. Similar to the content of the CSP singulation step (S104) in the first embodiment described above, the WLP 210 having a semi-cured insulating layer or the like is cut and divided by the scribe line 63 to obtain individual chips. A size package (CSP) 88 can be obtained. The separated CSP is held on a dicing tape 65.

(S207. Side surface protective layer forming step of individual piece)
FIG. 8B (g) shows a state of the CSP 88 in which the insulating layer 81 and the second insulating layer 86 are side-pressed by pressing or the like, and the protective layer 69 is formed on the side surface 66b of the semiconductor chip 66. The protective layer 69 is formed by bonding a part of the insulating layer 81 and the second insulating layer 86 to the side surface 66b of the semiconductor chip 66 constituting the CSP 88 separated into pieces. In the press working, a press machine having a die 67 is used. The semi-cured insulating layer 81 and the second insulating layer 86, which have already been diced, have their corners and side portions (broken lines 68) crushed and extended to protrude into the side surface 66b of the semiconductor chip 66, The protective layer 69 is formed by turning along the side surface 66b of the semiconductor chip 66 and closely bonding. Further, these insulating layers are thermally cured. When the die 67 is provided with a taper portion T having an angle θ with respect to the vertical surface M inside the die (0 ° <θ <90 °) and subjected to press working, the insulating layers 81 and 86 are formed on the semiconductor chip 66. It can be turned into the side surface 66b. When using a resin for these insulating layers, for example, GX92 of an epoxy resin manufactured by AFT can be used. The thermosetting conditions are a temperature of 170 ° C. to 200 ° C. and a curing condition of 1 hr to 2 hr. The insulating layer is pressed by, for example, operating a press machine provided with a plurality of pressing dies by driving an air cylinder or the like. The pressing conditions are, for example, pressing with a force of 60 KN to 100 KN, holding at a temperature of 100 ° C., and a pressing time of 300 seconds. By protecting the protective layer 69 of the cured insulating layer, mutual peeling of the semiconductor integrated circuit 52 of the stacked semiconductor chip 66, the protective film 54 on the semiconductor integrated circuit 52, the insulating layer 81, and the like can be prevented. it can.

  (H) of FIG. 8B is a figure which illustrates CSP88 obtained by the manufacturing method of the above process.

  FIG. 9 is a diagram illustrating typical dimensions of the CSP 88 obtained by the semiconductor device manufacturing method according to the second embodiment of the present invention in relation to the dimensions of the die 67 of the press machine. D5 and D6 are the lengths of each side of the rectangle of the semiconductor chip, for example, 3 mm to 5 mm. The thickness c1 of the semiconductor chip 66, which is a semiconductor substrate, is 100 μm to 300 μm, and a semiconductor wafer that has been subjected to back surface grinding in advance can be used. The thicknesses t1 and t3 of the insulating layer 81 and the second insulating layer 86 on the surface of the semiconductor chip are 5 μm to 50 μm and 10 μm to 20 μm, the thicknesses t2 and t4 on the side surfaces are 5 μm to 50 μm, 10 μm to 20 μm, and the semiconductor integration on the side surfaces The length p of the protective layer of the insulating layer from the circuit surface 70 of the circuit is 50 μm to 100 μm or the like. The height h1 of the external connection terminal 61 made of a material such as a solder ball is 100 μm to 300 μm, and the perspective view of the external connection terminal 61 viewed from the CSP stacking direction A is generally a circle, and the diameter b of the circle is 200 μm. ˜300 μm.

  The lengths D7 and D8 of the rectangular sides of the press opening in the die 67 of the press machine are designed to be 10 μm to 100 μm longer than the lengths D5 and D6 of the respective sides of the semiconductor chip. The thickness t2 and t4 of the side surface of the insulating layer 86 is ensured. The dimension of each part of the mold is 150 μm to 350 μm for F1, 10 μm to 50 μm for F2, 10 μm to 50 μm for F3, and 10 μm to 100 μm for F4.

  Note that other shapes for the insulating layer can be formed. For example, in the case where the thickness of the second insulating layer 86 described above can be sufficiently taken, only the corner portion and the side surface portion (broken line 68) of the second insulating layer 86 are crushed and extended so that the semiconductor chip 66 is It is possible to cover the side surfaces of the semiconductor chip 66 and the insulating layer 81 by protruding from the side surface 66 b and being turned along the side surface 66 b of the semiconductor chip 66 and the side surface of the insulating layer 81. In that case, it is possible to cure only the insulating layer 81 before the individual side surface protective layer forming step (S207) of this step.

<Effects of Second Embodiment>
Provided is a method for manufacturing a CSP in which a rewiring layer having an insulating layer and a wiring is formed on a semiconductor substrate, and reducing the chance of occurrence of initial internal defects and increasing the reliability. Simplification of the process can be achieved. Furthermore, since the expansion conversion from the arrangement pitch of the electrode pads 53 to the arrangement pitch of the external connection terminals 61 becomes possible, simplification in the mounting process to an external device that is connected and mounted at the location of the external connection terminals 61 is facilitated. In addition, it is possible to provide a manufacturing method of an application product of a semiconductor device with improved reliability.

<Third Embodiment>
FIG. 10 is a diagram illustrating a method for manufacturing a semiconductor device according to the third embodiment of the invention. This is a manufacturing method in which a plurality of separated semiconductor substrate mounting bodies 108 are simultaneously pressed using the press device 101 in FIG. The press machine 101 includes a press unit 102, a mold base 103, a press mold 104, and a press substrate 105.

(B) of FIG. 10 shows details of the U portion of (a). The mold base 103 has clamps 15 and 15 for adjusting the position of the press mold 104 in the horizontal direction (xy direction) and fixing the press molds 104 at positions where the respective press molds 104 are provided. , A position adjusting and fixing means 106 in the vertical direction (z direction) of the press mold 104 and a sliding means 107 that enables the press mold 104 to slide smoothly in the horizontal direction. When the press mold 104 is provided with a taper portion T having an angle θ with respect to the vertical surface M inside the mold (0 degree <θ <90 degrees), and the semi-cured insulating layer or the like is pressed, the insulating layer Can be turned into the side surface of the semiconductor chip. The taper portion T inside the mold has a shape having a rounded surface of a quadrangular pyramid ridge with respect to the rectangular CSP piece.

  In FIG. 10A, a plurality of individual semiconductor substrate mounting bodies 108 each having a semi-cured insulating layer and the like are arranged on a press substrate 105. A protective layer can be simultaneously formed on the side surface of each individual piece by performing press processing on the plurality of semiconductor substrate mounting bodies 108 separated into individual pieces. If the arrangement state is such that the mutual interval d of the plurality of semiconductor substrate mounting bodies 108 separated into small pieces and the plurality of press dies interfere with each other, after the CSP is separated into pieces, The individual pieces can be placed on the temporary placement substrate 109 by using a pick-up transfer device or the like while maintaining an appropriate wide interval, and the entire temporary placement substrate 109 can be set on the press substrate 105 to perform press working. . In addition, after the dicing process of CSP singulation, a dicing tape (such as 65 in FIG. 8B (f)) holding the WLP used in the dicing process is stretched and expanded to keep the intervals between the individual CSPs wide. (A) may be placed on the press substrate 105 or the like.

<Effect of the third embodiment>
About the manufacturing method characterized by semi-cured insulating layer processing according to the present invention by press processing of a plurality of individual semiconductor substrate mounting bodies using the press device 101 etc. illustrated in FIG. Productivity can be improved.

<Fourth embodiment>
When manufacturing a semiconductor device of the present invention using a resin as a semi-cured insulating layer, as illustrated in the third embodiment, a press machine provided with a press die is used. In order to perform processing while maintaining a semi-cured state of the resin, a technique for easily releasing the resin without causing the resin to remain attached to the metal mold is required at the time of releasing the CSP and the metal mold at the end of press working. As the material of the mold, stainless steel or the like whose surface layer is hardly deteriorated even when used for a long time is used. The roughness of the surface irregularities is adjusted according to the physical properties of the resin material. Further, in order to facilitate the mold release operation, the surface of the press die that contacts the separated semiconductor substrate mounting body can be covered with a material such as a fluororesin, for example, polytetrafluoroethylene. The press mold 111 illustrated in FIG. 11 is covered with a fluororesin 112 or the like, and the release property of the resin or the like of the insulating layer can be facilitated by pressing using the press mold 111.

<Effect of the fourth embodiment>
By press working using the mold 111 provided with the fluororesin 112 or the like, it is possible to provide a method for manufacturing a package with improved reliability and improved reliability of the CSP according to the present invention.

<Other Embodiments According to the Present Invention>
The preferred embodiment according to the present invention has been described in detail above. However, the present invention is not limited to the above-described embodiment, and various modifications can be made to the above-described embodiment without departing from the scope of the present invention. Variations and substitutions can be added.

  For example, in <Second Embodiment>, the wiring layer in the rewiring layer is formed as one layer on the insulating layer, but the second wiring layer is further formed on the second insulating layer. It is possible to form a rewiring layer characterized by a plurality of wiring layers, such as providing and then covering the surface layer with a third insulating layer.

50 Semiconductor wafer 50b Back surface 51 of semiconductor wafer 50 Connection electrodes 51a, 51b End face 52 of connection electrode 51 Semiconductor integrated circuit 53 Electrode pad 54 Protective film 56, 84 Seed layer 57, 85 Photoresist layer 59, 81 Insulating layer 61 External connection terminal 63 Scribe line 64, 88 Chip size package (CSP)
65 Dicing tape 66 Semiconductor chip 67 Die 68 Corner and side part of insulating layer 69 Protective layer 82 Wiring 86 Second insulating layer 87 Opening 101 for external connection terminal Press device 102 Press means 103 Mold bases 104 and 111 Press mold 105 Press base 106 Vertical position adjustment fixing means 107 of the press mold 104 Sliding means 112 for the press mold 104 Fluororesin
115 Clamp 150 Connection Layer 160 Redistribution Layer 200, 210 Wafer Level Package (WLP)
b Diameters D1, D2, D5, D6 in the perspective view of the external connection terminal 61 Lengths D3, D4, D7, D8 of the bottom side of the semiconductor chip Lengths E1, E2, E3 of the sides of the pressing opening of the die 67 E4, F1, F2, F3, F4 Dimensions of the mold h1 Height of the external connection terminal 61 H1, H2 Height position of the blade M Vertical plane inside the mold p Length of the protective layer t1, t2, t3, t4 Insulating layer thickness T Tapered surface in the mold θ Angle formed by the taper surface T and the vertical surface M in the mold

Claims (7)

A semiconductor chip with electrode pads;
A connection electrode having one end face connected to the electrode pad via a seed layer;
A first insulating layer formed on the semiconductor chip so as to expose the other end surface of the connection electrode;
A wiring formed on the first insulating layer and connected to the other end surface of the connection electrode;
A second insulating layer laminated on the first insulating layer so as to cover the wiring and exposing a part of the wiring;
The semiconductor device, wherein the first insulating layer and the second insulating layer extend along a side surface of the semiconductor chip, and a corner portion formed by the first insulating layer and the second insulating layer is tapered. A protective film exposing the electrode pad is formed on the semiconductor chip,
The semiconductor device according to claim 1, wherein the first insulating layer is formed on an upper surface of the protective film and extends to a side surface of the semiconductor chip to cover the side surface of the protective film. Preparing a semiconductor substrate on which a plurality of semiconductor chips each having an electrode pad are disposed, and forming a connection electrode having one end surface connected to the electrode pad via a seed layer on the electrode pad of each semiconductor chip; ,
Forming a semi-cured insulating layer on the semiconductor substrate so as to expose the other end surface of the connection electrode;
Forming a wiring connected to the connection electrode on the semi-cured insulating layer;
Forming a semi-cured second insulating layer on the semi-cured insulating layer so as to cover the wiring;
The semiconductor substrate on which the semi-cured insulating layer and the semi-cured second insulating layer are formed is separated into a plurality of pieces, and the semi-cured insulating layer and the semi-cured second insulating layer are provided. Forming a semiconductor chip;
Using a mold having a tapered portion at a position corresponding to a corner portion of the semiconductor chip, the semi-cured insulating layer and the semi-cured second insulating layer are turned into the side surface of the semiconductor chip, Forming a protective layer comprising the insulating layer and the second insulating layer and in close contact with the side surface of the semiconductor chip. The method for manufacturing a semiconductor device according to claim 3 , further comprising a step of curing the semi-cured insulating layer and the semi-cured second insulating layer after the step of forming the protective layer. 5. The method of manufacturing a semiconductor device according to claim 3 , wherein a surface of the tapered portion that contacts the semiconductor chip has a tapered surface that forms an angle of more than 0 degrees and less than 90 degrees with respect to a vertical surface inside the mold. The material of the mold, a method of manufacturing a semiconductor device according to any one of claims 3 to 5 is stainless. The surface in contact with the semiconductor chip of the tapered portion, a method of manufacturing a semiconductor device according to any one of claims 3 to 6 are covered with a fluororesin.

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