JP5386342B2 - LSI, Fail-safe LSI for railway, Electronic equipment, Electronic equipment for railway - Google Patents

Description

  The present invention relates to a semiconductor chip with a built-in microprocessor, and more particularly to a semiconductor chip used in a control system requiring high safety such as a signal system in a railway.

  For control systems that require high safety, such as signal systems in railways, if a failure occurs in equipment in the system, the system will not be put into a dangerous state and can be stopped safely. The equipment is designed according to the concept of “safe”. In order to realize fail-safe, it is indispensable to reliably detect device abnormalities. However, in a control system using a microprocessor, it is possible to detect abnormalities in the processor unit by multiplexing the processors and monitoring each other. Yes.

  In recent years, with the progress of high integration of semiconductors, it has become possible to perform operation comparison by incorporating two processors in one LSI chip. The comparison method can be found in Patent Document 1 and the like. Further, Non-Patent Document 1 shows an example of actually creating a one-chip failsafe LSI.

JP-A-6-161798

K. Shimamura, et al .: “A Single-Chip Fail-Safe Microprocessor with Memory Data Comparison Feature”, IEEE 12th Pacific Rim International Symposium on Dependable Computing (PRDC'06), (18-20 Dec. 2006)

  Recently, higher integration of semiconductors has progressed, and it has become possible to incorporate peripheral circuits that have been externally attached to the chip. In order to take advantage of the performance of a processor that operates at high speed, it is necessary to attach a high-speed and large-capacity memory.

  In order to connect various peripheral circuits and high-speed external memories to the chip, it is necessary to increase the number of signal pins of the chip and the package incorporating the chip. In addition, since the operating frequency of the peripheral circuit is also increased, it is necessary to consider the wiring delay and the difference in electrical characteristics when arranging the signal pins.

  On the other hand, in the prior art, from the viewpoint of ensuring reliability, reference is made to the arrangement of the processor and the comparison circuit in the chip, but no mention is made of the signal pin arrangement of the package or the arrangement of the parts of the device board. Further, the peripheral circuit connected to the outside of the chip has only one type of general-purpose bus, and the correspondence to various peripheral circuits and high-speed external memories has not been considered.

  In general, an LSI with a built-in processor has a so-called pin multiplex, in which a single external signal pin has a plurality of functions and the functions are switched as necessary in order to make the application versatile. Often has a signal pin. As a result, a limited number of signal pins can be used effectively, but the conventional technology does not consider pin multiplexing in fail-safe LSIs.

  An object of the present invention is to achieve both safety and high performance including the peripheral circuit of an LSI chip.

  In order to achieve both safety and high performance including the peripheral circuits, the signal pins for the two systems including the processor are arranged at the diagonal positions of the package, that is, at the farthest positions from each other, and between the signal pins for the two systems. A signal pin related to the common system is arranged. When there are two common peripheral circuits, one signal pin related to the peripheral circuit is arranged in a region between signals related to the two systems in two places.

  By placing the signal pins for the common system between the signal pins for the two systems, the distance between the signal pins for the two systems can be maximized, so that the two systems malfunction simultaneously due to a single factor such as electromagnetic noise. It is possible to reduce the possibility of causing

Summary of the present invention. Physical structure of fail-safe LSI. Internal configuration of fail-safe LSI. Outline of wiring connected to common internal bus. Internal configuration of common internal bus. The timing chart for demonstrating operation | movement of an internal bus. The internal configuration of the comparison device. Operation of the alternating signal generator. Internal configuration of the bus comparator. Internal configuration of duplex control circuit. Internal configuration of general-purpose input / output circuit. The figure for demonstrating the logic circuit layout and input-output pad arrangement | positioning in a LSI chip. The figure for demonstrating external pin arrangement | positioning of LSI. Component placement on electronic circuit boards. The internal structure of the fail safe LSI in the second embodiment. The internal structure of the general purpose input / output circuit and the pin function selector in the second embodiment. The figure for demonstrating the logic circuit layout and input-output pad arrangement | positioning in the LSI chip in a 2nd Example. The figure for demonstrating the external pin arrangement | positioning of LSI in a 2nd Example. Overview of fail-safe LSIs with different physical structures. The figure for demonstrating external pin arrangement in the fail safe LSI which has a different external pin structure.

  A first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a diagram for explaining the outline of the present invention. Two LSIs having the same configuration including a processor and an external interface (hereinafter referred to as I / F) circuit are mounted in one LSI 10. In this embodiment, the two systems are called A system and B system. Each processing apparatus has one or more processors and one or more external I / F circuits, which are connected to an internal bus in each system or the like. Since the processing result of the processor in each system etc. appears on the internal bus, if the signals of both buses are compared by the comparison device connected to the A system internal bus and the B system internal bus, the two systems of processing devices are the same You can see that it is moving. A normal / abnormal determination signal 200 is used to output a signal indicating normal when both perform the same operation, and abnormal when both perform different operations, to the outside of the fail-safe LSI chip 100. When normal, that is, when the same signal is output from the two internal buses, the comparison device selects one of them and outputs it to the common internal bus. The comparison device outputs the output from the common internal bus to the processing device to both internal buses of the two systems. By unifying such buses, the same processing is continued without shifting the operation timing of the two systems. A plurality of common external interface circuits are connected to the common internal bus. An external device can be connected to each of the two external I / Fs and the common external I / F having the same configuration. In this way, the integrated internal interface by collating the outputs from the two processors is not directly output to the outside of the chip as in the prior art, but once connected to the common internal bus, By allowing a plurality of external interface circuits to be connected to the internal bus, various peripheral circuits can be connected, and the performance of the LSI can be improved.

  In other words, a plurality of external interfaces can be built in by providing a common internal bus, so that a plurality of external devices can be directly connected to the chip.

  FIG. 2 is a diagram showing an outline of the physical structure of the fail-safe LSI in this embodiment. FIG. 2A is a diagram showing a cross section of the fail-safe LSI 10. The external I / F signal and power supply of the LSI chip 100 are connected to the package substrate 101 by bonding wires 103, and solder is attached to the lower portion of the package substrate 101. It is connected to the outside via the ball 104. The upper part of the LSI chip 100 is protected by a sealing material 102. FIG. 2B is an overhead view of the fail-safe LSI 10 with the sealing material 102 removed. The LSI chip 100 is arranged on the package substrate 101 with the circuit surface facing upward, and is connected to the package substrate 101 by bonding wires 103. Indicates that FIG. 2C is a diagram showing a circuit surface of the LSI chip 100. The LSI chip 100 is connected to a logic circuit mounting area 105 in which logic circuits such as two systems of processing devices and comparison devices are formed, and to signals and power supplies. This indicates that the input / output pad area 106 is formed. In this embodiment, an A-system processing device is arranged on the left side of the LSI chip 100, a B-system processing device is arranged on the right side, and a common system circuit is arranged in the center. The arrangement within the chip will be described later.

  FIG. 3 is a diagram showing the internal configuration of the fail-safe LSI and external devices in this embodiment. The fail-safe LSI 10 has two systems of processors 11A and 11B, two systems of internal buses 12A and 12B, and high-speed memory I / F circuits 13A and 13B and external bus I / F as two systems of external I / F. F circuits 14A and 14B and general-purpose input / output circuits 15A and 15B are provided. External RAMs 131A and 131B are connected to the high-speed memory I / F circuits 13A and 13B, and external ROMs 141A and 141B are connected to the external bus I / F circuits 14A and 14B as external devices, respectively. The fail safe LSI 10 includes a comparison device 20 and a common internal bus 21, and includes a system bus I / F circuit 22 and a network I / F circuit 23 as the common external I / F. A system bus bridge 221 is connected to the system bus I / F circuit 22 and a network physical layer 231 is connected to the network I / F circuit 23 as an external device. A normal / abnormal determination signal 200 is output from the comparison device 20.

  FIG. 4 is a diagram showing an outline of wiring connected to the common internal bus 21 in this embodiment. An I / F signal 205 with the comparison device 20, an I / F signal 222 with the system bus I / F circuit 22, and an I / F signal 232 with the network I / F circuit 23 are connected to the common internal bus 21. The The I / F signals 205, 222, and 232 are respectively sent to master ports 205M, 222M, and 232M that issue read / write requests to the internal bus, and slave ports 205S, 222S, and 232S that receive read / write requests from the internal bus. Divided. In the present embodiment, all three modules connected to the common internal bus 21 have a master port and a slave port, but generally only one of the ports is sufficient. Since the internal buses 12A and 12B of the two systems have the same configuration and functions as the common internal bus 21 except for the number of modules to be connected, detailed description will be omitted. For example, the high-speed memory I / F circuit 13A and The I / F with 13B has only a slave port.

  FIG. 5 is a diagram showing details of the internal configuration of the common internal bus 21 and the wiring to be connected in this embodiment. In FIG. 5, the master port and the slave port are shown separately for easy understanding of the signal flow. The common internal bus 21 includes a bus control circuit 211 and wiring to each port. The bus control circuit 211 includes a request control circuit 212 and a response control circuit 213. Each master port is composed of six types of signals: address (output), write data (output), command (output), grant (input), read data (input), and valid (input). Each slave port consists of seven types of signals: address (input), write data (input), command (input), busy (output), port number (output), read data (output), and valid (output). Is done. The input / output directions are from each port to the bus control circuit 211. The request control circuit 212 arbitrates a transfer request from each master port, decodes an address, and selects an output destination slave port. The code is well known for bus arbitration and address, and detailed description is omitted. The response control circuit 213 arbitrates the read data return request from each slave port, and outputs it to the requesting master port. The response control circuit 213 has a buffer (not shown) for temporarily holding read data for each slave port, and a return request from each slave port is not awaited.

  FIG. 6 is a timing chart for explaining the operation of the common internal bus 21. FIG. 6 shows data write and read operations between the master port 205M and the slave port 222S. The common internal bus 21 transfers data every clock cycle in synchronization with the clock signal shown at the top of the figure. When the comparator 20 gives an address indicating the register in the system bus I / F circuit 22 as the address 2051M, a write data 2052M, and a code indicating 4-byte write as the command 2053M to the bus control circuit 211 in the clock cycle i, the request The control circuit 212 determines that there is no request from another master port or the busy state of the slave port to which the request is issued, and asserts the grant 2054M to notify the request source that the request has been accepted. At the same time, the request control circuit 212 outputs the address 2221S, the write data 2222S, and the command 2223S to the slave port 222S to which the request is issued. The system bus I / F circuit 22 connected to the slave port 222S writes the write data to the register in its own module according to the received address.

  When an address indicating the internal register of the system bus bridge 221 connected to the system bus I / F circuit 22 as an address 2051M and a code indicating a 4-byte read as a command 2053M are given to the bus control circuit 211 in the clock cycle j, a request is made. The control circuit 212 determines the bus state and asserts the grant 2054M to notify the request source that the request has been accepted. At the same time, the request control circuit 212 outputs an address 2221S and a command 2223S to the slave port 222S to which the request is issued. The system bus I / F circuit 22 connected to the slave port 222S issues a read request to the system bus bridge 221 according to the received address. In clock cycle j + 1, the system bus I / F circuit 22 asserts busy 2227S and notifies the request control circuit 212 that other requests cannot be accepted. When the read data from the system bus bridge 221 is ready to be returned in the clock cycle J + 2, the system bus I / F circuit 22 uses the port number 2228S as a code indicating the requesting port 205M, read data 2225S. The data is output to the response control circuit 213 together with the valid 2226S. The response control circuit 213 outputs read data 2055M and valid 2056M to the port 205M indicated by the port number 2228S.

  In this way, data can be transferred between connected modules using the common internal bus 21. In particular, this bus separates request control and response control to realize a so-called split transaction that does not prevent data transfer between other modules even during a read request from one module. Even if there is a module that transfers a large amount of DMA data at a time, such as the system bus I / F, the bus is not occupied, and a reduction in bus throughput can be avoided. In addition, since the wiring between each port and the bus control circuit can be made one-to-one, the influence of wiring delay on the operation speed of the entire bus can be minimized even if the module is placed at a physically separated position.

  FIG. 7 is a diagram showing an internal configuration of the comparison device 20 in this embodiment. The comparison device 20 includes an alternating signal generator 201, a bus comparator 202, and a duplex control circuit 203, and is connected to the A system internal bus 121A, the B system internal bus 121B, and the common system internal bus 21.

  FIG. 8 is a diagram showing the operation of the alternating signal generator 201 in this embodiment. The alternating signal generator 201 outputs a normal / abnormal determination signal 200 in accordance with the comparison mismatch signal 204 output from the bus comparator 202. If a normal or abnormal state is output to the outside with a single level signal, a failure mode in which the signal level is fixed to ON or OFF is unavoidable. Therefore, in railway signal systems, etc., ON and OFF are repeated at a constant frequency. The “alternating signal” has been used in the past, which is normal if it is normal and abnormal in other states. Also in this embodiment, the alternating signal generator 201 outputs a frequency signal when the comparison mismatch signal 204 matches or indicates normality, and outputs a level signal when it does not match or indicates abnormality. Since the generation logic of the alternating signal is well known, detailed description thereof is omitted.

  FIG. 9 is a diagram showing an internal configuration of the bus comparator 202 in the present embodiment. The bus comparator 202 constantly compares the signal output from the A-system internal bus 121A and the signal output from the B-system internal bus 121B, and turns on the comparison mismatch signal 204 when a mismatch is detected. The data to be compared are address 1211MA and 1211MB, write data 1212MA and 1212MB, command 1213MA and 1213MB, busy 1217SA and 1217SB, port numbers 1218SA and 1218SB, read data 1215SA and 1215SB, and valid 1216SA and 1216SB. If detected, the flip-flop inside the bus comparator 202 is set, and the comparison mismatch signal 204 remains ON. In addition, in order to detect malfunction of the bus comparator itself, a technique is known in which the comparators are multiplexed or an error is intentionally generated at regular intervals. In this embodiment, a highly reliable comparator is used. Since this logic is publicly known, detailed description is omitted.

  FIG. 10 is a diagram showing the internal configuration of the duplex control circuit 203 in this embodiment. The duplex control circuit 203 outputs a signal output from the A-system internal bus 121A to the common system internal bus 21 unless a comparison mismatch is detected by the bus comparator 202. That is, address 1211MA, write data 1212MA, command 1213MA, busy 1217SA, port number 1218SA, read data 1215SA, valid 1216SA are address 2051M, write data 2052M, command 2053M, busy 2057S, port number 2058S, read data 2055S, valid. 2056S. When the comparison mismatch is detected, the output of the command 1213MA and the valid 1216SA is suppressed by the comparison mismatch signal 204, and the common internal bus 21 does not detect the issuance of the request and the response. The output to 21 is stopped.

  Signals output from the common internal bus 21 are sent simultaneously to the A internal bus 121A and the B internal bus 121B. That is, grant 2054M, read data 2055M, valid 2056M, address 2051S, write data 2052S, command 2053S are grant 1214MA and 1214MB, read data 1215MA and 1215MB, valid 1216MA and 1216MB, address 1211SA and 1211SB, write data 1212SA and 1212SB and commands 1213SA and 1213SB. As described above, the redundant control circuit 203 makes the A system internal bus 121A and the B system internal bus 121B look like one bus (port 205) from the common system internal bus 21, and the A system internal buses 121A and B Since the operation timing of the internal system bus 121B is not deviated, the processing in the two systems of processing devices is not deviated.

  The processors 11A and 11B are assumed to be general microprocessors, and description thereof is omitted as a known technique. The high-speed memory I / F circuits 13A and 13B are assumed to be general-purpose high-speed memories such as a DDR-SDRAM (Double Data Rate-Synchronous DRAM), and the description thereof is omitted as a known technique. The voltage tends to be lower than that of a general-purpose external bus. Specifically, the general-purpose external bus has an I / F voltage of 3.3 V, and the DDR-SDRAM has an I / F voltage of 2.5 V, and the LSI needs to support a plurality of I / F voltages. External bus I / F circuits 14A and 14B are assumed to be external buses of general microprocessors composed of chip select, address, data, read / write strobe, etc., and description thereof is omitted as a known technique.

  FIG. 11 is a diagram showing an internal configuration of the general-purpose input / output circuit 15A in this embodiment. The general-purpose input / output circuit 15B has the same configuration. The general-purpose input / output circuit 15A has a general-purpose IO read data register (PIORR_A) 151A, a general-purpose IO write data register (PIOWR_A) 152A, and a general-purpose IO function setting register (PIOFR_A) 153A, which are connected via the internal bus 12A. Values are read and written by the processor 11A. PIORR_A and PIOWR_A have a data width of 8 bits and are connected to the external signal line 150A of the LSI 10 via the input / output buffer 154A. PIOFR_A has a data width of 1 bit. When the value is 0, the data is output, and the value set in PIOWR_A is output to the external signal line 150A. When the value of PIOFR_A is 1, it is a data input, and the signal level of the external signal line 150A is input to PIORR_A.

  FIG. 12 is a diagram for explaining a logic circuit layout and input / output pad arrangement in the LSI chip 100 according to this embodiment. In order to avoid a single factor from causing the same error in both systems, it is desirable that the two systems be placed as far apart as possible in the chip. For this reason, the logic circuit layout in this embodiment is arranged such that an A-system processing device is arranged on the left side of the chip and a B-system processing device is arranged on the right side of the chip. By separating the A-system and B-system logic circuits. Further, the distance between the same logic circuits of the A system and the B system is maximized by making the layout within the B system processing apparatus upside down of the A system. The arrangement of the input / output pads is closely related to the logic circuit layout. In this embodiment, the input / output pads for signals relating to the A-system memory I / F are on the left side of the chip, and the signals relating to the B-system memory I / F are used. The input / output pads for the signals related to other external I / Fs in the A system are on the lower left side of the chip, and the input / output pads for signals related to the other external I / Fs in the B system are on the upper right side of the chip. In this manner, the A system signal and the B system signal are arranged at diagonal positions on the outer periphery of the chip. In addition, signal input / output pads related to the common external I / F are arranged on the upper and lower sides of the chip so as to separate the A and B signals. In the present invention, it is important to arrange the I / Fs, that is, the I / F signals of the A system and the B system are arranged diagonally, and to separate them with the signals of the common system. Details of the number of specific signals of F, the specific boundary positions of each I / F, and the specific signal arrangement in each I / F are not mentioned. Further, the directions of the left and right and the top and bottom of the chip are also relative, and are not limited to the directions shown in this embodiment.

  Further, in the actual input / output pad arrangement, there are usually restrictions on the input / output pad design such as a reserve pad for a power supply and a diagnostic function. When there is a restriction on the input / output pad arrangement, it is actually difficult to arrange all the signals on the input / output pads diagonally with respect to the center point of the chip. The present invention does not strictly require signal arrangement on the input / output pads at diagonal positions, and it is only necessary to arrange two systems of signals at approximately diagonal positions. For example, if the arrangement order of each I / F unit is diagonal, the arrangement of signals belonging to each I / F may be interchanged.

  FIG. 13 is a diagram for explaining the external pin arrangement of the LSI 10 in this embodiment. FIG. 13A is a perspective view of the pin arrangement seen from the viewpoint instructed to the appearance of the LSI 10 in FIG. 13B, that is, directly above the LSI 10. In this embodiment, the signal pin is not arranged at the center of the package, and is an empty area. The external pin arrangement is the same as the logic circuit layout and input / output pad arrangement in the LSI chip 100 shown in FIG. 12, with the input / output pins for signals related to the A-system memory I / F on the left side of the package and the B-system memory I. Input / output pins for signals related to / F on the right side of the package, input / output pins for signals related to other external I / Fs in the A system at the lower left of the package, and input / output signals for signals related to other external I / Fs in the B system On the upper right side of the package, the A system signal and the B system signal pin are arranged diagonally on the outer periphery of the package. Also, signal input / output pins related to the common system external I / F are arranged on the upper and lower sides of the package so as to separate the A system and B system signal pins. Further, according to the present invention, the arrangement of each I / F, that is, each I / F signal pin of the A system and the B system is arranged diagonally with respect to the center point of the package, and the common signal pins separate them. It is important to do so, and details of the number of specific signal pins of each I / F, the specific boundary position of each I / F, and the specific signal pin arrangement in each I / F are not mentioned. Moreover, the directions such as the left and right and the top and bottom of the package are relative and are not limited to the directions shown in the present embodiment.

  Furthermore, in actual signal pin arrangements, there are usually package design restrictions such as power supply pins and reserve pins for diagnostic functions. When there is a restriction on pin arrangement, it is actually difficult to arrange all signal pins diagonally with respect to the center point of the package. The present invention does not strictly require pin arrangement at diagonal positions, and two signal pins may be arranged at roughly diagonal positions. For example, if the arrangement order of each I / F unit is diagonal, the signal pins belonging to each I / F may be interchanged.

  FIG. 14 is a diagram showing a component arrangement on the electronic circuit board 30 on which the LSI 10 and the external device are mounted in the present embodiment. RAM-A1 (1311A), RAM-A2 (1312A), RAM-B1 (1311B), and RAM-B2 (1312B) are connected to the high-speed memory I / F circuits 13A and 13B of the failsafe LSI 10, and the external bus I The ROM-A (141A) and the ROM-B (141B) are connected to the / F circuits 14A and 14B. In addition, a system bus bridge LSI 221 is connected to the system bus I / F circuit 22 of the fail safe LSI 10, and a network physical layer LSI 231 is connected to the network I / F circuit 23. The black circles at the corners of the figures showing these external devices are index marks for semiconductor components, that is, marks for determining the mounting direction of the components. The device connected to the A system and the device connected to the B system are upside down in the same manner as the arrangement of the signal pins. The normality / abnormality determination signal 200 output from the comparison device 20 is connected to the state notification connector 2000 and notifies the outside of the electronic circuit board 30 of the state. A signal output from the system bus bridge LSI 221 is connected to a system bus connector 2210, and a bus signal is exchanged between the electronic circuit board 30 and another board. A signal output from the network physical layer LSI 231 is connected to the network connector 2310, and a network signal is exchanged between the electronic circuit board 30 and another board. As in the present embodiment, by arranging signal pins relating to the network I / F circuit 23 on the upper side of the LSI 10 and the system bus I / F circuit 22 on the lower side, the respective external circuits are connected to the respective I / F on the substrate. The wiring can be routed without detouring or being congested, which is advantageous from the design cost and performance of the board.

  In the electronic circuit board 30 of FIG. 14, a signal pin area relating to the high-speed memory I / F circuit 13A of the LSI 10, and an area 300A in which RAM-A1 (1311A) and RAM-A2 (1312A) are mounted (hatched area in the figure) The signal pin area related to the high-speed memory I / F circuit 13B of the LSI 10 and the area 300B (hatched area in the figure) where the RAM-B1 (1311B) and RAM-B2 (1312B) are mounted are the other areas. This is a region where the power supply voltage is different. Specifically, the high-speed memory I / F is a power supply voltage of 2.5V, and other I / Fs are 3.3V. Thus, in this embodiment, the different voltage regions can be separated into left and right, so that the influence of noise accompanying the operation of the high-speed RAM on the operation of the high-speed RAM on the opposite side can be reduced. Note that the essence of the present invention is that the same function I / F of the two systems is located at a diagonal position regardless of which I / F is what power supply voltage and how many different voltage regions exist. By arranging them in this way, mutual interference can be minimized.

  A second embodiment of the present invention will be described with reference to FIGS. When setting pin multiplexes in the fail-safe LSI which is the subject of the present invention, the external I / O described in the first embodiment is used for pin multiplexes between signals relating to two systems of processing devices or signals of common systems. This is a problem to be solved in the arrangement of / F, and it is sufficient that signals relating to the two systems of processing devices are arranged on the diagonal of the LSI. However, the pin multiplexes of the signals related to the two systems of processing devices and the signals of the common system are preferably arranged as in the second embodiment to be described.

  FIG. 15 is a diagram showing an internal configuration of the fail-safe LSI and external devices in the second embodiment. The first embodiment differs from FIG. 3 in that it has general-purpose input / output circuits 24A and 24B and pin function selectors 25A and 25B, and signals related to the general-purpose input / output circuits 15A and 15B are directly connected to the outside of the LSI 10. First, signals related to the general-purpose general-purpose input / output circuits 24A and 24B are selectively connected to the outside by the pin function selectors 25A and 25B, that is, are pin multiplexed.

  FIG. 16 is a diagram showing the internal configuration of the general purpose input / output circuit 15A, the general purpose input / output circuit 24A and the pin function selector 25A in the second embodiment. The general-purpose input / output circuit 15B, the general-purpose input / output circuit 24B, and the pin function selector 25B have the same configuration. As in the first embodiment, the general purpose input / output circuit 15A has a general purpose IO read data register (PIORR_A) 151A, a general purpose IO write data register (PIOWR_A) 152A, and a general purpose IO function setting register (PIOFR_A) 153A. The register is read and written by the processor 11A via the internal bus 12A. The general-purpose input / output circuit 24A includes a general-purpose IO read data register (PIORR_C1) 241A, a general-purpose IO write data register (PIOWR_C1) 242A, and a general-purpose IO function setting register (PIOFR_C1) 243A. The values are read and written by simultaneous access from the processors 11A and 11B.

  The pin function selector 25A includes a general purpose IO selection register (PIOSR_A) 251A and a selection circuit 252A. A circuit (not shown) for register access of PIOSR_A is in the general-purpose input / output circuit 15A, and values are read and written by the processor 11A via the internal bus 12A. PIORR_A and PIOWR_A have an 8-bit data width, and PIOFR_A has a 1-bit data width, and are connected to the selection circuit 252A. PIORR_C1 and PIOWR_C1 have an 8-bit data width, and PIOFR_C1 has a 1-bit data width, and are connected to the selection circuit 252A. PIOSR_A has a data width of 1 bit. When the value is 0, the function of the general-purpose input / output circuit 24A is selected, and when the value is 1, the function of the general-purpose input / output circuit 15A is selected. That is, when the function of the general-purpose input / output circuit 24A is selected, PIORR_C1 and PIOWR_C1 are connected to the external signal line 250A of the LSI 10 via the input / output buffer 252A, and the input / output direction is determined according to the value of PIOFR_C1. When the function of the general-purpose input / output circuit 15A is selected, PIORR_A and PIOWR_A are connected to the external signal line 250A of the LSI 10 via the input / output buffer 252A, and the input / output direction is determined according to the value of PIOFR_A.

  FIG. 17 is a diagram for explaining a logic circuit layout and input / output pad arrangement in the LSI chip 100 according to the second embodiment. The difference from FIG. 12 is that a pin function selector for switching between the A system external I / F and the common system external I / F is arranged at the lower left of the chip, and the B system external I / F and the common system external I / F are arranged at the upper right of the chip. A pin function selector for switching between the signal input / output pad for the signal related to the A system external I / F and the signal input / output pad for the signal related to the common system external I / F at the lower left Input signals related to signals switched by the pin function selector between the pad input / output pads for signals related to the B system external I / F and the signal input / output pads related to the common system external I / F. The output pad, that is, the B system / common system mixed region is arranged.

  FIG. 18 is a diagram for explaining the external pin arrangement of the LSI 10 in the second embodiment. The difference from FIG. 13 is related to the signal switched by the pin function selector between the signal input / output pin for the A system external I / F and the signal input / output pin for the common system external I / F in the lower left as in FIG. I / O pins, that is, A / common system mixed area, signals that are switched by the pin function selector between the I / O pins for signals related to the B-system external I / F in the upper right part and the I / O pins for signals related to the common-system external I / F Input / output pins, that is, B system / common system mixed areas are arranged. When performing pin multiplexing of the signals related to the two systems of processing devices and the signals of the common system, it is possible to break the symmetry of the signals of the A system and the B system by using the pin arrangement as in the second embodiment. Can be prevented.

  FIG. 19 is a diagram showing an outline of a fail-safe LSI having a physical structure different from that of the first embodiment. FIG. 19A is a diagram showing a cross section of the fail-safe LSI. The external I / F signal and power supply of the LSI chip are connected to the package substrate by the bumps 107 on the chip. FIG. 19B is an overhead view of a state where the sealing material is removed from the fail-safe LSI. The LSI chip 100 is arranged on the package substrate with the circuit surface facing downward, and is connected to the package substrate by the bump 107 on the chip. Indicates that FIG. 19C is a diagram showing the circuit surface of the LSI chip. A B-type processing device is arranged on the left side of the LSI chip, an A-type processing device is arranged on the right side, and a common system circuit is arranged in the center. However, as with the first embodiment, the external pins of the LSI package are arranged such that signal pins of the A system are arranged on the left side of the LSI, the B system is arranged on the right side, and the common pins are arranged vertically. That is, when the chip is mounted on the back as shown in this figure, the signal arrangement of the LSI chip and the LSI package is reversed left and right.

  FIG. 20 is a diagram for explaining an external pin arrangement in a fail-safe LSI having an external pin structure different from that of the first embodiment. FIG. 20A shows the case of the first embodiment in which there is no external pin at the center of the package. The signal pins of the A system are arranged on the left side of the LSI, the B system is arranged on the right side, and the common system is arranged vertically. Is done. However, in this figure, power pins (including ground pins) that are not I / F signals are indicated by black circles. The total number of pins and the arrangement and number of power supply pins vary depending on the package design. In this figure, the signal pins of the A system, B system, and common system are mounted in any positional relationship. It shows that. FIG. 20B shows the case where there are external pins at the center of the package, but the center is all power pins. The signal pins of the A system on the left side of the LSI, the B system on the right side, and the common system on the top and bottom. Is placed. Since there is no signal pin in the central portion, the signal pins of the A system and the B system are separated by the common signal pins as in FIG. FIG. 20C shows the case where there is an external pin at the center of the package, and the center is also a signal pin. The signal of the A system on the left side of the LSI, the B system on the right side, and the common system at the top and bottom and center A pin is placed. As described above, the common system signal pins are separated from the common system signal pins by disposing the common system signal pins in the center as in the other examples.

10 Fail-safe LSI
11A, 11B Processors 12A, 12B Internal buses 13A, 13B High-speed memory interface circuits 14A, 14B External bus interface circuits 15A, 15B General-purpose input / output circuit 20 Comparison device 21 Common internal bus 22 System bus interface circuit 23 Network interface circuit 25A , 25B Pin function selector 30 Electronic circuit board 100 Fail-safe LSI chip 200 Normal / abnormal discrimination signal 201 Alternating signal generator 202 Bus comparator 203 Duplex control circuit 204 Comparison mismatch signal

Claims (20)

A first processor including a processor and an external interface circuit;
A second processor including the same processor and external interface circuit as the first processor;
A comparison device of a common system not belonging to the two systems for comparing the processing results of the two systems of processing devices;
A common external interface circuit not belonging to the two systems,
The comparison device has a bus comparator that outputs a determination signal indicating normal when the two systems of processing devices perform the same operation and abnormal when the two systems of processing devices perform different operations. And
The input / output signal pins of the common external interface circuit are arranged between the input / output signal pins of the two external interface circuits so that the input / output signal pins of the two external interface circuits are not adjacent to each other. LSI characterized by that. In the LSI according to claim 1,
The input / output signal pins of the external interface circuit of the first system and the corresponding input / output signal pins of the external interface circuit of the second system are:
LSI, characterized in that the position of it respectively diagonally to the central point of the LSI package, or the position of each diagonal in the outer periphery of the LSI package, or in each opposite side side of the LSI package. In the LSI according to claim 2,
Has the common system external interface circuit of the two or more input and output signal pins of the two or more external interface circuit of the common system, with respect to the center point on the LSI package, it respectively versus position of the corners, or An LSI characterized by being arranged at diagonal positions on the outer periphery of the LSI package or on opposite sides of the LSI package . An electronic device having an electronic circuit board on which the LSI according to claim 3 is mounted,
An electronic apparatus, wherein the LSI is arranged between two or more external devices of the common system connected to two or more external interface circuits of the common system. In the LSI according to claim 1,
The comparison device outputs a signal from the matched processing device when the signals output from the two processing devices match, and outputs a signal from the processing device when they do not match. A duplex control circuit that does not output
When the signals output from the two processing devices match each other, the matched signals from the processing devices are received from the duplex control circuit, and the signals are sent to the plurality of external interface circuits in the common system. An LSI having a common internal bus control circuit for outputting. In the LSI according to claim 5,
2. The LSI according to claim 1, wherein the duplex control circuit includes a transmission means for outputting a signal from the common internal bus control circuit to the two systems of processing devices. In the LSI according to claim 1,
First pin function selection that selects a part of the input / output signals of the external interface circuit of the first system and a part of the input / output signals of the external interface circuit of the common system and shares them with the same input / output signal pin Circuit,
Second pin function selection for selecting a part of the input / output signals of the external interface circuit of the second system and a part of the input / output signals of the external interface circuit of the common system to be shared by the same input / output signal pins And an LSI. In the LSI according to claim 1,
Between the input / output signal pin of the external interface circuit of the first system and the input / output signal pin of the external interface circuit of the common system, a part of the input / output signals of the external interface circuit of the first system and the common system Input / output signal pins that share part of the input / output signals of the external interface circuit
Between the input / output signal pin of the external interface circuit of the second system and the input / output signal pin of the external interface circuit of the common system, a part of the input / output signal of the external interface circuit of the second system and the common system And an input / output signal pin that shares a part of the input / output signal of the external interface circuit. In the LSI according to claim 1,
Output pads of the external interface circuit of the two systems mounted on the LSI chip, the position of which respectively the diagonal with respect to the center point of the LSI chip in the package, or the position of each diagonal in the outer periphery of the LSI package, or Placed on opposite sides of the LSI package ,
The input / output pads of the common external interface circuit mounted on the LSI chip are input / output of the two external interface circuits so that the input / output pads of the two external interface circuits are spaced apart from each other. Between the pads,
In the logic circuit mounting area in the LSI chip, the comparison device and the common system are between the area where the first processor and the external interface circuit are mounted and the area where the second processor and the external interface circuit are mounted. An LSI in which the interface circuit is mounted so that the first system area and the second system area are not adjacent to each other. In the LSI according to claim 1,
An external device connected to the two external interface circuits;
An LSI, wherein the external device includes an external memory. The LSI according to claim 10, wherein
2. An LSI according to claim 1, wherein a signal voltage of the external memory connected to the two systems of external interface circuits differs at least in part from a signal voltage of the common system external interface circuit. In an electronic device for railroad equipped with the LSI according to claim 10,
And an external memory disposed in said first line, said the arrangement of the external memory in the second system, the electronic circuit board on which the LSI is mounted, the position of the diagonal centered the LSI, or the outer periphery of the LSI An electronic device characterized by being at a diagonal position in or opposite to the LSI . A first system processing device including a processor and an external interface circuit, and a second system processing device including the same processor and external interface circuit as the first system processing device are provided in one LSI chip.
A comparison device for a common system that does not belong to the two systems for comparing the processing results of the two systems;
A common external interface circuit not belonging to the two systems,
The comparison device has a bus comparator that outputs a determination signal indicating normal when the two systems of processing devices perform the same operation and abnormal when the two systems of processing devices perform different operations. And
The input / output signal pins of the external interface circuit of the common system are arranged between the input / output signal pins of the external interface circuit of the first system and the input / output signal pins of the external interface circuit of the second system, and the first system the arrangement region of the input and output signal pins of the external interface circuit of the system, the second system external interface circuit output signal pins railway off O Rusefu LSI to the arrangement region, characterized in that are spaced in the . In the fail safe LSI for railways according to claim 13,
The arrangement region of the input and output signal pins of the external interface circuit of the first system, and the arrangement region of the input and output signal pins of the external interface circuit of the corresponding second system,, respectively whereas the center point of the LSI package pairs A fail-safe LSI for railroad, which is arranged at a corner position or at each diagonal position on the outer periphery of the LSI package or at each opposite side of the LSI package . In the failsafe LSI for railway according to claim 14,
Has the common system external interface circuit of the two or more input and output signal pins of the two or more external interface circuit of the common system, with respect to the center point on the LSI package, it respectively versus position of the corners, or A rail-safe fail-safe LSI, characterized by being arranged at diagonal positions on the outer periphery of the LSI package or on opposite sides of the LSI package . In the fail safe LSI for railroad according to claim 15,
Output pads of the external interface circuit of the two systems mounted on the LSI chip, the position of which respectively the diagonal with respect to the center point of the LSI chip in the package, or the position of each diagonal in the outer periphery of the LSI package, or Placed on opposite sides of the LSI package ,
The input / output pads of the common external interface circuit mounted on the LSI chip are input / output of the two external interface circuits so that the input / output pads of the two external interface circuits are spaced apart from each other. Between the pads,
In the logic circuit mounting area in the LSI chip, the comparison device and the common system are between the area where the first processor and the external interface circuit are mounted and the area where the second processor and the external interface circuit are mounted. An area for mounting the interface circuit is arranged so that the area of the first system and the area of the second system are not adjacent to each other. In the fail safe LSI for railroad according to claim 16,
The external device connected to the two external interface circuits includes an external memory,
A rail fail-safe LSI, wherein a signal voltage of the external memory connected to the two external interface circuits differs from a signal voltage of the common external interface circuit at least in part. 18. The railway electronic device equipped with the rail fail-safe LSI according to claim 17, wherein the arrangement of the external memory in the first system and the arrangement of the external memory in the second system are an electronic circuit on which the LSI is mounted. on the substrate, the position of the diagonal centered the LSI, or the position of the diagonal in the outer periphery of the LSI, or railway electronic apparatus, characterized in that has a very of the LSI. The failsafe LSI for railroad according to claim 17,
The comparison device outputs a signal from the matched processing device when the signals output from the two processing devices match, and outputs a signal from the processing device when they do not match. A duplex control circuit that does not output
When the signals output from the two processing devices match each other, the matched signals from the processing devices are received from the duplex control circuit, and the signals are sent to the plurality of external interface circuits in the common system. A rail-safe fail-safe LSI having a common internal bus control circuit for output. In the fail safe LSI for railroad according to claim 19,
The redundant control circuit includes a transmission unit that outputs a signal from the common internal bus control circuit to the two systems of processing devices.

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