JP5392810B2 - Instruction issue control device and instruction issue control method - Google Patents

Description

  The present invention mainly relates to vector operation instruction issue control.

  In recent years, hardware devices such as processors have been improved so as to increase the speed of instruction execution, and a plurality of instructions can be issued and executed simultaneously in one cycle. For example, in a vector processing apparatus, vector instructions are executed in parallel using a plurality of arithmetic units. Technologies for improving the performance of hardware devices are disclosed in, for example, Patent Documents 1 and 2.

A vector processing device that executes a vector instruction uses a vector register to execute the vector instruction, temporarily stores the operation result in the temporary register, and transfers the operation result stored in the temporary register to the vector register. It is broken down into operation result transfer instructions to be executed.
JP 2006-079623 A Japanese Patent Laid-Open No. 58-154045

  In a vector processing device, when an arithmetic register is composed of a 1-port RAM (Random Access Memory), a read process from a register by an arithmetic process instruction and an arithmetic result write process by an arithmetic result transfer instruction at the time of execution of the arithmetic instruction As a result, access to the RAM may compete.

  This is because a one-port RAM is used because it is necessary to minimize the amount of hardware such as arithmetic registers in order to reduce the area of an LSI (large scale integration). Specifically, since a 1-port RAM, that is, a RAM that can execute either a read process or a write process at a certain timing, is employed, there is a problem that access to the RAM competes.

  Also, minimizing the amount of arithmetic registers and other hardware has been a long-standing issue in order to reduce the area occupied by the logical operation unit from the viewpoint of LSI cost reduction. Therefore, in a situation where a 1-port RAM has to be adopted, there has been a demand for improvement in calculation performance even in a configuration in which contention occurs between the reading process from the register and the writing process of the calculation result.

  An object of the present invention is to provide a vector processing apparatus and method capable of efficiently executing vector instructions.

  One aspect of the vector processing apparatus according to the present invention is a vector instruction control unit that receives a vector instruction and manages the issuance of vector instructions, a vector instruction issued from the vector instruction control unit, and uses a vector register to A vector comprising: an operation processing instruction that temporarily stores an operation result in a temporary register; and a vector operation means that decomposes and executes an operation result instruction that transfers the operation result stored in the temporary register to a vector register In the processing apparatus, the vector instruction control means stores an execution waiting vector instruction in a state of being decomposed into an operation processing instruction and an operation result transfer instruction, accepts a vector instruction, and receives the received vector Determine the temporary register used by the instruction and accept the If the register number specified for the operand of the Kuttle instruction matches the temporary register, the operand register of the accepted vector instruction is renamed to the temporary register, and either the accepted vector instruction or the renamed vector instruction An instruction analysis unit that separates the arithmetic processing instruction and the operation result transfer instruction and stores the instruction in the instruction issuance waiting buffer unit; Waiting instruction control means for detecting an arithmetic processing instruction to be executed in advance, stored in a register, and canceling the issuance of an arithmetic result transfer instruction corresponding to the detected arithmetic processing instruction, and managing the issuance of the execution waiting vector instruction Command issue management means.

  According to another aspect of the vector processing method of the present invention, an execution waiting vector instruction, an operation processing instruction for temporarily storing an operation result in a temporary register, and an operation for transferring the operation result stored in the temporary register to the vector register are provided. A vector processing method comprising instruction issue waiting buffer means for storing a result transfer instruction in a state of being decomposed, accepting a vector instruction, determining a temporary register used by the accepted vector instruction, If the register number specified for the operand matches the temporary register, the operand register of the accepted vector instruction is renamed to the temporary register, and the operation is performed on either the accepted vector instruction or the renamed vector instruction. Processing instructions and said It is separated into calculation result transfer instructions and stored in the instruction issue waiting buffer means, and the execution destination vector register of the execution waiting vector instructions is analyzed for the same and stored in the same vector register. An arithmetic processing instruction is detected, the operation result transfer instruction issuance corresponding to the detected arithmetic processing instruction is stopped, the issuance of the execution waiting vector instruction is managed, and output to the vector arithmetic means for executing the vector instruction.

  According to the present invention, it is possible to execute a vector instruction efficiently.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. For clarity of explanation, the following description and drawings are omitted and simplified as appropriate. In the drawings, components having the same configuration or function and corresponding parts are denoted by the same reference numerals and description thereof is omitted.

(Embodiment 1)
In the embodiment, an aspect of improving the efficiency of execution of a vector instruction by controlling the execution of the operation result transfer instruction among the operation processing instruction and the operation result transfer instruction obtained by dividing the vector instruction will be described. Embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing an outline of an instruction issue mechanism of the vector processing apparatus according to the first embodiment of the present invention. The vector processing apparatus includes a scalar processing unit (hereinafter referred to as “SPU” as appropriate) 1, a vector instruction control unit (hereinafter referred to as “VIC” as appropriate) 2, and a vector operation pipe unit (hereinafter referred to as “VPP” as appropriate). ).

  In FIG. 1, the scalar processing unit 1 has a function of identifying a vector instruction using calculation resources of VPPs 30 to 37 and sending it to the VIC 2.

  The vector instruction control unit (vector instruction control means) 2 buffers the vector instruction received from the SPU 1, manages the busy of operation resources, and sends an instruction to execute the vector instruction to the VPPs 30 to 37 at an appropriate timing.

  The vector operation pipe units 30 to 37 execute designated vector operation processing in accordance with the vector instruction execution instruction received from the VIC 2. Here, although the case where the eight vector operation pipe parts 30-37 are provided is shown, it is not necessarily restricted to this number. Moreover, in the following description, when the whole vector calculation pipe parts 30-37 are shown, it is called the vector calculation part (vector calculation means) 3.

  Next, the configuration of the VIC 2 will be described. The VIC 2 includes an instruction analysis unit 41, a standby instruction control unit 42, an instruction issue management unit 43, and an instruction issue standby buffer unit 204.

  The instruction analysis means 41 receives a vector instruction and determines a temporary register used by the received vector instruction. When the register number specified in the operand of the accepted vector instruction matches the temporary register, the operand register of the accepted vector instruction is renamed to the temporary register. Further, either the received vector instruction or the renamed vector instruction is separated into an operation processing instruction and an operation result transfer instruction and stored in the instruction issue standby buffer unit 204. The instruction analysis unit 41 includes a vector instruction buffer unit 201, an inter-instruction dependency analysis unit 202, and an instruction decomposition and rename processing unit 203.

  The standby instruction control means 42 analyzes the same execution destination vector register among the execution waiting vector instructions, detects a previously executed arithmetic processing instruction stored in the same vector register, and detects the detected arithmetic processing. Stops issuing the operation result transfer instruction corresponding to the instruction. The standby command control means 42 includes an identical VR write recognition unit 208, a TR number use recognition unit 209, and a retire command invalidation processing unit 210.

  The instruction issuance management unit 43 manages the issuance of execution waiting vector instructions. The command issuance management unit 43 includes a command issuance check unit 205, a command issuance unit 206, and a pass busy management unit 207.

  The outline of the function of each means has been described above, but each component included in the instruction analysis means 41, the standby instruction control means 42, and the instruction issue management means 43, and the instruction issue standby buffer unit 204 will be described in detail.

  The vector instruction buffer unit 201 temporarily buffers the vector instruction received from the SPU1. The vector instruction received from the SPU 1 includes the write destination register number of the vector instruction and VL length information. The vector instruction buffer unit 201 reads the buffered vector instruction if the instruction issue standby buffer unit 204 is not busy, assigns an ID to the vector instruction, and sends it to the inter-instruction dependency analysis unit 202. “The instruction issue standby buffer unit 204 is busy” means that the instruction issue standby buffer unit 204 is not empty. When the instruction issue standby buffer unit 204 is busy, the vector instruction buffer unit 201 waits until the busy state of the instruction issue standby buffer unit 204 is resolved. At this time, if the instruction continues to be sent from SPU1, its own memory becomes full and the instruction from SPU1 cannot be held. Therefore, the vector instruction buffer unit 201 sends a busy signal to SPU1 and instructs to stop sending the instruction. To do.

  The inter-instruction dependency analysis unit 202 receives a vector instruction and ID from the vector instruction buffer unit 201, generates instruction dependency information, and sends the vector instruction, ID, and instruction dependency information to the instruction decomposition and rename processing unit 203. . Specifically, the inter-instruction dependency analysis unit 202 analyzes and analyzes the register dependency between the received vector instruction and the preceding vector instruction existing in the instruction decomposition and rename processing unit 203 and the instruction issue waiting buffer unit 204. The result is generated as instruction dependent information. The inter-instruction dependency relationship is information of Read after Write, Write after Read, Write after Write, or no dependency relationship.

  Further, the write destination register number, VL length information and ID of the vector instruction existing in the inter-instruction dependency analysis unit 202 are sent to the same VR write recognition unit 208. The vector instruction existing in the inter-instruction dependency analysis unit 202 is a vector instruction sent from the vector instruction buffer unit 201. The inter-instruction dependency analysis unit 202 holds the vector instruction sent from the vector instruction buffer unit 201, and is replaced (overwritten) when a new vector instruction is sent next time. That is, the inter-instruction dependency analysis unit 202 holds the latest vector instruction (one) sent from the vector instruction buffer unit 201.

  The instruction decomposition and rename processing unit 203 determines a temporary register area for storing operation results used by the vector instruction received from the inter-instruction dependency analysis unit 202. If the register number (VR number) specified in the operation operand exists in the temporary register (TR), the register specified in the operand is renamed to a temporary register, and the information is decomposed into an instruction decomposition and rename processing unit 203. In the rename table.

  FIG. 2 shows an example of the rename table. FIG. 2 shows a case where the result storage register number is one type. The timing at which the entry held in the rename table is deleted is the timing at which the operation result transfer instruction (retire instruction) from the temporary register to the vector register is issued. If the temporary register number is not included in the operand of the unexecuted instruction stored in the instruction issue standby buffer unit 204, the entry is reset. That is, when the temporary register number is included in the operand of the unexecuted instruction, it is assumed that the transfer instruction is not issued, and as a result, the entry is not reset.

  The instruction disassembly and rename processing unit 203 renames the vector instruction and stores the operation instruction until the vector instruction is stored in the temporary register area for storing the operation result, and the temporary register area for storing the operation result. The operation result transfer instruction for transferring the operation result is decomposed into two. The instruction decomposition / rename processing unit 203 includes an instruction issuance standby buffer unit that receives the vector instruction (operation processing instruction and operation result transfer instruction) decomposed into two, inter-instruction dependency information and ID received from the inter-instruction dependency analysis unit 202 To 204. Further, the vector command information after the rename is sent to the TR number use recognition unit 209.

  The instruction issue standby buffer unit 204 has the following functions (1) to (5). (1) A function that stores the decomposed vector instruction, inter-instruction dependency information, and ID received from the instruction decomposition and rename processing unit 203, and sends information necessary for the issue check of the vector instruction to the instruction issue check unit 205. (2) A function of receiving an ID and an entry reset instruction from an instruction issue check unit 205 (to be described later) and resetting an entry corresponding to the instructed ID after a certain period. Further, (3) when the retire instruction invalidation prohibition flag is not valid in the storage field of the retired instruction in the instruction issue waiting buffer section 204 from the retire instruction invalidation processing section 210, the ID received from the retirement instruction invalidation processing section 210 Function to invalidate the corresponding operation result transfer instruction. (4) When the retirement instruction invalidation prohibition flag validation signal is received from the retirement instruction invalidation processing unit 210, the retirement instruction invalidation is prohibited in the storage field of all the operation result transfer instructions stored in the instruction issue waiting buffer unit 204. Function to enable flag. (5) A function for validating the retire instruction invalidation prohibition flag in the retire instruction storage field to be written to the operand input vector register number received from the retire instruction invalidation processing unit 210.

  The instruction issue check unit 205 receives inter-instruction dependency information as information necessary for the issuance check of the vector instruction from the instruction issue standby buffer unit 204, and selects an appropriate vector instruction from among the instructions that can be issued without inter-instruction dependency. To do. Further, the instruction issuance check unit 205 receives operation resource busy information such as an arithmetic unit to be used in the selected vector instruction and various data transfer paths from the path busy management unit 207 described later, and is not busy in all the operation resources to be used. When the conditions are confirmed, it is determined that the issue is confirmed, and the vector instruction whose issue is confirmed is sent to the instruction issue unit 206 and the pass busy management unit 207.

  The instruction issuance unit 206 receives a vector instruction whose issue is confirmed from the instruction issuance check unit 205, generates information necessary for vector instruction execution in the vector operation unit 3 to be described later, and sends it to the vector operation unit 3 have.

  The path busy management unit 207 receives a vector instruction that has been issued from the instruction issuance check unit 205, and issues a function for managing busy information for each computing resource used by the vector instruction and busy information for all the computing resources. It has a function of sending to the check unit 205. Here, it is assumed that the instruction issuing unit 206 instructs the VPPs 30 to 37 to start operations simultaneously. Therefore, the path busy management unit 207 manages one busy information of the VPPs 30 to 37. Here, it is assumed that the VPPs 30 to 37 instruct to start the operation at the same time. For example, it manages the busy information (whether it is in use) of VR303 and VRR309 of VPP30.

  The same VR write recognition unit 208 receives the write destination register number and VL length information of the vector instruction from the inter-instruction dependency analysis unit 202. The same VR write recognition unit 208 includes a write destination register number of a vector instruction existing (received) in the inter-instruction dependency analysis unit 202, a vector instruction existing in the instruction decomposition / rename processing unit 203, and the instruction issue standby buffer unit 204. Are compared with each other and the IDs of the matched vector instructions are sent to the TR number use recognition unit 209. Specifically, (1) the vector instruction write destination register number held by the inter-instruction dependency analysis unit 202 is compared with the vector instruction write destination register number held by the instruction decomposition and rename processing unit 203, and the matching vectors Extracts the register number to which the instruction is written. Subsequently, (2) the vector instruction write destination register number held by the inter-instruction dependency analysis unit 202 is compared with the vector instruction write destination register number held by the instruction issue waiting buffer unit 204, and the matching vector instruction is written. Extract the destination register number. (3) The vector instruction write destination register number extracted in (1) and (2) above is sent to the TR number use recognition unit 209.

  Further, the same VR write recognition unit 208 holds the VL length information of the latest operation instruction notified from the inter-instruction dependency analysis unit 202 in its own storage area. The same VR write recognition unit 208 compares the stored VL length information (the latest VL length information) with the VL length information received from the inter-instruction dependency analysis unit 202 and receives the inter-instruction dependency analysis unit 202. If the VL length is small, a retire command invalidation prohibition signal is sent to the TR number use recognition unit 209. After the comparison process, the same VR write recognition unit 208 holds (rewrites) the VL length information received from the current inter-command dependency analysis unit 202 as the latest VL length information. The same VR write recognition unit 208 holds an initial value (here, zero) as the latest VL length information.

  The TR number use recognizing unit 209 receives the vector instruction after the rename process from the instruction decomposition and rename processing unit 203, and changes the input operand from the register number whose coincidence is confirmed by the same VR write recognition unit 208 to the temporary register number. If it is confirmed that the name has been renamed, the ID received from the same VR write recognition unit 208 is validated and sent to the retirement instruction invalidation processing unit 210. If a vector register is designated as the input operand, the operand input vector register number is sent to the retired instruction invalidation processing unit 210 for the maximum number of operands. That is, if there is a register number that has not been renamed in the operand of the renamed vector instruction, all the register numbers that have not been renamed are sent to the retired instruction invalidation processing unit 210. For example, when a vector instruction has two operands, the maximum number of operands is two. No special operation is performed when a temporary register is specified. The TR number use recognizing unit 209 has a function of sending a retire command invalidation prohibition signal received from the same VR write recognizing unit 208 to the retire command invalidation processing unit 210.

  The retirement instruction invalidation processing unit 210 receives the ID and the retirement instruction invalidation prohibition signal from the TR number use recognition unit 209, and invalidates the operation result transfer instruction corresponding to the received ID when the retirement instruction invalidation prohibition signal is not valid. The function to send the instruction to the instruction issue standby buffer unit 204 is provided. Further, the retirement instruction invalidation processing unit 210 has a function of transmitting a retirement instruction invalidation prohibition flag validation signal to the instruction issue standby buffer unit 204 when receiving a retirement instruction invalidation inhibition signal from the TR number use recognition unit 209. . Further, the retired instruction invalidation processing unit 210 has a function of sending the operand input vector register number received from the TR number use recognizing unit 209 to the instruction issue standby buffer unit 204.

  Here, the reason why the retired instruction invalidation is inhibited when the VL length becomes small is that when there are a plurality of arithmetic instructions stored in the same VR number, the preceding instruction is invalidated even though the VL length becomes small in the subsequent arithmetic instruction. This is to prevent the phenomenon that the data corresponding to the VL difference is not written to the vector register. Depending on the architecture, there may be cases where it is allowed, but we will exclude it here.

  If the VL length of the subsequent vector instruction is larger than the VL length of the preceding vector instruction, the latest operation result is stored in the vector register by the retired instruction of the subsequent vector instruction even if the retired instruction of the preceding vector instruction is invalidated. So there is no problem from the viewpoint of data consistency. Therefore, in this embodiment, when the VL length becomes longer than the preceding vector instruction, the operation result transfer instruction is invalidated. Thereby, it is possible to further reduce the number of times that the operation result transfer instruction is executed when the operation result transfer instruction is not invalidated when the VL length is large.

  Note that the registers included in each component of the VIC 2 are reset at the start of operation and set to an initial value (for example, zero).

  Next, details of the VPPs 30 to 37 will be described. FIG. 3 is a block diagram illustrating a configuration example of the vector pipe unit. Each of the VPPs 30 to 37 has the same configuration. Each VPP includes a load data supply unit 301, a register input crossbar 302, a vector register 303, a register output crossbar 304, a timing adjustment FF (timing adjustment flip-flop) 305, a two-input selector 306, a two-input selector 307, a computing unit 308, a temporary A register 309, a store data transmission unit 310, and a pipeline control unit 311 are included.

  The load data supply unit 301 sends the data loaded from the memory according to an instruction from the pipeline control unit 311 described later to the vector register 303 through the register input crossbar 302.

  The register input crossbar 302 has a function of selecting output data from the load data supply unit 301 or the temporary register 309 in accordance with an instruction from a pipeline control unit 311 described later, and sending the selected data to the vector register 303.

  In this embodiment, the vector register 303 is composed of four 1-port RAMs (each of which has an input / output port), and a total of four read operations and write operations are performed using ports assigned in a time division manner. It has functions that can be implemented. FIG. 4 shows an example of a vector register data element storage image in the present embodiment. In the following description, the four RMAs of the vector register 303 are described as RAM # 0 to RAM # 3.

  The register output crossbar 304 has a function of outputting the register read data output from the register / vector register 303 to a timing adjustment FF 305, a 2-input selector 307, or a store data transmission unit 310, which will be described later, in accordance with an instruction from the pipeline control unit 311.

  The timing adjustment FF 305 receives the register read data received from the register output crossbar 304 and sends it to the 2-input selector 306 after one clock.

  The 2-input selector 306 selects either the data output from the timing adjustment FF 305 or the output data from a temporary register 309 described later according to the instruction from the pipeline control unit 311, and sends it as operation operand data of the operation unit 308.

  The 2-input selector 307 selects either register read data output from the register output crossbar 304 or output data from a temporary register 309 described later in accordance with an instruction from the pipeline control unit 311 and transmits the selected data as operation operand data of the operation unit 308.

  The arithmetic unit 308 has a function of performing an operation according to an instruction of the pipeline control unit 311 using the outputs of the 2-input selector 306 and the 2-input selector 307 as operation operand data, and outputting operation result data to the temporary register 309.

  The temporary register (VRR) 309 has a function of temporarily storing calculation result data received from the calculator 308. Further, according to an instruction from the pipeline control unit 311, a function of reading the operation result data as an operation result transfer instruction for transferring the operation result from the temporary register area to the register and sending it to the register input crossbar 302, and a function from the pipeline control unit 311 It has a function of outputting data read in accordance with the instruction to the 2-input selector 306 or 2-input selector 307 as operation operand data. The temporary register 309 is a RAM having a total of four ports, one write port and three read ports, and has a function capable of performing the above-described operations simultaneously. FIG. 5 shows an example of a temporary register data element storage image in the present embodiment.

  The store data sending unit 310 has a function of storing the register read data received from the register output crossbar 304 in the memory in accordance with an instruction from the pipeline control unit 311.

  The pipeline control unit 311 is a pipeline control unit, receives the vector instruction issued from the instruction issue unit 206, performs instruction identification processing, and each of the load data supply unit 301 to the store data transmission unit 310 described above at a predetermined timing. It has a function of giving data transfer instructions and calculation instructions to the components.

  Vector instructions generally include vector load instructions, vector store instructions, vector operation instructions, and mask update instructions. The vector load instruction is a read instruction, the vector store instruction is a write instruction, the vector operation instruction is an operation instruction, and the mask update instruction is an instruction for operating a mask bit. The vector instructions sent from the SPU 1 to the vector instruction buffer unit 201 include the four types of instructions described above. Of the vector instructions, an instruction using the arithmetic unit 308 is called a “vector operation instruction” and may be distinguished. However, in the present embodiment, description will be made using the names of vector instructions without making any particular distinction.

Next, the operation of this embodiment will be described with reference to the drawings. First, the operation in the case of only one vector instruction is shown, and then the operation in the case of two vector instructions will be described. First, the operation when there is one vector instruction will be described. An example of an instruction sequence (referred to as instruction 1) used here is as follows.
V7 ← V0 + V1 VL = 8 ... (Instruction 1)
This instruction is a vector instruction that arithmetically sums the registers V0 and V1 of 8 elements (VL = 8) and stores them in the register V7. Here, the number of elements (VL) of the instruction is the number of elements processed by each of the vector operation pipe units (VPP) 30 to 37. For example, in FIG. 1, when VL = 8, since 8 VPPs 30 to 37 process, 8 * 8 = 64 elements can be processed in parallel.

  The instruction 1 is identified as a vector instruction in the SPU 1 and sent to the vector instruction buffer unit 201 in the VIC 2.

  The vector instruction buffer unit 201 temporarily buffers the vector instruction received from the SPU1. The vector instruction buffer unit 201 confirms that the instruction issue standby buffer unit 204 is not busy, reads the buffered vector instruction, and assigns ID “0001” to the vector instruction to analyze the inter-instruction dependency relationship. To the unit 202.

  The inter-instruction dependency analysis unit 202 analyzes a register dependency with the preceding vector instruction existing in the instruction decomposition / rename processing unit 203 and the instruction issue standby buffer unit 204. Here, since there is no instruction at this time in the instruction decomposition / rename processing unit 203 and the instruction issuance standby buffer unit 204, there is no inter-instruction dependency information indicating that there is no relationship between Read after Write, Write after Read, and Write after Write. And ID “0001” are sent to the instruction resolution and rename processing unit 203. In addition, the inter-instruction dependency analysis unit 202 uses the same VR write recognition unit for the write destination register number, the VL length information, and the ID “0001” of the vector instruction (the vector instruction received from the vector instruction buffer unit 201) existing in itself. Send to 208.

  The same VR write recognition unit 208 receives the write destination register number and VL length information of the vector instruction from the inter-instruction dependency analysis unit 202. First, the same VR write recognition unit 208 exists in the write destination register number of the ID “0001” vector instruction existing in the inter-instruction dependency analysis unit 202, the instruction decomposition / rename processing unit 203, and the instruction issue standby buffer unit 204. Compare the register number of the vector instruction write destination. Here, since there is no instruction in the instruction decomposition / rename processing unit 203 and the instruction issuance standby buffer unit 204, the same VR write recognition unit 208 sends the mismatch information to the TR number use recognition unit 209. In addition, the same VR write recognition unit 208 holds the VL length information received this time from the inter-instruction dependency analysis unit 202 (replaces the held VL length information).

  The instruction decomposition and rename processing unit 203 determines the temporary register area for storing the operation result used by the vector instruction (instruction 1) received from the inter-instruction dependency analysis unit 202 as T0, and uses the information as instruction decomposition and rename processing. This is held in the rename table in the section 203. Since the register number (VR number) specified for the operation operand does not exist in the temporary register (TR), the register specified for the operand is not renamed.

The instruction disassembly and rename processing unit 203 also includes an operation processing instruction (instruction 1-1) until the vector instruction (instruction 1) is stored in the operation result storage temporary register after being renamed, and an operation result storage temporary. An operation result transfer instruction (instruction 1-2) for transferring an operation result from the register area to the register is decomposed into two. Instructions 1-1 and 1-2 are shown below.
T0 ← V0 + V1 VL = 8... (Instruction 1-1)
V7 ← T0 VL = 8... (Instruction 1-2)

  At this time, the instruction IDs are “0001a” and “0001b”, respectively, and the second operation result transfer instruction (instruction 1-2), which has been divided into two in order to keep the order relationship of Read after Write of the temporary register, is an arithmetic process. The inter-instruction dependency relationship information for the instruction (instruction 1-1) is given, and the inter-instruction dependency information received from the inter-instruction dependency relation analyzing unit 202 is sent to the instruction issuance standby buffer unit 204.

  The inter-instruction dependency relationship information is information given to the decomposed instructions, and is given because it is necessary to keep the order of reading after writing to the same temporary register number between the decomposed instructions. Here, the operation result is written to the register T0 of the VRR 309 by the instruction of ID “0001a”, and then the operation result written to T0 by the instruction of ID “0001b” is read and stored in the V7 register. At this time, the instruction with ID “0001b” has a dependency after Read Write with respect to the instruction with ID “0001a” via T0.

  The TR number use recognizing unit 209 receives the vector instruction “V7 ← V0 + V1” after the rename processing from the instruction decomposition and rename processing unit 203, and cannot confirm that the input operand is renamed to the temporary register number. The ID received from the same VR write recognition unit 208 is invalidated. Further, as described above, since the outputs of the same VR write recognizing unit 208 do not match, the TR number use recognizing unit 209 sends information having no corresponding ID to the retired instruction invalidation processing unit 210.

  The instruction issue standby buffer unit 204 stores the decomposed vector instructions (instruction 1-1 and instruction 1-2) received from the instruction decomposition and rename processing unit 203, inter-instruction dependency information, and IDs “0001a” and “0001b”. Information necessary for the issuance check of the vector instruction is sent to the instruction issuance check unit 205. This state is shown in FIG.

  The retired instruction invalidation processing unit 210 receives information without corresponding ID from the TR number use recognition unit 209 and does not send an invalidation instruction to the instruction issue standby buffer unit 204 because there is no invalidation target.

  The instruction issuance check unit 205 receives inter-instruction dependency information as information necessary for the issuance check of the vector instruction from the instruction issuance standby buffer unit 204, selects an ID “0001a” arithmetic processing instruction that can be issued without inter-instruction dependency, It is confirmed that the arithmetic unit 308 and the register slot (each RAM of the vector register 303) which are arithmetic resources used by the arithmetic processing instruction are not busy, and the issue is confirmed to the instruction issue unit 206 and the pass busy management unit 207 as issue confirmation. Send a vector instruction. At this time, the ID “0001b” operation result transfer instruction is not issued because it has an inter-instruction dependency on the ID “0001a” operation instruction and does not satisfy the instruction selection condition.

  The instruction issuance check unit 205 manages the register input / output timing of the vector register 303 and the temporary register 309, and the ID “0001b” immediately after the operation result is stored in the temporary register 309 by the ID “0001a” operation processing instruction. The inter-instruction dependency information held in the instruction issuance standby buffer unit 204 is cleared so that the operation result is read from the temporary register 309 by the operation result transfer instruction. In this embodiment, inter-instruction dependency held in the instruction issue standby buffer unit 204 at such a timing that the ID “0001b” operation result transfer instruction can be issued 9 clocks after the ID “0001a” operation processing instruction is issued. Clear related information.

  The instruction issuing unit 206 receives the operation processing instruction that has been issued and issued from the instruction issuance check unit 205, generates information necessary for executing the vector instruction, and sends it to the vector operation pipe units 30 to 37 included in the vector operation unit 3. Send it out.

  The path busy management unit 207 receives the operation processing instruction whose issue is confirmed from the instruction issuance check unit 205, and manages the arithmetic unit busy information which is the operation resource used by the vector instruction and the busy information of the register slot. The computing unit busy information is information indicating whether the computing unit 308 is in use. The register slot busy information is information indicating whether or not a read address in the vector register 303 (for example, a read address of RAM # 0) is in use.

  The pipeline control unit 311 receives the arithmetic processing instruction “T0 ← V0 + V1 VL = 8” (instruction 1-1) issued from the instruction issuing unit 206, and performs instruction identification processing. Subsequently, the pipeline control unit 311 instructs the vector register 303 and the register output crossbar 304 to read the operation instruction operand registers V0 and V1 for eight elements. The 2-input selector 306 and the 2-input selector 307 are instructed to select register read data. The pipeline control unit 311 instructs the arithmetic unit 308 to arithmetically sum two operands. The pipeline control unit 311 instructs the temporary register 309 to store the operation result in the area T0.

  Further, the pipeline control unit 311 receives the operation processing instruction “T0 ← V0 + V1 VL = 8” (instruction 1-1) and receives the operation result transfer instruction “V7 ← T0 VL = 8” (instruction 1− 2), the T0 data read instruction is issued to the temporary register 309, the T0 data selection instruction is issued to the register input crossbar 302, and the T0 data write instruction is issued to the vector register 303.

  FIG. 7 is a time chart showing an execution example of one vector instruction in one vector operation pipe unit. Here, the case of VPP 30 is shown as an example.

  The vector register 303 first inputs the address of the element V0-00 to the RAM # 0, performs a read operation, and reads the V0-00 element. This state is timing_1 in the time chart of FIG. In the following description, the clock (Clock timing) shown in the time chart is indicated as “timing_x” (x ≧ 0). “R” before V0-00 in the time chart indicates a Read operation. “W” indicates a write operation.

  At the next clock timing_2, the read operation is performed by inputting the address of the element V1-00 to the RAM # 0 and simultaneously the read operation is performed by inputting the address of the element V0-01 to the RAM # 1. At the next clock timing_3, the address of the element V1-01 is input to the RAM # 1 to perform a read operation, and at the same time, the address of the element V0-02 is input to the RAM # 2 to perform the read operation. At the next clock timing_4, the address of the element V1-02 is input to the RAM # 2 to perform a read operation, and at the same time, the address of the element V0-03 is input to the RAM # 3 to perform the read operation. At the next clock timing_5, the address of the element V1-03 is input to the RAM # 3 to perform a read operation, and at the same time, the address of the element V0-04 is input to the RAM # 0 to perform the read operation.

  In this way, the leading addresses of V0 and V1 are sequentially input to RAM # 0 to RAM # 3, and the designated 8 elements of the V0 and V1 registers are sequentially read.

  The register output crossbar 304 receives the element read from the vector register 303, performs crossbar control every clock, and transmits the elements V0-00 to V0-07 to the timing adjustment FF 305, and the elements V1-00 to V1-07. Is sent to the 2-input selector 307. Since the elements V0-00 to V0-07 read out as described above are read earlier by one clock than the elements V1-00 to V1-07, the timing of each element of V0 is adjusted by the timing adjustment FF 305. Input to the 2-input selector 306.

  The 2-input selector 306 selects the register read data (elements V0-00 to V0-07) and outputs them to the computing unit 308. The 2-input selector 307 selects register read data (elements V1-00 to V1-07) and outputs the selected data to the computing unit 308.

  The arithmetic unit 308 receives element V0-00 and element V1-00 as operand data at the timing of the arithmetic unit stage A, performs arithmetic sum operation processing by pipeline operation up to the arithmetic unit stage E, and outputs the operation result to the temporary register 309 at timing_8. Output to.

  The temporary register 309 writes the calculation result received from the calculator 308 to the designated T0-00 at timing_9.

  The temporary register 309 writes eight operation result elements T0-01 to T0-07 sequentially from timing_9. In addition, the temporary register 309 receives a T0 data read instruction and sends T0-00 to the read register input crossbar 302 at timing_9.

  The register input crossbar 302 selects T0-00 sent from the temporary register 309 according to an instruction from the pipeline control unit 311 and sends it to the RAM # 0 in the vector register 303 as write data.

  T0-00 is written to RAM # 0 in the vector register 303 at timing_10. In timing_11, T0-01 is written in RAM # 1, in timing_12, T0-02 is written in RAM # 2, in timing_13, T0-03 is written in RAM # 3, and in timing_14, T0-04 is written in RAM # 0. Thereafter, T0-07 is written to RAM # 3 at timing_17, and a series of operations is completed.

Next, the operation when there are two vector instructions will be described. An example of two instruction sequences used here (instruction 11 and instruction 12) is shown below.
V7 ← V0 + V1 VL = 8 (... 11)
V7 ← V2 + V7 VL = 8... (Command 12)
This instruction sequence is characterized in that the write destination register number of the instruction 11 matches the operand register number of the instruction 12 and the write destination register number. Here, the number of elements (VL) of an instruction is the number of elements processed by each of the vector operation pipe units (VPP) 30 to 37 as in the case of the instruction 1. Further, the processing flow of the instructions 11 and 12 is shown in FIGS. 8 to 15 using the configuration diagram of FIG. 1 (the vector calculation unit 3 is omitted in some drawings). In these drawings, the processing contents are shown instead of the names of the components shown in FIG. If it is blank, the process is not executed. The operation will be described with reference to FIGS. FIG. 8 shows an initial state (T).

  First, the instruction 11 is identified as a vector instruction by the SPU 1 and sent to the vector instruction buffer unit 201 in the VIC 2. At the next clock, the instruction 12 is identified as a vector instruction by the SPU 1 and sent to the vector instruction buffer unit 201 in the VIC 2 (FIG. 8).

  In the next clock (FIG. 9), the vector instruction buffer unit 201 temporarily buffers the vector instruction 11 received from the SPU1. Subsequently, it is confirmed that the instruction issue waiting buffer unit 204 is not busy, reads the buffered vector instruction, assigns ID “0001” to the vector instruction 11 and sends it to the inter-instruction dependency analysis unit 202. To do.

  In the next clock (FIG. 10), the vector instruction buffer unit 201 buffers the vector instruction 12. Subsequently, an ID “0002” is assigned to the vector instruction 12 and sent to the inter-instruction dependency analysis unit 202. The inter-instruction dependency analysis unit 202 sends the vector instruction write destination register number, VL length information, and ID “0001” to the same VR write recognition unit 208 in the case of the instruction 1 vector instruction. It is the same.

  The same VR write recognition unit 208 receives from the inter-instruction dependency analysis unit 202 the write destination register number of the vector instruction and VL length information (here, V7 and VL = 8). First, the same VR write recognition unit 208 exists in the write destination register number of the ID “0001” vector instruction existing in the inter-instruction dependency analysis unit 202, the instruction decomposition / rename processing unit 203, and the instruction issue standby buffer unit 204. Compare the register number of the vector instruction write destination. Here, since there is no instruction in the instruction decomposition / rename processing unit 203 and the instruction issuance standby buffer unit 204, the same VR write recognition unit 208 sends the mismatch information to the TR number use recognition unit 209. The same VR write recognition unit 208 holds the VL length information received this time from the inter-instruction dependency analysis unit 202 in its own storage area. In FIG. 13, a dotted arrow indicates a comparison operation. The same applies to FIGS.

  The inter-instruction dependency analysis unit 202 analyzes a register dependency with the preceding vector instruction existing in the instruction decomposition / rename processing unit 203 and the instruction issue standby buffer unit 204. However, since there is no instruction at this time in the instruction disassembly and rename processing unit 203 and the instruction issue standby buffer unit 204, the vector instruction 11 has inter-instruction dependency information indicating that there is no relationship between Read after Write, Write after Read, and Write after Write. And ID “0001” are sent to the instruction resolution and rename processing unit 203.

  At the next clock (FIG. 11), the instruction disassembly and rename processing unit 203 determines that the temporary register area for storing the operation result used by the vector instruction 11 received from the inter-instruction dependency analysis unit 202 is T0, and the information Is stored in a rename table in the instruction decomposition and rename processing unit 203. Since the register number (VR number) specified for the operation operand does not exist in the temporary register (TR), the register specified for the operand is not renamed.

The instruction disassembly and rename processing unit 203 includes an arithmetic processing instruction unit (instruction 11-1) until the vector instruction 11 is stored in a temporary register for storing operation results after renaming, and a temporary register area for storing operation results. The operation result transfer instruction part (instruction 11-1) for transferring the operation result from the register to the register is decomposed. Instructions 11-1 and 11-2 are shown below.
T0 ← V0 + V1 VL = 8... (Instruction 11-1)
V7 ← T0 VL = 8... (Instruction 11-2)

  At this time, the instruction IDs are “0001a” and “0001b”, respectively, and the second operation result transfer instruction part (instruction 11-2), which is divided into two parts in order to maintain the order relationship of Read after Write of the temporary register, is operated. The inter-instruction dependency relationship information for the processing instruction part (instruction 11-1) is given, and the inter-instruction dependency information received from the inter-instruction dependency relation analyzing unit 202 is sent to the instruction issuance standby buffer unit 204.

  Further, the inter-instruction dependency analysis unit 202 analyzes the register dependency between the instruction 12 and the preceding vector instruction 11 existing in the instruction decomposition / rename processing unit 203 and the instruction issue standby buffer unit 204. The inter-instruction dependency analysis unit 202 has a relationship of Read after Write and Write after Write with respect to the vector instruction 11 “V7 ← V0 + V1 VL = 8” existing in the instruction decomposition and rename processing unit 203. This is detected, and the vector instruction 12 and ID “0002” are sent to the instruction decomposition and rename processing unit 203 together with the inter-instruction dependency information. Further, the inter-instruction dependency analysis unit 202 sends the write destination register number, VL length information, and ID “0002” of the vector instruction existing in itself to the same VR write recognition unit 208.

  The same VR write recognition unit 208 receives from the inter-instruction dependency analysis unit 202 the write destination register number of the vector instruction and VL length information (here, V7 and VL = 8). First, the same VR write recognition unit 208 writes the write destination register number of the ID “0002” vector instruction 12 present in the inter-instruction dependency analysis unit 202 and the write destination of the vector instruction 11 present in the instruction decomposition and rename processing unit 203. Compare register numbers. Since the same VR write recognition unit 208 matches the write destination register number of the instruction 12 and the ID “0001b” vector instruction 11 existing in the instruction decomposition and rename processing unit 203, the ID “0001b” of the matched vector instruction 11-1 Is sent to the TR number use recognition unit 209. The same VR write recognition unit 208 has a function of holding VL length information, and compares the held VL length information with the VL length information received from the inter-instruction dependency analysis unit 202. The same VR write recognizing unit 208 does not send a retire command invalidation prohibition signal to the TR number use recognizing unit 209 because both are the same “8”.

  At the next clock (FIG. 12), the instruction decomposition and rename processing unit 203 holds the temporary register area for storing the operation result used by the vector instruction 12 received from the inter-instruction dependency analysis unit 202 in the rename table. Further, T0 is determined from the relationship of “V7−T0”, and the information is stored in the rename table in the instruction decomposition and rename processing unit 203. A specific example of the rename table at this time corresponds to FIG. Similarly, the register number designated as the operation operand is renamed T0 from the information in the rename table. As a result of this processing, the vector instruction 12 is as follows: “T0 ← V2 + T0”.

The instruction disassembly and rename processing unit 203 includes an arithmetic processing instruction unit (instruction 12-1) until the vector instruction 12 is stored in a temporary register for storing operation results after renaming, and a temporary register area for storing operation results. The operation result transfer instruction part (instruction 12-2) for transferring the operation result from the register to the register is decomposed. The instructions 12-1 and 12-2 are shown below.
T0 ← V2 + T0 VL = 8... (Command 12-1)
V7 ← T0 VL = 8... (Command 12-2)

  At this time, the instruction IDs are “0002a” and “0002b”, respectively, and the second operation result transfer instruction part (instruction 12-2) divided into two parts in order to keep the order relationship of Read after Write of the temporary register is an operation. The inter-instruction dependency relationship information for the processing instruction part (instruction 12-1) is given, and the inter-instruction dependency information received from the inter-instruction dependency relation analyzing unit 202 is sent to the instruction issuance standby buffer unit 204.

  The TR number use recognizing unit 209 receives the vector instruction 12 “T0 ← V2 + T0” after the renaming process from the instruction decomposing and renaming unit 203 and confirms that the input operand is renamed to the temporary register number. The ID “0001b” received from the same VR write recognition unit 208 is validated and sent to the retirement instruction invalidation processing unit 210.

  The instruction issue standby buffer unit 204 receives the ID “0001a”, the instruction 11-1 and the ID “0001b”, and the instruction 11-2 from the instruction decomposition and rename processing unit 203, and buffers them. The state of the instruction issue standby buffer unit 204 at this time is shown in FIG. Since the instruction 11 is the same as the instruction 1, the state is the same as the case of the instruction 1.

  At the next clock (FIG. 13), the instruction issue standby buffer unit 204 receives the ID “0002a”, the instruction 12-1 and the ID “0002b”, and the instruction 12-2 from the instruction disassembly and rename processing unit 203, and buffers them. The state of the instruction issue standby buffer unit 204 at this time is shown in FIG.

  The retirement instruction invalidation processing unit 210 receives a valid ID “0001b” from the TR number use recognition unit 209 and sends an instruction to invalidate the operation result transfer instruction with the ID “0001b” to the instruction issue standby buffer unit 204.

  The instruction issue standby buffer unit 204 receives an instruction to invalidate the operation result transfer instruction with the ID “0001b” from the retirement instruction invalidation processing unit 210, and the invalidation prohibition flag with the ID “0001b” is “0”. The operation result transfer instruction with ID “0001b” is invalidated. The state of the instruction issue standby buffer unit 204 at this time is shown in FIG. At this timing, the instruction 11-1 first stored in the instruction issue standby buffer unit 204 is sent to the instruction issue check unit 205.

  At the next clock (FIG. 14), the instruction 11-1 is sent to the instruction issuing unit 206, and at the next clock (FIG. 15), the instruction 11-1 is executed in the vector operation unit 3.

  FIG. 18 shows a time chart when an instruction buffered in the instruction issue standby buffer unit 204 is executed. FIG. 18 shows the timing until the eighth operand data of the instruction 12-1 is read in timing_18. Compared with the time chart of FIG. 7, (1) the operand reading of the first element of the instruction 12-1 has started at timing_10, and (2) one of the operands has been renamed from V7 to T0. It is characteristic that the data is read from the temporary register 309.

Next, the operation when the VL length changes in the direction of decreasing based on the instructions 11 and 12 will be described. This operation is the same as the conventional operation. A redundant description will be omitted, and characteristic points will be described. An example of two instruction sequences (instruction 21 and instruction 22) used here is shown below. The instruction 21 is the same as the instruction 11 but is assumed to be the instruction 21 for easy understanding of the explanation.
V7 ← V0 + V1 VL = 8 ... (Instruction 21)
V7 ← V2 + V7 VL = 6 ... (Instruction 22)
This instruction sequence is based on the instruction sequences shown in the instructions 11 and 12. The VL length of the instruction 21 is 8, but the VL length of the instruction 22 is 6, which is VL. 19 to 26 show the flow of processing. The representation of the figure is the same as in FIGS. 19 to 26 show the flow of processing of all clocks because the instruction number and the VL length of the instruction 22 are different, but the description of the same processing as in FIGS. 8 to 18 is omitted.

The instruction sequence decomposed by the instruction decomposition and rename processing unit 203 is as follows. The disassembly operation is the same as the instructions 11 and 12.
T0 ← V0 + V1 VL = 8... (Instruction 21-1)
V7 ← T0 VL = 8... (Instruction 21-2)
T0 ← V2 + T0 VL = 6... (Command 22-1)
V7 ← T0 VL = 6... (Command 22-2)

  As shown in FIG. 22, the inter-instruction dependency relationship analysis unit 202 analyzes the register dependency with the preceding vector instruction existing in the instruction decomposition and rename processing unit 203 and the instruction issue standby buffer unit 204. The instruction 22 detects that there is a relationship of Read after Write and Write after Write with respect to the vector instruction 21 “V7 ← V0 + V1 VL = 8” existing in the instruction decomposition and rename processing unit 203, and depends on the inter-instruction. The vector instruction 22 and ID “0002” are sent to the instruction decomposition and rename processing unit 203 together with the information. Further, the inter-instruction dependency analysis unit 202 sends the write destination register number, VL length information, and ID “0002” of the vector instruction existing in itself to the same VR write recognition unit 208.

  The same VR write recognition unit 208 receives the write destination register number and VL length information of the vector instruction from the inter-instruction dependency analysis unit 202. First, the same VR write recognizing unit 208 writes the write destination register number of the ID “0002” vector instruction 22 existing in the inter-instruction dependency analyzing unit 202 and the write destination of the vector instruction 21 existing in the instruction disassembly and rename processing unit 203. Compare register numbers. Since the write destination register number of the ID “0001b” vector instruction 21 existing in the instruction decomposition and rename processing unit 203 matches, the same VR write recognition unit 208 matches the ID “0001b” of the matched vector instruction 21-1 with the TR number. It is sent to the use recognition unit 209. The same VR write recognizing unit 208 holds the VL length information “8” of the most recent vector instruction 21 passed one clock ago, and the vector instruction 22 received from the value and inter-instruction dependency analyzing unit 202. The VL length information “6” is compared. The same VR write recognition unit 208 detects that the VL length of the vector instruction 22 is smaller than the held VL length, and sends a retire instruction invalidation prohibition signal to the TR number use recognition unit 209. The same VR write recognition unit 208 holds the VL length information “6” of the vector instruction 22 received from the inter-instruction dependency analysis unit 202 this time in its own storage area.

  At the next clock (FIG. 23), the TR number use recognizing unit 209 receives the vector instruction 22 “T0 ← V2 + T0” whose rename processing is completed from the instruction decomposition and rename processing unit 203, and the input operand thereof is a temporary register number. The ID “0001b” received from the same VR write recognition unit 208 is validated and sent to the retire command invalidation processing unit 210, and the retire command received from the same VR write recognition unit 208 is also sent. An invalidation prohibition signal is sent to the retirement instruction invalidation processing unit 210.

  The retirement instruction invalidation processing unit 210 receives a valid ID “0001b” from the TR number use recognizing unit 209 and simultaneously receives a retirement instruction invalidation prohibition signal. Therefore, the retirement instruction invalidation processing unit 210 receives an instruction to invalidate the operation result transfer instruction of ID “0001b”. The retired instruction invalidation prohibition signal is sent to the instruction issue standby buffer unit 204 without sending it (FIG. 23).

  The instruction issue standby buffer unit 204 receives the retirement instruction invalidation prohibition signal from the retirement instruction invalidation processing unit 210, and sets invalidation prohibition flags for all the operation result transfer instructions buffered in the instruction issue standby buffer unit 204. Enable (FIG. 24). The state of the instruction issue standby buffer unit 204 at this time is shown in FIG. As shown in FIGS. 25 and 26, the instruction 21-2 is held in the instruction issuance standby buffer unit 204 without being invalidated and waits for execution of the instruction.

  FIG. 28 shows a time chart when an instruction buffered in the instruction issue standby buffer unit 204 is executed.

  FIG. 28 shows a time chart until the 8th element of the operand data of the instruction 22-1 is read out in timing_18. Compared with the time chart of FIG. 18 because the retired instruction of the instruction 21-2 is executed, (1) the operand reading of the first element of the instruction 22-1 is started at timing_11 which is one clock later, (2) the instruction Characteristic is that the reading of the operand of 22-1 is completed for six elements.

By the above operation, the retired instruction of the preceding instruction is invalidated in the case of an instruction in which the write destination register number matches between the instructions and the VL length is the same as in the instruction sequence of the instructions 11 and 12. By doing so, it is possible to reduce the RAM port contention probability, and to increase the probability that the execution of the subsequent operation instruction can be started so that there is no unused time of the operation unit.
In addition, it is possible to reduce the data change rate by executing only necessary instructions while ensuring consistency in executing the instructions.

(Other embodiments)
In the first embodiment, the vector register 303 of the vector register 303 is composed of four 1-port RAMs, and is configured to perform a read operation and a write operation using ports assigned in a time division manner. Can be constituted by a two-port RAM capable of simultaneously performing a read operation and a write operation. In this case, there is no conflict between the read operation and the retire instruction processing operation, but since there is a case where the vector load instruction processing and the retire instruction processing conflict, the retire instruction invalidation is effective in improving the performance.

  When configuring a vector register from a 2-port RAM, it is possible to adopt a configuration in which all elements of the vector register number in one RAM are stored. In this case, it is necessary to read from a plurality of RAMs in a time-sharing manner. In this case, since the RAM write port usage time can be reduced, disabling the retire instruction is effective in improving the performance.

  In the present embodiment, the vector register is composed of four RAMs. However, an apparatus composed of five or more RAMs is also effective in improving performance.

  In the first embodiment, there are two processing instructions, that is, an operation processing instruction until a vector instruction is stored in a temporary register for storing operation results, and an operation result transfer instruction (retirement instruction) for transferring operation results from a temporary register area for storing operation results to a register. In this example, the instruction issuance waiting buffer unit 204 is buffered in separate records. If invalidation / invalidation prohibition can be controlled in each unit divided into two, separate records are provided. There is no need to do so, and the instruction divided into two may be stored in one record.

  In the description of the first embodiment, it is assumed that the inter-instruction dependency analysis unit 202, the instruction decomposition / rename processing unit 203, and the instruction issuance standby buffer unit 204 each require one clock time. These processes may be performed with one clock. The same applies to the processing in the same VR write recognition unit 208, TR number use recognition unit 209, retired instruction invalidation processing unit 210, and instruction issue standby buffer unit 204.

Although the operation of the vector store instruction is not described in the first embodiment, the store instruction is not renamed as a temporary register in the configuration of the first embodiment. To the retired instruction invalidation processing unit 210, it is possible to deal with vector store instructions while maintaining instruction consistency.
The instruction issue control unit can cope with an Out-of-Order or In-Order control method as long as consistency between instructions is maintained.

  The same VR write recognizing unit 208 can enable the invalidation prohibition flag of the preceding retired instruction by detecting that the latest arithmetic instruction and the VL length have changed, but the vector mask has been updated. It is also possible to cope with a masked operation instruction by adding a function for detecting. At this time, when the same VR write recognizing unit 208 identifies the vector mask update instruction, the retired instruction invalidation prohibition signal is sent to the TR number use recognizing unit 209.

  As described above, any of the above embodiments has a vector arithmetic unit capable of continuous execution, a vector register composed of a plurality of RAMs, and a temporary register capable of temporarily storing the output result of the vector arithmetic unit. When a vector operation instruction is executed, the vector is divided into an operation for temporarily storing the vector operation result in the temporary register and an operation for reading the operation result from the temporary register and transferring the operation result to the vector register. The present invention can be applied to a processing device, particularly a vector processing device using a device (for example, the vector operation unit 3) in which a RAM write port constituting a vector register competes with a vector load instruction, a vector transfer instruction, or the like.

  In particular, when issuing a vector instruction, the operation instruction until the vector instruction is stored in the temporary register for storing the operation result after the vector operation instruction is renamed using the temporary register, and the temporary register for storing the operation result Is divided into two operation result transfer instructions for transferring the operation result from the register to the register and stored in the instruction issue standby buffer means (for example, the instruction issue standby buffer unit 204 in FIG. 1), and then issued after the instruction issue check is performed. This can be applied to a case where instruction issue control means (for example, the vector instruction control unit 2 in FIG. 1) is provided.

  Specifically, when it is defined as an instruction calculation result transfer instruction (retired instruction) that reads the calculation result from the temporary register and transfers the calculation result to the vector register, the write destination vector register between the vector calculation instructions is analyzed. Then, an instruction stored in the same vector register is detected, and control is performed so as to suppress the issue of the retired instruction by invalidating the retired instruction of the preceding vector operation instruction. These processes can be realized by the instruction analysis unit 41, the standby instruction control unit 42, and the instruction issue standby buffer unit 204 in FIG. More specifically, the inter-instruction dependency analysis unit 202, the instruction disassembly and rename processing unit 203, the instruction issue standby buffer unit 204, the same VR write recognition unit 208, the TR number use recognition unit 209, and the retired instruction invalid in FIG. This is realized by the coordination processing unit 210 operating in cooperation.

  In the vector processing apparatus, the standby instruction control means 42 compares the means for holding the VL length information of the latest vector operation instruction with the VL length information of the subsequent instruction and the VL length information of the latest vector operation instruction. When the VL length is detected to be small, a retire instruction invalidation prohibition signal is generated so as not to invalidate the retirement instruction of the preceding instruction. Specifically, this is realized by the same VR write recognizing unit 208, the TR number use recognizing unit 209, and the retired instruction invalidation processing unit 210 of FIG.

Further, in the vector processing apparatus, the standby instruction control means 42 checks the operand specification of the arithmetic instruction after being renamed using the temporary register, and if there is an operand that is not renamed in the temporary register, it is not renamed. A retire instruction invalidation prohibition signal is generated so as not to invalidate the retirement instruction of the preceding instruction written to the vector register.
More specifically, the same VR write recognizing unit 208, TR number use recognizing unit 209, retired instruction invalidation processing unit 210, and instruction issuance waiting buffer unit 204 in FIG.

  Also, in the vector processing unit, when buffering the standby instruction instruction, the arithmetic processing instruction until the vector arithmetic instruction is stored in the temporary register area for storing the arithmetic result, and the arithmetic operation is performed on the register from the temporary register area for storing the arithmetic result. Means capable of distinguishing and storing the calculation result transfer instruction (retire instruction) for transferring the result and a flag for prohibiting invalidation of the retire instruction are provided. Further, when the flag for prohibiting retirement instruction invalidation is valid, a function for invalidating the corresponding retirement instruction even when a retirement instruction invalidation instruction is given is provided. Specifically, this is realized by the instruction issue standby buffer unit 204 of FIG.

  As described above, according to one aspect of the embodiment of the present invention, the performance of the entire system can be improved. The reason for this is that in the case of instructions where the write destination register numbers match between instructions and the VL length is the same, the retired instruction of the preceding instruction is invalidated to reduce the RAM port contention probability. By increasing the probability that execution of the subsequent operation instruction can be started so that there is no unused time of the operation unit. In other words, by analyzing the write destination vector register between the vector operation instructions and detecting the instruction stored in the same vector register, the instruction consistency is maintained by providing means for invalidating the retirement instruction of the preceding vector operation instruction. It is possible to reduce the frequency of use of the write path to the vector register.

  In addition, the power consumption of the system can be reduced. The reason is that it is possible to reduce the data change rate by executing only necessary instructions while ensuring consistency in executing the instructions.

  Each of the above embodiments can be applied to an arithmetic processing device, particularly a vector processing device.

  In addition, this invention is not limited to embodiment shown above. Within the scope of the present invention, it is possible to change, add, or convert each element of the above-described embodiment to a content that can be easily considered by those skilled in the art.

It is a block diagram which shows the outline of the instruction issue mechanism of the vector processing apparatus which concerns on Embodiment 1 of this invention. It is a figure which shows an example of a rename table. It is a block diagram which shows the structural example of a vector pipe part. It is a figure which shows an example of a vector register data element storage image. It is a figure which shows an example of a temporary register data element storage image. It is a figure which shows the example of a state which stored the command sequence of the command 1 in the command issue waiting buffer. It is a time chart which shows the example of execution of the vector instruction of the instruction 1 in one vector operation pipe part. When executing instructions 11 and 12, it is a diagram showing a flow of processing in the VIC (initial state T). FIG. 11 is a diagram illustrating a flow of processing in the VIC when instructions 11 and 12 are executed (clock T + 1). FIG. 11 is a diagram showing a flow of processing in the VIC when instructions 11 and 12 are executed (clock T + 2). When instructions 11 and 12 are executed, it is a figure which shows the flow of a process in VIC (clock T + 3). When instructions 11 and 12 are executed, it is a figure which shows the flow of a process in VIC (clock T + 4). When instructions 11 and 12 are executed, it is a figure which shows the flow of a process in VIC (clock T + 5). When instructions 11 and 12 are executed, it is a figure which shows the flow of a process in VIC (clock T + 6). FIG. 11 is a diagram showing a flow of processing in the VIC when instructions 11 and 12 are executed (clock T + 7). It is a figure which shows the example of a state immediately after storing the instruction sequence of the instructions 11 and 12 in the instruction issue waiting buffer part. FIG. 9B is a diagram illustrating a state example of the instruction issue waiting buffer unit after the retirement instruction is invalidated from the state of FIG. 9A. It is a time chart which shows the execution example of two vector instructions with the same number of elements in one vector operation pipe part. FIG. 5 is a diagram showing a flow of processing in a VIC when executing instructions 21 and 22 (initial state T). FIG. 11 is a diagram showing a flow of processing in the VIC when instructions 21 and 22 are executed (clock T + 1). FIG. 11 is a diagram showing a flow of processing in the VIC when instructions 21 and 22 are executed (clock T + 2). FIG. 11 is a diagram showing a flow of processing in the VIC when instructions 21 and 22 are executed (clock T + 3). FIG. 11 is a diagram showing a flow of processing in the VIC when instructions 21 and 22 are executed (clock T + 4). FIG. 11 is a diagram showing a flow of processing in the VIC when instructions 21 and 22 are executed (clock T + 5). FIG. 11 is a diagram showing a flow of processing in the VIC when instructions 21 and 22 are executed (clock T + 6). FIG. 11 is a diagram showing a flow of processing in the VIC when instructions 21 and 22 are executed (clock T + 7). It is a figure which shows the example of a state which stored the instruction sequence of the instructions 21 and 22 in the instruction issue waiting buffer part. It is a time chart which shows the example of execution of two vector instructions from which the number of elements differs in one vector operation pipe part.

Explanation of symbols

1 Scalar processing unit (SPU)
2 Vector instruction control unit (VIC)
3 Vector operation part 41 Instruction analysis means 42 Standby instruction control means 43 Instruction issue management means 30 to 37 Vector operation pipe part (VPP)
201 Vector instruction buffer unit 202 Inter-instruction dependency analysis unit 203 Instruction decomposition and rename processing unit 204 Instruction issue waiting buffer unit 205 Instruction issue check unit 206 Instruction issue unit 207 Pass busy management unit 208 Same VR write recognition unit 209 TR number use recognition unit 210 Retired Instruction Invalidation Processing Unit 301 Load Data Supply Unit 302 Register Input Crossbar 303 Vector Register 304 Register Output Crossbar 305 Timing Adjustment FF
306 2-input selector 307 2-input selector 308 arithmetic unit 309 temporary register 310 store data sending unit 311 pipeline control unit

Claims (5)

Vector instruction control means for accepting vector instructions and managing the issue of vector instructions;
Accepts a vector instruction issued from the vector instruction control means, and uses a vector register to store a vector instruction, an operation processing instruction for temporarily storing the operation result in a temporary register, and an operation result stored in the temporary register to the vector register A vector processing device comprising vector operation means for executing the operation result transfer instruction to be decomposed and transferred,
The vector instruction control means includes
Instruction issue waiting buffer means for storing the execution waiting vector instruction in a state of being decomposed into an operation processing instruction and an operation result transfer instruction;
Accepts a vector instruction, determines a temporary register to be used by the accepted vector instruction, and if a register number designated as an operand of the accepted vector instruction matches a temporary register, the operand register of the accepted vector instruction is Instruction analysis means for renaming a temporary register and separating the received vector instruction and the renamed vector instruction into the operation processing instruction and the operation result transfer instruction and storing them in the instruction issue waiting buffer means When,
Analyzes whether the write destination vector register is the same among the execution-waiting vector instructions, detects a previously executed arithmetic processing instruction stored in the same vector register, and performs an arithmetic operation corresponding to the detected arithmetic processing instruction Standby command control means for canceling result transfer command issuance,
An instruction issuance management means for managing the issuance of the execution waiting vector instruction ;
The standby instruction control means holds the number of elements of the vector instruction received last time, and when the number of elements of the newly received vector instruction is smaller than the number of elements of the vector instruction received last time, A vector processing apparatus that outputs an invalidation prohibition signal that prohibits the issuance of an issuance . The standby instruction control means is a vector instruction to be executed in advance if the arithmetic processing instruction of the vector instruction renamed by the instruction analyzing means is analyzed and the operand designation of the arithmetic processing instruction is not renamed to a temporary register and, the vector instruction to be written into the vector register which is not renamed, vector processing apparatus according to claim 1, wherein the outputting the disable inhibition signal. The instruction issue waiting buffer means associates a flag indicating whether or not the invalidation prohibition signal is output in addition to the arithmetic processing instruction and the arithmetic result transfer instruction in association with the arithmetic processing instruction and the arithmetic result transfer instruction. 3. The vector processing apparatus according to claim 1, further comprising a storage area. 4. The vector processing apparatus according to claim 3, wherein the instruction issue management means issues the operation result transfer instruction when the flag indicates the output of the invalidation prohibition signal . Waiting for instruction issuance to store the execution waiting vector instruction in a state of being decomposed into an operation processing instruction for temporarily storing the operation result in the temporary register and an operation result transfer instruction for transferring the operation result stored in the temporary register to the vector register. A vector processing method comprising buffer means,
Accepts a vector instruction, determines a temporary register used by the accepted vector instruction;
If the register number specified in the operand of the accepted vector instruction matches a temporary register, the operand register of the accepted vector instruction is renamed to the temporary register;
For any of the received vector instruction and the renamed vector instruction, the operation processing instruction and the operation result transfer instruction are separated and stored in the instruction issue waiting buffer means,
Analyzes whether the write destination vector register is the same among the execution vector instructions,
Detecting a processing instruction to be executed in advance, which is stored in the same vector register, stops issuing an operation result transfer instruction corresponding to the detected processing instruction,
Managing issuance of the execution waiting vector instruction, and outputting to a vector operation means for executing the vector instruction ,
The step of detecting the arithmetic processing instruction executed in advance holds the number of elements of the previously received vector instruction, and the number of elements of the newly received vector instruction becomes smaller than the number of elements of the previously received vector instruction. A vector processing method for outputting an invalidation prohibiting signal for prohibiting the issuance of an operation result transfer instruction .

Images