JP5398664B2 - Semiconductor memory - Google Patents

Description

  The present invention relates to leveling of current consumption during a write / read operation of a semiconductor memory.

  A semiconductor memory (hereinafter also referred to as “memory” as appropriate) writes data to the memory cell array in response to a request from the system side (host). At this time, a write command is issued from the host to the semiconductor memory, and a data mask signal (hereinafter also simply referred to as “mask signal”) is transferred together with the data. The semiconductor memory writes the transferred data to the memory cell array. At this time, the semiconductor memory controls whether data is actually written in the memory cell array according to the data mask signal. A semiconductor memory having a large number of data bits controls a data signal (DQ) input from the outside by a mask signal (DM) input simultaneously.

  For example, Patent Document 1 discloses a technique related to mask processing of a semiconductor memory. FIG. 10 is a schematic block diagram showing an internal configuration and a connection configuration of a part of the storage device disclosed in Patent Document 1. As shown in FIG. The storage device has a data mask operation during writing. For example, Patent Document 1 describes a general memory mask operation as follows with reference to FIG. “The data mask unit 700 is connected to the external input terminals of the data masks DM0,..., DM15, and is connected to the external input / output terminals for the data signals DQ0,. Further, the data mask unit 700 includes one data mask signal latch circuit 71 for each external input terminal for the data mask signals DM0,..., DM15, and a data signal input / output buffer circuit 72 for data signals. One set of external input / output terminals corresponding to 8 bits is provided for each set, and each data mask signal latch circuit 71 and data signal input / output buffer circuit 72 receives a clock signal CLK. By grouping data signals every few bits and controlling whether or not to mask, the number of external input terminals required for masking can be reduced. And, it is masked in the group has been fixed. "

  In Patent Document 1, regarding the general masking operation shown in FIG. 10, “whether to mask each data signal in burst reading or burst writing of a data signal without increasing the external input terminal for the data mask signal. This makes it possible to select a different mask for each bit of each data signal. Then, as a solving means, referring to the drawing shown in FIG. 11, “the mask pattern signal stored in the mask register circuit 911 is used based on the mask instruction signal input via the external input terminal 917 for the address signal. The read data converter circuit 916a and the write data converter circuit 916c select whether or not to mask each data signal for burst reading or burst writing, and convert the data signal. Is output to and stored in the memory cell 950, and is output to the external input / output terminal 917 for data signals at the time of reading. "

Here, a configuration example of a general semiconductor memory is shown, and an outline of the operation will be described. FIG. 12 is a block diagram illustrating a configuration example of a general semiconductor memory. Here, a configuration example of a DRAM (Dynamic Random Access Memory) core (hereinafter referred to as a memory core) is shown as an example of a semiconductor memory.
The memory core includes a plurality of memory cells (MEMORY CELL) 1, a row decoder (ROW DEC) 2, a column decoder (COL DEC) 3, a sense-up unit (sense amplifier / Y switch: SENSE AMP / YSW) 4, a read / write unit (Data amplifier / write amplifier: DATA AMP / WRITE AMP) 5, control unit (address, command, timing controller: ADDRESS, COMMAND, TIMING CONTROLLER) 6, and data mask signal input / output unit (data interface / data mask: DATA I / O, DATA MASK) 7. In addition, a clock signal, an address signal (row address signal, column address signal), and a command signal are input to the memory core via the bus 8. Further, the data signal DQ and the mask signal DM are input to the memory core via the bus 8. Here, detailed description of each component is omitted.

The operation of writing data to the semiconductor memory using the system side that operates the memory core as a host will be described. The host inputs a clock signal, an address signal, a command signal (write command, read command), a data signal DQ, and a mask signal DM to the memory core via the bus 8.
For example, when writing data to the memory, the host outputs a write command to the memory core and outputs a data signal DQ and a mask signal DM to the memory core.

In the memory core, when a write command is input from the host via the bus 8 to the control unit 6, the data signal DQ and the mask signal DM output from the host 20 via the bus 8 are set as a data mask. The signal is input to the signal input / output unit 7. A data write area of the memory cell array is controlled by a mask signal DM.
The data mask signal input / output unit 7 masks the data signal DQ with the mask signal DM and outputs it to the read / write unit 5. The read / write unit 5 writes the data signal DQ controlled by the mask signal DM (whether or not writing is possible) to the memory cell 1 via the sense amplifier unit 4. At this time, the mask operation of the read / write unit 5, specifically, the write amplifier of the read / write unit 5, is controlled by the mask signal DM.

  In the mask operation of the write amplifier, as described with reference to FIG. 10, it is assumed that a 1-bit mask signal is associated with a data signal of a plurality of bits. When the mask signal indicates a mask state, the data signal associated with the mask signal is not written. Therefore, the enable signal for activating the write amplifier is canceled by the mask signal DM, and the write amplifier is not activated. On the other hand, when the mask signal indicates mask release (non-mask state), the enable signal becomes valid and the write amplifier is activated.

  Here, for example, when the value of the mask signal DM is “H”, it is mask processing (internally cancels the enable signal of the write amplifier), and when it is “L”, the mask is released (the enable signal of the write amplifier is valid). ). Depending on whether the value of the mask signal is “H / L”, the mask operation of the write amplifier is mask processing if it is “H”, and mask release if it is “L”.

  In the memory core, a default state is set in advance for the mask signal. As the default state of the mask signal, “mask state” or “non-mask state” is uniquely designed and set. For example, the memory shown in FIG. 10 has a configuration in which the mask signal DM is assigned to every 8DQ (every 8IO) in a 128DQ configuration (128IO). In the mask signal DM, a mask signal in a default state of “H” or “L” is set. Accordingly, the 128 data signals are set to a masked state or a non-masked state every 8DQ.

In recent years, there has been provided a semiconductor memory that adapts the operation specifications (internal data configuration) of the semiconductor memory according to the external data configuration and burst length specified by the host. When using such a semiconductor memory, the host outputs a mode register set (MDRS: Mode Register Set) command to the semiconductor memory when starting to use the memory. The semiconductor memory sets the internal data configuration of the semiconductor memory according to the MDRS command.
As described above, the default state of the mask signal is set in the semiconductor memory. However, according to the external data configuration set by the host, the number of bits of the mask signal to be operated in the first access for accessing the memory cell first is set. Different.

  Until now, in a semiconductor memory, the operation current in the memory cell array occupies most of the current consumption, such as the column selection operation and the word selection operation of the memory cell array, or the sense operation by the sense amplifier. In recent years, the operation unit of a memory cell array has been reduced for speeding up. For example, word driver and sense operation areas are reduced by dividing the memory cell array. Along with this, the ratio of the above-described operation to the entire current consumption itself is decreasing.

  On the other hand, in a semiconductor memory, the data bandwidth is increasing in order to improve its performance. Along with this, the number of data processed at one time increases, and the number of data handled by the internal bus (IO) itself and the mask signal for masking the data signal increase. Furthermore, as the memory capacity increases, the chip area increases. As a result, the internal bus of the data signal and the mask signal increases the current consumption for transmitting the data signal and the mask signal by extending the wiring of the wiring itself.

  Under such circumstances, it has become desirable not only to reduce the operating current of the memory cell array, but also to reduce the signal transmission current for transmitting data signals and mask signals. This is because the ratio of the signal transmission current to the consumption current is large. In particular, the semiconductor memory is unstable in the first operation (1st access) after the power is turned on or reset. For this reason, in semiconductor memories, characteristic failures often occur due to the reaction speed of the internal power supply, power supply drop due to current consumption in the initial setting, or ground noise.

JP 2009-187615 A

  When the semiconductor memory has a product specification having multiple IO (Input-Output), the semiconductor memory can set its internal data configuration according to the external data configuration and burst length specified by the host. it can. Here, the product specification having multiple IOs means a specification in which the semiconductor memory has many IO terminals. At this time, the operation specifications of the semiconductor memory differ depending on the number of IOs and the number of IOs using a small number of IO terminals. Since the semiconductor memory covers operation specifications from many IOs to few IOs, the operation specifications are switched according to the designation of the host. At this time, the mask signal also needs to be switched according to the operation specifications. Specifically, when the mask signal setting corresponding to the operation specification to be set is different from the default state of the mask signal, the number of mask signals to be operated increases.

  This occurs because the default state of the mask signal is fixed to the mask state “H” or the non-mask state “L”, and is not an optimal default state corresponding to the operation specifications. . For example, depending on the operation specifications, all the mask signals are operated from “H” to “L”. At this time, since the mask signal performs switching, an operating current flows. In the first access, consuming a large current by switching the mask signal results in an operation delay or malfunction. Therefore, from the viewpoint of stable operation and reduction of current consumption, it is preferable to reduce the number of mask signals to be switched according to operation specifications.

  As described above, since the number of mask signals that temporarily operate increases, it is not possible to level the current consumption timing. As a result, when accessing the semiconductor memory, there is a problem that it is not possible to reduce the peak current at which the current consumption temporarily increases.

One aspect of a semiconductor memory according to the present invention includes a memory cell array and a data mask controller. The data mask control unit outputs an internal mask signal for controlling data exchange between the memory cell array and the data input / output contact. Further, the data mask control unit makes the logical value of the standby state of the internal mask signal variable according to a default mask signal input from the outside or generated internally.
The data mask control unit makes the logical value of the standby state of the internal mask signal variable. In other words, the data mask controller can change the default state of the internal mask signal before the first access is performed from the host. At this time, the data mask control unit sets the internal mask signal so as to reduce the switching operation of the internal mask signal in the first access.

  According to the present invention, when a semiconductor memory is accessed, it is possible to reduce a peak current that temporarily increases current consumption.

1 is a block diagram illustrating a configuration example of a semiconductor memory according to a first embodiment of the present invention. It is a figure which shows the condition where a mask signal changes when a general semiconductor memory receives the 1st command which accesses a memory cell array. FIG. 3 is a diagram illustrating an operation rate of a mask signal in consideration of the probability that a mask process is instructed from a host in addition to the transition of the mask signal illustrated in FIG. 2. It is a figure which shows the operation example at the time of maintaining the default state of an internal mask signal in the operation | movement specification of Config1 of the semiconductor memory of this embodiment. It is a figure which shows the operation example at the time of changing the default state of an internal mask signal in the operation | movement specification of Config1 of the semiconductor memory of this embodiment. It is a figure which shows the operation example when not performing the default process of a mask signal in the operation specification of Config2-4 of the semiconductor memory of this embodiment. It is the figure which showed the operation rate of the mask signal in consideration of the probability that the mask processing is instructed from the host in the transition of the mask signal of this embodiment. It is a control schematic diagram which shows an example of the process which produces | generates MASK2. FIG. 6 is a block diagram illustrating a configuration example of a semiconductor memory according to a second embodiment. FIG. 10 is a block diagram illustrating another configuration example of the semiconductor memory according to the second embodiment. FIG. 3 is a schematic block diagram showing an internal configuration and a connection configuration of a part of a storage device disclosed in Patent Document 1. 10 is a block diagram showing a configuration of a part of a semiconductor memory device disclosed in Patent Document 1. FIG. It is a block diagram which shows the structural example of a general memory core.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. For clarity of explanation, the following description and drawings are omitted and simplified as appropriate. In the drawings, components having the same configuration or function and corresponding parts are denoted by the same reference numerals and description thereof is omitted.

  The present invention can be applied to a semiconductor memory that can handle a plurality of data configurations (word configurations). The semiconductor memory that can handle a plurality of data configurations is, for example, a semiconductor memory that has a product specification of a multi-IO configuration and can set operation specifications according to a plurality of product modes. The product mode is information notified from the host to the semiconductor memory, and is information determined according to the external data configuration and burst length of the host. Hereinafter, in order to facilitate explanation, the data configuration adopted by the host may be referred to as “external data configuration”, and the data configuration of the semiconductor memory may be referred to as “internal data configuration”.

  When the semiconductor memory is used, the host operates according to at least one specification among a plurality of product modes. The semiconductor memory sets an internal data configuration according to at least one product mode. For example, when a mode register setting (MDRS) command is notified, the semiconductor memory sets the internal data configuration according to the product mode notified together with the mode setting command. When the internal data configuration is set, the semiconductor memory operates according to the operation specification corresponding to the product mode. The product mode will be described in detail later.

A semiconductor memory having a multi-IO configuration includes a large number of data input / output contacts, and exchanges data between the memory cell array and the data input / output contacts. At this time, the semiconductor memory controls transmission / reception of the data using a mask signal (data mask signal). Here, the data input / output contact is an external terminal of the semiconductor memory.
The semiconductor memory according to the present invention changes the default state (for example, H: mask state, L: non-mask state) of the mask signal based on the operation specification and a signal received from the host. In other words, the logical value of the standby state of the mask signal is made variable. This provides means for reducing the number of mask signals that operate at the time of the first access (at the time of the first access).
The semiconductor memory receives various information such as commands, address signals, or product modes from the outside. In the following description, the outside of the semiconductor memory will be referred to as “host”, but the case of receiving information from other than the host is not excluded. The host is a device that uses a semiconductor memory, for example, a device that outputs an instruction such as a command to the semiconductor memory. The host is also called the system side.

(Embodiment 1)
FIG. 1 is a block diagram showing a configuration example of a semiconductor memory according to Embodiment 1 of the present invention. The semiconductor memory (memory core) 10 includes a memory cell array 11, a row decoder 12, a column decoder 13, a control unit 16, and a data mask signal input / output unit (DATA I / O, DATA MASK) 17. Further, a clock signal, an address signal (row address signal, column address signal), a command signal, and the like are input from the host 20 to the semiconductor memory 10 via the bus 8. The column address signal is also called a Y address. Further, the data signal DQ and the mask signal DM are input from the host 20 to the data mask signal input / output unit 17 in the semiconductor memory 10 via the bus 8. FIG. 1 shows an example in which the column decoder 13 and the data / mask signal input / output unit 17 constitute the data mask control unit 101.

Here, it is assumed that the mask signal uses “H” as a mask state for performing mask processing and “L” as a non-mask state for performing mask release. The mask signal can take any value of a mask state (H), a non-mask state (L), or an indefinite state (a value is not determined). The default value of the mask signal held by the semiconductor memory is premised on the mask state (H).
In the present specification, the mask signal may be distinguished by using the following names depending on the location where the mask signal exists and the change of the value. However, the functions, possible values, and the like as the mask signal are the same, and when the term “mask signal” is simply used, it is assumed that reference is made to matters that do not need to be distinguished.

The “mask signal DM” or “external mask signal” is a mask signal input from the outside of the semiconductor memory 10. For example, the semiconductor memory 10 receives an external mask signal from the host 20. The external mask signal indicates a logical value of the data mask input (designated) from the outside.
The “internal mask signal” is a mask signal generated inside the semiconductor memory 10. The internal mask signal indicates a logical value that controls data exchange between the memory cell array and the data input / output contact (external terminal).

In the following description, the external mask signal is also expressed as “MASK1”, and the internal mask signal is also expressed as “MASK2”.
The internal mask signal is generated in the data mask control unit 101. Specifically, in the configuration example of FIG. 1, a case will be described in which the column decoder 13 generates an internal mask signal in the data mask control unit 101. However, the present invention is not limited to this configuration. For example, the data mask signal input / output unit 17 may generate an internal mask signal.

Subsequently, each component will be described.
The memory cell array 11 has a plurality of memory cells formed at intersections of a plurality of word lines and a plurality of bit lines. Each memory cell stores data. Each memory cell is alternatively selected by selecting a word line and a bit line. In FIG. 1, an activated region of the memory cell array 11 is shown as an active area 14.
In FIG. 1, the sense amplifier unit 4 and the read / write unit 5 shown in FIG. 12 are not clearly shown, but it is assumed that the semiconductor memory 10 also has these functions in the memory cell array 11.

  The row decoder 12 selects a word line to be activated from a plurality of word lines. Specifically, the row decoder 12 decodes a row address signal input via the bus 8 and activates a word line corresponding to the decoded address among a plurality of word lines of the memory cell array (word line). Selection process).

  The column decoder 13 outputs to the memory cell array 11 an internal mask signal (in this case, corresponding to “MASK2” described above) for selecting a bit line to be activated among a plurality of bit lines (bit line selection processing). . Specifically, the column decoder 13 generates an internal mask signal using at least one of a default mask signal (DEF_MASK), an external mask signal, and a column address signal, which will be described later, and generates the generated internal mask. A signal is output to the memory cell array 11. After the internal mask signal is output from the column decoder 13 to the memory cell array 11, it is used in a sense amplifier unit (sense amplifier) or a read / write unit (write amplifier / data amplifier) not shown in FIG.

The control unit 16 controls the operations of the row decoder 12, the column decoder 13, and the data / mask signal input / output unit 17 according to a clock signal, an address signal, a command signal, and the like input from the bus 8. The control unit 16 outputs a row address signal to the row decoder 12 and outputs a column address signal or the like to the column decoder 13. The control unit 16 outputs a write enable signal (WEN) to the memory cell array 11, the column decoder 13, the data / mask signal input / output unit 17, and the like. The control unit 16 includes a default mask signal generation unit 19.
FIG. 1 shows an example in which the control unit 16 includes the default mask signal generation unit 19, but the control unit 16 may be disposed in another location as long as it is disposed in the semiconductor memory 10.

The default mask signal generation unit 19 generates a default mask signal using the product mode notified from the host 20 and outputs the default mask signal to the column decoder 13.
The default mask signal is a signal indicating whether or not to change the default state of the internal mask signal. Here, it is assumed that the default mask signal uses, as values, active (H) indicating a change in the default state of the internal mask signal and inactive (L) indicating no change. When setting the internal data configuration of the device itself, the default mask signal generation unit 19 sets the default mask so that the change of the value of the internal mask signal is small in the next access to the memory cell array 11 requested from the host 20. Generate a signal. In other words, the default mask signal holds a value that sets the logical value in the standby state of the internal mask signal so that the change in the logical value of the internal mask signal is reduced in the first access to the memory cell array 11. To do.

The data mask signal input / output unit 17 holds a data signal read from the memory cell array 11 and outputs it to the host 20 via the bus 8 at the time of reading. The data mask signal input / output unit 17 holds the data signal DQ and the mask signal DM input from the bus 8 in a register at the time of writing. Then, the mask signal DM is decoded to generate an external mask signal (MASK1), which is output to the column decoder 13. Further, the data signal DQ is output to the memory cell array 11 in response to the write enable signal.
Between the data mask signal input / output unit 17 and the memory cell array 11, a read / write bus (RWBS 72IO) having 72IO for inputting / outputting 72 data signals is provided. The input / output number 72IO will be described later.

  Here, the internal data configuration (data configuration of the memory core) of the semiconductor memory 10 to which the present invention is applied will be described. The semiconductor memory 10 has product specifications including the number of data signal bits (DQ number or IO number) operating at a time and the number of internal mask signal bits (DM number) for each product. In the following description, in the description regarding the data configuration, the information specifying the internal data configuration may be referred to as “internal DQ number” or “internal IO number”. “Internal” indicates information regarding product specifications of the semiconductor memory 10 itself. In contrast, information specifying the external data configuration used when the host 20 accesses the semiconductor memory 10 is referred to as “external DQ number” or “external IO number”. Thereby, the data configuration (internal data configuration) of the semiconductor memory is distinguished from the data configuration (external data configuration) used by the host.

  Subsequently, after describing the product mode and the array configuration of the semiconductor memory 10, the operation of the mask process will be described. In the following, a specific number of bits is used for easy explanation. In the present embodiment, a semiconductor memory 10 in which the number of bits of a data signal is an internal 144DQ (144IO) configuration and the number of bits of an internal mask signal is 16DM will be described as an example. This is a configuration having an internal mask signal every 9DQ. However, without being limited to this configuration, for example, an internal 128DQ configuration and 16DM (having an internal mask signal for every 8DQ) disclosed in Patent Document 1 may be used.

First, the product mode will be described by taking, as an example, the semiconductor memory 10 having the internal 144DQ (144IO) configuration and 16DM (internal mask signal) product specifications.
The product mode has one external data configuration (the number of external DQs, that is, the number of external DQ terminals, for example, x36, x18, x9) that can be adopted by the host 20 according to the product specifications of the semiconductor memory 10. This is a specification for setting the burst length (BL, for example, BL2, 4) of the data signal DQ to be processed by READ or WRITE.
The external data configuration specifies the number of data input / output of data among the external DQ terminals provided by the semiconductor memory 10 when accessing the semiconductor memory 10 according to the number of external DQs (IO number).
The burst length is a numerical value indicating how many data are output to one external DQ terminal, that is, the number of data output from the external DQ in one access.

Here, the number of internal DQs is the maximum number of DQs operable within the semiconductor memory 10, and the number of external DQs is the number of DQs operable when the semiconductor memory 10 inputs / outputs data to / from the outside (host 20). It is.
For example, when the internal 144DQ and 16DM semiconductor memory 10 is used, the following product mode is possible.
External DQ number: x36, x18, x9
BL: 2, 4
For example, in the product mode in which the number of external DQs is x36 and the burst length is 4, that is, when there are 36 external DQ terminals and 4 data are related to one external DQ terminal, the semiconductor memory 10 In total, 36 × 4 = 144 data is processed inside the memory. This is 144 data since data is input / output four times to / from one external DQ terminal in one access.

  As specific examples of typical product modes, there are four types of Config1-4. Config1 is a product mode in which the maximum 144IO (× 36 and BL4) operates in the memory cell array. Config2 is 72IO (x18 and BL4, or x36 and BL2). Config3 is 36IO (x9 and BL4, x18 and BL2). Config4 is 18IO (x9 and BL2). Further, the data mask signal has a configuration having 1 DM for each external 9DQ. In the following description, for ease of explanation, the above-described product mode is used for explanation, but the present invention is not limited to this. Product modes vary depending on the product specifications of the semiconductor memory, and the present invention can be applied to other product modes.

  The number of internal IOs when the semiconductor memory 10 operates is determined by the combination of the external data configuration and the burst length employed by the host 20. The maximum number of data is when the external data configuration (external DQ number) is x36, BL4, and the number of operating internal IOs is 144 IOs. The minimum number of data is when the external data configuration is × 9, BL2, and the number of internal IOs that operate is 18 IOs.

  As described above, the semiconductor memory 10 has a range of product modes that can be adopted according to the product specifications of the semiconductor memory 10, specifically, the internal data configuration. The host 20 determines which product mode to use among one or more product modes provided by the semiconductor memory 10 according to its external data configuration. For this reason, the host 20 first sets the product mode to be adopted in the semiconductor memory 10 by the MDRS command after the power is turned on. The semiconductor memory 10 sets operation specifications according to the product mode, that is, according to the number of external DQs and the burst length. Therefore, the semiconductor memory 10 determines the operation specification according to the product mode adopted by the host 20.

Next, the array configuration will be described. The semiconductor memory 10 is accessed by dividing the memory cell array 11.
For example, when the above-described internal 144IO semiconductor memory 10 is accessed by being divided into 72PERs of UPPER DQ and LOWER DQ (two-array configuration), the maximum number of operation IOs in each of the memory cell arrays of UPPER DQ and LOWER DQ is 72IO. become.

Here, a product (Config1-4) capable of supporting the above-described four types of specifications as the operation specifications of the semiconductor memory 10 will be described as an example.
When the memory cell array 11 is divided and controlled as described above, the maximum operation IO number of UPPER DQ (or LOWER DQ) is 72IO, 36IO, 18IO, and 9IO in Config1-4, respectively. FIG. 1 shows an example in which the memory cell array 11 is divided into two to control 72IO. Accordingly, the semiconductor memory 10 includes 72 input / output buses (72IOBS) between the memory cell array 11 and the data mask signal input / output unit 17.

  Next, the mask processing operation of the semiconductor memory 10 will be described, particularly regarding the change in the value of the internal mask signal when the power is turned on. First, a general mask processing operation, that is, an operation when the above-described default mask signal (DEF_MASK) is not used will be described with reference to FIGS. Thereafter, the operation of the mask processing according to the first embodiment of the present invention, that is, the operation in the case of using the default mask signal will be described with reference to FIGS. 4A, 4B, and 5. FIG.

  A general mask process will be described with reference to the configuration example of FIG. Here, it is assumed that an internal mask signal is output from the column decoder 13 to the memory cell array 11. However, it is assumed that the value of the internal mask signal matches the external mask signal. In contrast, in the mask process according to the first embodiment of the present invention, the internal mask signal generated by the column decoder 13 is output to the memory cell array 11.

  FIG. 2 is a diagram illustrating a situation in which an internal mask signal changes when a general semiconductor memory receives a first command (for example, READ or WRITE) for accessing a memory cell array. When the mode register set (MDRS) is notified from the host 20, the semiconductor memory 10 sets an internal mask signal according to each product mode (Config1-4). At this time, the internal mask signal maintains the default state. Therefore, the internal mask signal operates when the first command is received.

  The value of the internal mask signal shown in FIG. 2 is the value of the internal mask signal output from the column decoder 13 to the memory cell array 11, specifically, to the active area 14 of the memory cell array 11. FIG. 2 shows a case in which 144IO in the active area 14 is divided and 72IO is operated by one access. In FIG. 2, since one internal mask signal is assigned to every 9 IO of 72IO, 72 IO is divided into 9 of 0-8, 9-17,..., 63-71 and assigned to every 9 IO. The change in the value of the internal mask signal is shown.

  In FIG. 2, the value of the internal mask signal is indicated using “H” or “L”. When “H” and “L” are connected by an arrow (for example, H → L), this indicates that the value of the internal mask signal changes in the direction indicated by the arrow. An internal mask signal indicated by either “H” or “L” indicates that the value does not change. As shown in FIG. 2, the IO that operates among the 72 IOs varies depending on the operation specifications of the product mode. A region where the value of the internal mask signal does not change indicates that the device does not operate. Whether or not the IO in the active area operates is specified by a column address signal. In other words, the column address signal is address information indicating an area where the internal mask signal must be canceled by Config1-4. For example, an area in the memory cell array 11 where a write operation is actually performed is specified by a column address signal and is not masked.

The number of external DQs and the burst length of Config1-4 are as described above, and are described in the right column of FIG. In FIG. 2, the active area to which the value of the internal mask signal changing from “H” to “L” is assigned becomes the operating IO. In an initial state such as immediately after power-on (Power ON) or immediately after reset, all 72IO of the memory core is masked. For example, when Config1 is set according to a command that determines operation specifications such as an MDRS command, the semiconductor memory 10 operates the internal mask signals for all 72Q DQs from "H" to "L" to release the mask. . In the case of Config2, the mask of 32IO designated by the column address signal is released from 72IO. Similarly, the masks of the IOs that are also activated in the Configs 3 and 4 are released.
In FIG. 2, the product mode in which the operation to change from “H” to “L” is more frequent (for example, Config1), the more current is consumed in the initial state and the initial setting.

  The column address signal is a column address that designates a column area for accessing the memory core, and is appropriately assigned according to the operation specification Config. In addition, the column address signal performs selection / non-selection control on an area for activating the array irrespective of the external mask signal. In actuality, the write amplifier control for writing data into the memory cell array 11 needs to be selected by the enable signal and not masked at the time of writing. The internal mask signal includes not only the mask signal MD (external mask signal) but also control of the column address signal of the activation area. Therefore, not only the write amplifier but also the data amplifier may control selection / non-selection at the same time.

In FIG. 2, the total number of internal mask signals is eight. In the case of Config1, 100% of the eight internal mask signals for each 9IO operate, and in the case of Config2-4, four (50%) each. Note that two (25%) and one (12.5%) operate. This point is further analyzed using FIG.
FIG. 3 is a diagram showing the operation rate of the internal mask signal by adding the probability that the mask process is instructed from the host to the transition of the internal mask signal shown in FIG. That is, in Config1-4 of FIG. 2, it is the figure which showed the case where the mask signal DM input from the host 20 to the semiconductor memory 10 was further considered in the ratio of the signal which changed from "H" to "L". FIG. 3 shows a case where, for example, the semiconductor memory 10 receives a memory access (write) in which the mask signal DM is specified from the host 20.

FIG. 3 shows the product of the value A and the value B calculated by the following equation.
A = operation rate of internal mask signal by Config = 1− (number of operation IOs by Config / total number of IOs)
B = Ratio of masking when the mask signal DM is input from the host A is the operation rate of the internal mask signal determined according to the setting of the operation specification (Config). In the example shown in FIG. 2, the total number of IOs is 72 IO, and the operation rate of the internal mask signal is 100%, 50%, 25%, and 12.5%.
B is defined as the ratio at which the internal mask signal maintains the mask by the mask control when the mask signal DM is input together with the data signal DQ from the host 20 to the semiconductor memory 10.

  For example, when Config1 is set as the product mode, as shown in FIG. 2, the internal mask signal operates from 100% “H” to “L”, and the mask for the memory cell array 11 is released. On the other hand, although it is an extreme example, when an instruction for masking the entire data signal DQ from the host 20 is received as the mask signal DM (B = 100%), all the internal mask signals in Config 1 are fixed to “H”. Thus, the mask state is maintained. The table of FIG. 3 shows the product of A and B. In this case, the operation rate indicating the rate at which the mask operates from “H” to “L” is 0%. When 25% of the data signal DQ input to the semiconductor memory 10 is masked by the mask signal DM, in the case of Config1, 75% of the internal mask signal operates from “H” to “L”, but the remaining 25% is “H”. To maintain the mask state. The same applies to Config2-4. However, the internal mask signal is considered as one for every 9DQ, and the maximum is 8DM, but for the explanation of the value B, it is simplified in this figure.

As shown in FIG. 3, when the mask signal DM is input from the host 20 to the semiconductor memory 10 and the ratio of maintaining the mask state in the semiconductor memory 10 is as low as 0 to 50% (the ratio of inputting the internal mask signal in the table) In the operation specification Config1, the internal mask signal operates from “H” to “L” by 50% or more. On the other hand, with Config2-4, the operation is 50% or less.
Conversely, when the mask signal DM is input from the host 20 to the semiconductor memory 10 and the ratio of maintaining the mask state in the semiconductor memory 10 is as high as 50% to 100%, Config1 is 50% or less, whereas Config2− 4 is 50% or more.

  This occurs because the semiconductor memory 10 having a product specification with a large number of internal DQs covers from a product mode with a large number of external DQs to a product mode with a small number of external DQs, so that the number of operating internal mask signals increases. It was. For example, assuming that the default state of the internal mask signal is the mask state (H), the semiconductor memory 10 changes all the internal mask signals from the mask state (H) to the non-mask state (L) depending on the product mode. To do. Therefore, when the operation specifications are switched according to the product mode adopted by the host 20, the number of internal mask signals to be operated increases depending on the product mode, and the operating current increases.

  This occurs because the default state of the internal mask signal in the semiconductor memory 10 is fixed to the mask state (H) and is not the optimum default state for all of Config1-4. Therefore, the default state of the internal mask signal is optimized according to the operation rate (the above-mentioned value A) according to the operation specification corresponding to the product mode and the ratio (the above-mentioned value B) that the mask signal DM is input from the host and masked. Is preferable.

In FIG. 2, when the product mode is Config1, it has been described that the internal mask signal operates from the mask state to the non-mask state (H to L). In this operation, an operating current for switching the internal mask signal flows.
As described above, in recent years, current due to an increase in the number of internal mask signals to be switched and an increase in internal wiring (routing) of signals due to an increase in memory capacity has become impossible to ignore. Since consuming a large current by switching the internal mask signal results in an operation delay or malfunction, it is desirable to reduce it from the viewpoint of stable operation and reduction of current consumption.

  Therefore, in the present embodiment, means for reducing the number of mask signals that operate at the first memory access is provided using the configuration example shown in FIG. Specifically, in a semiconductor memory with a large number of DQs corresponding to a plurality of product modes (Config) (a semiconductor memory having a multi-IO configuration), the default state of the internal mask signal is changed according to the operation specification notified from the host. To do. In other words, the logical value in the standby state of the internal mask signal is made variable. This reduces the operation rate of the mask signal in the 1st access. Details of the mask processing operation of the first embodiment will be described with reference to FIGS. 4A, 4B, and 5. FIG.

  The default mask signal generator 19 shown in FIG. 1 generates a default mask signal (hereinafter also referred to as “DEF_MASK”) when setting operation specifications according to the product mode. Further, when the semiconductor memory 10 receives the MDRS command from the host 20 (when setting the internal data configuration of the own device), the column decoder 13 changes the value of MASK2 according to the product mode and DEF_MASK. .

The default mask signal generation unit 19 sets DEF_MASK so that the number of internal mask signals that operate when the host 20 transmits a 1st access request (first access to the memory cell array 11) is reduced. That is, it is generated so as to reduce the operating current. This reduces the switching operation of the internal mask signal in the 1st access. As a result, the current consumption is leveled and the peak current during access is reduced.
Assuming that the default state of MASK2 is the mask state (H), the column decoder 13 controls the default state of MASK2 as follows when setting operation specifications in accordance with the MDRS command. When DEF_MASK is “L”, the default state of MASK2 (mask state: H) is maintained. When DEF_MASK is “H”, the default state of MASK2 is set (changed) to mask release (L).

4A, 4B, and 5 are diagrams showing an example of the mask processing operation of the semiconductor memory 10 according to the present embodiment.
4A and 4B both show a case where the semiconductor memory 10 sets the operation specification of Config 1 as a product mode. 4A shows that when DEF_MASK is set to inactive (L) and the default state of MASK2 is maintained (when the default processing is not performed), FIG. 4B shows that DEF_MASK is set to active (H) and MASK2 The case where the default state is changed (when default processing is performed) is shown. FIG. 5 shows a case where the semiconductor memory 10 sets the operation specification of CONFIG 2-4 as the product mode.
4A and 4B both show a case where the following command is transmitted from the host 20 to the semiconductor memory 10. Command: MDRS, Write / Read, Write (external mask signal is specified), RESET, MDRS, Write / Read.

  In the processing of the MDRS command in FIG. 4B, the column decoder 13 changes MASK2 from the mask state (H) in the default state to the non-mask state (L) in response to “H” of DEF_MASK. As a result, in the processing of the next 1st access and Write / Read command, the operating MASK2 becomes zero, and the operating current can be reduced. On the other hand, in FIG. 4A, in the MDRS command processing, the column decoder 13 maintains the default state of MASK2 in accordance with “L” of DEF_MASK. For this reason, in the next processing of the Write / Read command, the entire MASK 2 is operated, and an operating current is generated. The MASK 2 operating at this time is the same as the situation shown in FIG.

  As described above, in FIG. 2, in the case of Config1, all the internal mask signals are changed from the mask state to the non-mask state (H to L). On the other hand, by inverting the default value of MASK2 using DEF_MASK (inverting the default value), after the MDRS command is processed, MASK2 changes to the unmasked state in the first memory cell access. Maintain “L” to “L”.

In this way, the default mask signal generation unit 19 sets the number of bits of the internal mask signal corresponding to the number of data required for one access of the semiconductor memory 10 to the host 20 and all of the MASK2 set by the column decoder 13. A default mask signal is generated based on the comparison result with the number of bits. Specifically, the number of bits of the internal mask signal corresponding to the number of data required for one access, in other words, the number of bits of the internal mask signal used in the set operation specification is smaller than the total number of bits of MASK2. In the case (Config2-4), the internal mask signal is maintained in the mask state (default state). When the number of bits of the internal mask signal used in the set operation specification matches the total number of bits of MASK2 (Config1), the mask state of the internal mask signal is changed to mask release.
In the present embodiment, for Config2-4, since the default mask signal generator 19 does not activate DEF_MASK (H), FIG. 5 shows a case where DEF_MASK is not active (L).

  FIG. 6 is a diagram showing the operation rate of the internal mask signal by adding the probability that the mask processing is instructed from the host to the transition of the internal mask signal of the present embodiment. In FIG. 6, in the case of Config1, the default value of the internal mask signal in the chip is set in reverse by DEF_MASK, and the other Configs 2-4 are left as they are. Specifically, FIG. 6 shows the operation rate of the internal mask signal when the default state of the internal mask signal is premised on the non-mask state in Config1 and the mask state in Config2-4. Therefore, FIG. 6 shows that in the case of Config1, the operation rate shown in FIG. 3 is improved in the range of 0 to 50% (the range surrounded by the dotted line in FIG. 6) that the mask processing instruction is instructed from the host. It shows that. Specifically, when the ratio of data masked by the mask signal DM (MASK1) input from the host 20 (the above-described value B) is 0-50%, the operation rate of the internal mask signal is improved. In FIG. 3, when the probability of the mask processing being instructed from the host 20 is 0-50%, the operation is 100-50% from the mask state to the mask release (H to L). On the other hand, in FIG. 6, the operation rate can be improved as low as 0-50% (FIG. 8).

The operation of setting the default value of the internal mask signal (MASK2) in reverse by DEF_MASK is determined when determining the operation specifications of the semiconductor memory 10 according to the product mode (Config1-4) of the host 20. In the above description, as an example, a case has been described in which a DEF_MASK signal is generated when an MDRS command is received, and the default state of MASK2 is changed. However, the default state of MASK2 is implemented in “a period from when the power is turned on until the first access command is received”, in other words, “a period during which the internal data configuration of the device is set according to the product mode”. That's fine. In other words, the internal mask signal may be switched so that the switching operation of the internal mask signal is reduced at the time of the first access. For example, it may be performed until an operation command such as a WRITE / READ command is input to the memory cell array 11.
Here, the 1st access (the first command that is requested to access the memory cell array) is a command that accesses the memory cell array among commands received from the host. Therefore, the 1st access does not include a command for setting operation specifications such as an MDRS command or a RESET command.

  Further, the operation specification corresponding to the product mode is performed according to the usage status of the customer's system using the semiconductor memory 10. In the above description, an example in which DEF_MASK is generated when an MDRS command is received has been described, but the present invention is not limited to this. For example, for customers using Config1, it is also possible to set in advance by an option such as FUSE so that the default value is reversed by DEF_MASK after Power ON and reset.

Here, the operation of the above-described mask processing will be specifically described using the case where the MDRS command and the Write / Read command shown in FIG. 4B are received.
First, a case where the semiconductor memory 10 receives an MDRS command from the host 20 will be described.

The control unit 16 receives an MDRS command from the host 20 via the bus 8. At this time, the control unit 16 receives the product mode adopted by the host 20 together with the MDRS command. The control unit 16 outputs the product mode to the default mask signal generation unit 19. When receiving the product mode from the control unit 16, the default mask signal generation unit 19 generates DEF_MASK.
The default mask signal generation unit 19 holds in advance information indicating whether or not to change the default state of the internal mask signal according to the product mode. The information to be held is information for which it is determined in advance whether or not to change the default state of MASK2 in accordance with the information shown in FIG.

  For example, the default mask signal generation unit 19 may hold a combination of a product mode and a value indicating whether or not to change the default state for each of a plurality of product modes, and among the plurality of product modes, MASK2 A product mode for changing the default state of the product may be maintained. For example, in the case of the present embodiment, the default mask signal generation unit 19 may hold information that the default state of MASK2 is changed when the product mode is Config1. The default mask signal generation unit 19 may be configured to generate DEF_MASK corresponding to the product code according to the information held. Not limited to this, the default mask signal generation unit 19 may be configured to generate DEF_MASK in accordance with information regarding the product mode, which is held in other components in the semiconductor memory 10.

  The column decoder 13 inverts the default state MASK2 when DEF_MASK indicates a change in the default state. If DEF_MASK does not indicate a change in the default state, the default state MASK2 is maintained as it is.

  Next, a case where the semiconductor memory 10 receives a Write / Read command from the host 20 will be described. The control unit 16 receives a Write / Read command from the host 20 via the bus 8. At this time, in this embodiment, the default mask signal generation unit 19 does not receive the product mode from the control unit 16, and therefore maintains the value of DEF_MASK generated last time without newly generating DEF_MASK. Thereafter, the value of DEF_MASK is maintained until the semiconductor memory 10 receives an MDRS command from the host 20.

  The default mask signal generation unit 19 generates DEF_MASK not only when the semiconductor memory 10 receives the MDRS command but also when the semiconductor memory 10 performs an operation of setting the internal data configuration according to the product mode. To do. Thereafter, the value of DEF_MASK is maintained until the semiconductor memory 10 sets the internal data configuration again. In other words, the value of DEF_MASK is maintained until the internal data structure is set once and then set again. In FIG. 5B, the value of “H” is set again by the MDRS command after the RESET command.

  The column decoder 13 generates MASK2 using DEF_MASK, MASK1, and column address information.

FIG. 7 is a control schematic diagram illustrating an example of processing for generating MASK2. The configuration shown in FIG. 7 shows an example provided in the column decoder 13 in FIG.
As described above, DEF_MASK is a signal generated by the default mask signal generation unit 19. MASK 1 is an external mask signal received from the host 20 via the bus 8. The column address signal is a signal received from the host 20 via the bus 8 and designates an address for releasing the masked state (an address to be set to the unmasked state) according to the product mode. Therefore, the column decoder 13 generates MASK2 that sets the address for which unmasking is specified by MASK1 and the address for which unmasking is specified by the column address signal to be unmasked.

  MASK2 is a signal for actually controlling the memory core, and the mask processing of the memory cell array 11 is designated by MASK1, the column address signal, and DEF_MASK. MASK1 is mask information notified from the host 20, and the column address signal is information set in the product mode (here, Config1-4) and determined by address information input from the host 20. .

  As described with reference to FIGS. 2-6, when the product mode is Config1, in other words, when the number of external DQs is large, the area selected as the active area (operating area) in the operation specifications of the semiconductor memory 10 is wide. When the host 20 accesses the memory cell array 11, the column address signal is information indicating that all addresses are unmasked. Therefore, all the MASK2s are changed to the unmasked state (H to L). At this time, when the host 20 designates mask processing by an external mask signal, the designation of the mask state of MASK1 is related as a logical product. For example, when an external mask signal is input from the host 20 with an input probability of α = 0-50%, 100% -α of MASK2 operates. This is because the default state of the internal mask signal is set to “H”.

In the present embodiment, the default mask signal generation unit 19 generates DEF_MASK so as to invert the default value (mask state: H) of MASK2. Specifically, the default mask signal generation unit 19 sets DEF_MASK to active (H).
The operation of the column decoder 13 at this time is as follows. The switch 132 is configured to select either MASK1 or MASK1 inverted by the buffer 133 according to DEF_MASK. Here, the switch 132 selects the inverted MASK1 when DEF_MASK is active (H). The calculation unit 131 generates MASK2 using DEF_MASK, the inverted MASK1, and the column address signal.

Specifically, the arithmetic unit 131 calculates MASK2 according to Expression (1) when DEF_MASK is not active (L), and calculates MASK2 according to Expression (2) when DEF_MASK is active (H).
MASK2 = (MASK1) or not (column address signal) (1)
MASK2 = not (MASK1) / COL selection (= not equation (1)) (2)

When the logic of the normal default decoder is represented by Expression (1), Expression (2) used when DEF_MASK is active (H) inverts the logic of Expression (1) according to Domorgan's formula.
Because of this logic inversion, DEF_MASK is output to the switch 132 for selecting MASK1 and the arithmetic unit 131.
Expressions (1) and (2) indicate that MASK2 is generated based on whether the mask is specified by MASK1 and whether it is selected by the column address signal.

  Note that the configuration shown in FIG. 7 shows an example of a circuit configuration for generating MASK2, and is not limited to this, and other circuit configurations may be used. At this time, the circuit configuration may be any circuit configuration that inputs at least DEF_MASK, MASK1, and a column address signal and outputs MASK2. Therefore, FIG. 1 shows a configuration example in which the column decoder 13 outputs MASK2 to the memory cell array 11. However, other components may output MASK2 to the memory cell array 11. For example, the data mask signal input / output unit 17 or a component equivalent thereto may output MASK2 to the memory cell array 11.

  Furthermore, in this embodiment, the aspect which implements the process in which the column decoder 13 produces | generates MASK2 was demonstrated. This is an example of the configuration for ease of explanation, and the present invention is not limited to this. MASK2 may be generated in the semiconductor memory 10 and output to the memory cell array 11. For example, when the configuration example shown in FIG. 7 is arranged independently in the semiconductor memory 10, only the arithmetic unit 131 is arranged in the column decoder 13 and the others are arranged outside the column decoder 13, or, for example, A configuration in which everything is arranged in other components such as the data mask signal input / output unit 17 may also be used.

  According to the present embodiment, the current consumption during the first access can be reduced by controlling the default state of the internal mask signal of the semiconductor memory. For example, the default state of the internal mask signal is controlled immediately after power-on after power-on or immediately after a reset in the semiconductor memory. By controlling the default state of the internal mask signal, for example, by controlling the default value of the internal mask signal when the first operation mode is set, by the switching operation of the internal mask signal that occurs during the first write operation / read operation Current consumption can be reduced. Furthermore, it is possible to disperse the peak of current consumption by executing the switching operation of the internal mask signal when setting the operation mode. As a result, a stable operation can be obtained simultaneously with the reduction of current.

(Embodiment 2)
In the first embodiment, the case where the semiconductor memory sets the value of the default mask signal according to the product code has been described. However, in this embodiment, the case where the host specifies the value of the default mask signal will be described.
FIG. 8 is a block diagram illustrating a configuration example of the semiconductor memory according to the second embodiment. In the present embodiment, an information circuit (MASK Status) 41 accessible by the host 40 is provided. The semiconductor memory 30 is configured to directly input the value held by the information circuit 41 to the column decoder 33. The information circuit 41 holds a value corresponding to the value of DEF_MASK in the first embodiment. FIG. 8 shows an example in which the column decoder 33 and the data mask signal input / output unit 17 constitute a data mask control unit 301.

  The host 40 selects the value of DEF_MASK according to the product mode adopted by the host device. When the host 40 performs mask processing using an external mask signal, the host 40 preferably selects the value of DEF_MASK according to the number of bits to be masked by the external mask signal. Further, in the configuration example of FIG. 8, the host 40 holds the frequency of performing the mask process on the semiconductor memory 30 based on the external mask signal, and determines whether or not DEF_MASK needs to be switched according to the frequency. Then, the host 40 includes an information circuit 41 that switches DEF_MASK as appropriate according to the determination result. In FIG. 8, the semiconductor memory 30 is configured to input the value held by the information circuit 41 directly to the column decoder 33, but is not limited to this configuration. For example, the value of the information circuit 41 may be input via the bus 8. In FIG. 8, the information circuit 41 is arranged outside the host 40. However, the information circuit 41 may be arranged inside the host 40, and the host 40 may output the value of DEF_MASK to the bus 8 together with the command. .

  The semiconductor memory 30 is configured so that a value set in the information circuit 41 can be referred to via the bus 8. The column decoder 33 uses the value set in the information circuit 41 as DEF_MASK. The operation of the column decoder 33 is the same as that of the first embodiment.

  Further, the information circuit 41 may not be provided. FIG. 9 is a block diagram illustrating another configuration example of the semiconductor memory according to the second embodiment. For example, as shown in FIG. 9, the host 60 may be configured to select the value of DEF_MASK by internal processing and output DEF_MASK to the semiconductor memory 50. In this case, the host 60 may notify the semiconductor memory 50 of DEF_MASK as a parameter to be added to the MDRS command. In the semiconductor memory 50, the control unit 56 outputs DEF_MASK received from the host 40 to the column decoder 13. The operation of the column decoder 13 is the same as that of the first embodiment.

  According to the present embodiment, the host (here, the host 40 or 60, which is the same in the second embodiment hereinafter) can select the value of DEF_MASK. Thus, the default value of the internal mask signal can be flexibly changed according to the situation in which the host uses the semiconductor memory (here, the semiconductor memory 30 or 50, which is the same in the second embodiment). This is particularly effective when the host performs mask processing using an external mask signal.

  With respect to this point, the case of Config1 will be specifically described with reference to FIG. When the ratio of the external mask signal input is low (0-50%), an operation of inverting the default value of the internal mask signal (specifically, MASK2) by DEF_MASK is performed. The effect at this time is as described in the first embodiment. On the other hand, when the rate at which the external mask signal is input from the host is high (50-100%), the internal mask signal operates more than half and the efficiency is poor. In such a case, the host shown in FIG. 8 or FIG. 9 can change the rate at which the internal mask signal operates by selecting the default value of the internal mask signal. In other words, the host can change the default state of the internal mask signal of the semiconductor memory according to the external mask signal.

  Therefore, according to the configuration of the present embodiment, the ratio of the operation of the internal mask signal at the time of the first access is reduced both when 0-50% when the mask state indicated by the external mask signal is low and when it is 50-100% when it is high. can do. As a result, the operation rate at which the internal mask signal is switched during the 1st access can be reduced. As a result, current consumption can be leveled.

  In the description of FIG. 8, the semiconductor memory 30 controls the default value of the internal mask signal based on the determination result of the information circuit 41. In the description of FIG. 9, the semiconductor memory 50 controls the default value of the internal mask signal by inputting information from the host 60. Without being limited to such control, it is possible to arbitrarily perform control or test from the host 40 or 60 by inputting a command corresponding to the determination result from the outside of the semiconductor memory 30 or 50.

(Other embodiments)
In each of the above embodiments, it is assumed that the operation specifications of the semiconductor memory are set according to one product mode. However, the host may adopt two or more product modes. In this case, the semiconductor memory is set so that a part of the memory cell array 11 corresponds to the operation specification of the first product mode and the other part corresponds to the operation specification of the second product mode. In such a case, DEF_MASK is preferably set according to the number of product modes.
Therefore, when setting operation specifications according to a plurality of product modes, the semiconductor memory sets DEF_MASK corresponding to each product mode.

  As described above, according to any of the above embodiments, the switching current of the internal mask signal in the first access (write operation / read operation) can be reduced. In each of the above embodiments, the current consumption for the first access is reduced by switching the internal mask signal in advance. Thereby, the current consumption timing is leveled. This leads to a reduction in peak current when accessing the semiconductor memory. Furthermore, it is possible to reduce fluctuations in the power source and obtain stable operation.

  In addition, this invention is not limited to embodiment shown above. Within the scope of the present invention, it is possible to change, add, or convert each element of the above-described embodiment to a content that can be easily considered by those skilled in the art.

1 Memory cell (MEMORY CELL)
2 ROW decoder (ROW DEC)
3 COL decoder (COL DEC)
4 Sense-up section (Sense amplifier / Y switch: SENSE AMP / YSW)
5 Read / write section (data amplifier / write amplifier: DATA AMP / WRITE AMP)
6 Control unit (address, command, timing controller: ADDRESS, COMMAND, TIMING CONTROLLER)
7 Data mask signal input / output section (DATA I / O, DATA MASK)
8 Bus 10, 30, 50 Semiconductor memory 11 Memory cell array 12 Row decoder 13 Column decoder 14 Active area 16, 36 Control unit 17 Data mask signal input / output unit 19 Default mask signal generation unit 20, 40, 60 Host 41 Information circuit 101 301 Data mask controller

Claims (14)

A memory cell array;
A data mask controller for outputting an internal mask signal for controlling data exchange between the memory cell array and the data input / output contact;
The data mask control unit is configured to change a logical value of a standby state of the internal mask signal according to a default mask signal input from the outside or generated internally,
A semiconductor memory, wherein the default mask signal is set so that a change in a logical value of the internal mask signal is reduced when a first command for accessing the memory cell array is inputted from the outside .   2. The semiconductor memory according to claim 1, wherein the data input / output contact is an external terminal of the semiconductor memory. The default mask signal is set based on a comparison result between the number of bits of the mask signal corresponding to the number of data required for one access to the outside and the total number of bits of the internal mask signal. The semiconductor memory according to claim 1 or 2 . The semiconductor memory is a semiconductor memory according to any one of claims 1 to 3, characterized in that to set the data structure according to the product mode. 5. The semiconductor memory according to claim 4 , wherein the logical value of the standby state of the internal mask signal is changed during a period for setting a data configuration of the own device. When accessing the memory cell array, the data mask control unit performs a logical operation of an external mask signal and a column address signal input from the outside according to the default mask signal to generate the internal mask signal the semiconductor memory according to any one of claims 1 to 5, characterized in that. When the data mask controller represents the external mask signal as MASK1, the column address signal as COL, and the internal mask signal as MASK2, the internal mask signal is expressed as follows:
If the default mask signal indicates unmasking, the expression
MASK2 = (MASK1) or not (COL selection)
Is calculated using
If the default mask signal indicates a mask state, the expression
MASK2 = not (MASK1) / COL selection (= not equation (1))
7. The semiconductor memory according to claim 6 , wherein the semiconductor memory is calculated using 6. The semiconductor memory according to claim 4 , further comprising a default mask signal generation unit that generates the default mask signal using the product mode received from outside. The default mask signal generation unit holds in advance information indicating whether or not to change the default state of the mask signal according to the product mode, and the default mask signal is generated based on the held information and the product mode. 9. The semiconductor memory according to claim 8 , wherein a signal is generated. The default mask signal, the semiconductor memory according to any one of claims 1 to 9, wherein the receiving host. The default mask signal is a signal acquired by referring to an information circuit arranged outside the own device,
11. The semiconductor memory according to claim 10 , wherein the information circuit is arranged outside the host, and the host sets a value. The default mask signal, the semiconductor memory according to claim 10, wherein the notified along with the host or al product mode. The default mask signal, the host, using the product mode and external mask signal, when processing a first command for accessing the memory cell array, much variation in the logical value of the internal mask signal the semiconductor memory according to any one of claims 11 to 12, characterized in that a set value so. Before Symbol products mode is comprised of a plurality of product mode,
The memory cell array has a plurality of data configurations set based on the plurality of product modes,
The default mask signal, the semiconductor memory according to any one of claims 4,5,12,13, characterized in that specify multiple default values corresponding to said plurality of product modes.

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