JP5403380B2 - Crossbar switch, vector processing apparatus, and crossbar control method - Google Patents

Description

  The present invention relates to a crossbar switch, and more particularly to improvement in utilization efficiency of a crosspoint buffer.

  In a vector type computer, it is sometimes necessary to arbitrate elements with a crossbar while guaranteeing a passing order through the crossbar. In addition, since performance is also required, there is a technology that uses a crosspoint buffer with a large amount of hardware.

  An example of a vector processing apparatus according to the background art will be described with reference to FIGS. 9, FIG. 11, and FIG. 13 show the configuration of the crossbar, and FIG. 10, FIG. 12, and FIG.

  FIG. 9 shows a configuration of a general crossbar switch. Here, as an example of the crossbar switch, a 16 × 16 crossbar is assumed in which there are 16 input buffers (I00 to I15), 16 output buffers (O00 to O15, the first character is “O” in alphabets).

  FIG. 10 shows an operation example corresponding to FIG. Assume that the elements of S00 to S15 first, the elements of L0 to L1, then the element of M0, and then the element of N0 flow from the input buffer first.

  Each element exits the crossbar in one cycle and is sequentially output to the output buffer. In S00, it is issued from the input buffer at time 0 cycle and output from the output buffer at time 1 cycle.

  Here, an element that passes through the crossbar is assumed to be an architecture in which the order of arrival in the input buffer must be maintained in the output buffer. The same applies to the present invention described later. In other words, in the example of FIG. 10, L0 and L1 must not be output to the output buffer O01 overtaking S00 to S15, and similarly M0 can be output to the output buffer O01 overtaking L0 and L1. An architecture that should not be assumed.

  In this example, since all the elements are concentrated in the output buffer O01, the arbitrating unit of the crossbar must arbitrate each element and sequentially output the elements. That is, the arbitration results S00 to S15 are sequentially issued, but the 16th element S15 is issued after waiting for 15T.

  In this example, since all output destinations are O01, it seems that all orders are guaranteed, but for example, S00 to S07 output O01, S08 to S15 output O09, L0 outputs O01, and L1 outputs O09. When the buffer is used, an architecture is assumed in which the case where L1 having O09 as the destination is issued first when the timing of the entire output buffer is viewed from S07 having O01 as the output destination is not a problem. That is, when viewed in each output buffer, it is only necessary that the order of elements viewed in the output buffer guarantees the arrival order in the input buffer.

  Specifically, this applies to a vector type computer, and the vector load / store instruction that issues a plurality of elements must not be overtaken by the vector load / store instruction that issues a plurality of elements.

  Note that, as a more severe restriction, elements that arrive at the input buffer at the same time are treated as preceding arrival elements on the input buffer I00 side. In this example, it is good to output to the O01 buffer in the order of S00, S01,... S15, but at the same time, although it arrives at the input buffer, it is output in the order of S15, S14. It shall not be allowed.

  Summarizing the priorities, it is assumed that the one that arrives first in the input buffer has priority, and that the input buffer younger (I00 side) has priority in simultaneous arrival.

  In order to observe these restrictions, the subsequent L0 and L1 elements cannot participate in the arbitration until all the preceding S00 to S15 elements have been swept. Therefore, in order to guarantee the order, participation of L0 and L1 to the input buffer (= arbitration participation) is 16 cycles. Similarly, M0 participates in arbitration until L0 and L1 have all swept as a result of the arbitration. Since this is not possible, the start of participation in the input buffer (= arbitration participation) is 18 cycles.

  The examples of FIGS. 9 and 10 show problems when a simple crossbar configuration is used in an architecture in which the arrival order of elements must be observed. That is, in order to guarantee the order, L0 and L1 are waiting for S00 to S15, M0 is waiting for L0 and L1, and as a result, N0 that makes the output buffer O00 other than O01 cannot participate in the arbitration, Waiting. As a result, the utilization efficiency of the crossbar has become low.

  FIGS. 11 and 12 show an example of a crossbar switch including a crosspoint buffer, which is a performance improvement measure for avoiding problems with a simple crossbar configuration. In this system, buffers are provided at points where the input buffer and the output buffer intersect, and are indicated as X00 to X15 in FIG. This X00 to X15 is one set per output buffer.

  FIG. 12 shows an operation example in the crosspoint buffer. Unlike FIG. 10, since the cross-point buffer is held, all the elements S00 to S15 arranged in the input buffer are held in the cross-point buffer after one cycle. The elements from S00 to S15 held in the crosspoint buffer are issued one by one through the 16 to 1 selector to the output buffer.

  The difference from FIG. 10 is that the arbitration start time of subsequent L0 and L1 is advanced. In other words, the start of arbitration of L0 and L1 was cycle 16 without the crosspoint buffer, whereas it was cycle 1 with the crosspoint buffer. In other words, if the destination buffers of L0 and L1 are other than O01, L0 and L1 can be issued immediately to the crosspoint buffer, and this is a method that is effective in performance.

  However, in this example, since the destination buffers of the subsequent L0 and L1 are also the same O01 as S00 to S15, the entire performance is not improved because the crosspoint buffer is waited thereafter.

  As a measure for further improving the performance of the crosspoint buffer, there is a method of increasing the number of words of the crosspoint buffer. FIGS. 13 and 14 show examples of crossbar switches in which the number of words in the crosspoint buffer is two words.

  In FIG. 13, in addition to the cross buffer buffers 1 X00 to X15, cross point buffers 2 Y00 to Y15 are provided below them.

  FIG. 14 shows an example of operation in a crosspoint buffer with the number of words set to two. Unlike FIG. 12, since the crosspoint buffer has two words in the depth direction, the issuance of L0 and L1 that have been waiting in the input buffer earlier is earlier. In FIG. 12, issuance of L0 and L1 is waited until 16 cycles, whereas in FIG. 14, issuance is in one cycle without waiting.

  Thus, having the number of words in the depth direction of the crosspoint buffer has a certain effect on performance.

  Here, as a related technique, Patent Document 1 discloses a technique for increasing the utilization efficiency of a crossbar. The technique disclosed in Patent Document 1 improves the utilization efficiency of the crossbar by improving the selection algorithm of the output element from the input buffer and the crosspoint buffer.

Japanese Patent No. 4002210

  In the example shown in FIG. 13 and FIG. 14, since the destination buffer of the subsequent M0 is also the same O01 as L0 and L1, the overall performance is not improved since the system waits until the crosspoint buffer becomes empty. . If the depth direction is further increased and the crosspoint buffer is set to 3 words, N0 with a different destination buffer is not waited for, so that the performance can be improved. In this case, however, a large amount of hardware is required. In addition, there is a problem that the latency deteriorates as the number of words increases.

  From the examples so far, it can be said that the background art has the following problems.

  As a measure for improving the performance of the cross-point buffer, there is a method of increasing the number of words in the buffer depth direction. However, in an architecture that must guarantee the passage order for elements that pass through the crossbar, performance cannot be obtained in a specific pattern or random access even if the number of words is simply in the depth direction. Case exists. In addition, the solution in the case of simply increasing the number of words also has the problem of increasing the amount of hardware and worsening the latency.

  Further, since the technique disclosed in Patent Document 1 is a means that can be used in a crossbar that does not need to guarantee the order of output elements, there is a problem that it cannot be used in a configuration that needs to guarantee the order of output elements.

(Object of invention)
An object of the present invention is to provide a crossbar switch, a vector processing device, and a crossbar control method for solving the above-described problems and improving the crossbar utilization efficiency in a crosspoint buffer system having two or more words in the depth direction. It is.

  The first crossbar switch of the present invention includes a crosspoint buffer of 2 words or more in the depth direction between the crossbar input buffer and the crossbar output buffer, and implements a shift function in the second word of the crosspoint buffer. When the number of elements in the first word of the buffer is larger than the number of elements in the second word of the crosspoint buffer, selection means for selecting not to use the shift function is included.

  A first vector processing apparatus of the present invention includes a crossbar switch including a crosspoint buffer of two words or more in the depth direction between a crossbar input buffer and a crossbar output buffer, and a second word of the crosspoint buffer of the crossbar switch. A shift function is implemented, and the crossbar switch includes selection means for selecting not to use the shift function when the number of elements in the first word of the crosspoint buffer is larger than the number of elements in the second word of the crosspoint buffer.

  A first crossbar control method according to the present invention is a crossbar control method using a crossbar switch including a crosspoint buffer of two words or more in the depth direction between a crossbar input buffer and a crossbar output buffer, and includes two words of the crosspoint buffer. When the shift function is implemented in the eyes and the number of elements in the first word of the crosspoint buffer is larger than the number of elements in the second word of the crosspoint buffer, the selection means executes a selection step for selecting not to use the shift function. To do.

  A second crossbar control method according to the present invention is a crossbar control method by a vector processing device including a crossbar switch including a crosspoint buffer of two words or more in the depth direction between a crossbar input buffer and a crossbar output buffer. If the number of elements in the first word of the point buffer is greater than the number of elements in the second word of the crosspoint buffer, a selection step for selecting not to use the shift function implemented in the second word of the crosspoint buffer of the crossbar switch The crossbar switch selection means executes.

  According to the present invention, it is possible to improve the utilization efficiency of the crossbar in the cross point buffer system having two words or more in the depth direction.

It is a figure which shows the shift function by the 1st Embodiment of this invention. It is a figure which shows the effect when the shift function by the 1st Embodiment of this invention is mounted. It is a figure which shows the structure of the crossbar switch by the 1st Embodiment of this invention. It is a figure which shows the effect when not using the shift function by the 1st Embodiment of this invention. It is a flowchart which shows operation | movement of the crossbar switch by the 1st Embodiment of this invention. It is a flowchart which shows operation | movement of the crossbar switch by the 1st Embodiment of this invention. It is a flowchart which shows operation | movement of the crossbar switch by the 1st Embodiment of this invention. It is a flowchart which shows operation | movement of the crossbar switch by the 1st Embodiment of this invention. It is a figure which shows the example of the vector processing apparatus by background art. It is a figure which shows the example of the vector processing apparatus by background art. It is a figure which shows the example of the vector processing apparatus by background art. It is a figure which shows the example of the vector processing apparatus by background art. It is a figure which shows the example of the vector processing apparatus by background art. It is a figure which shows the example of the vector processing apparatus by background art. It is a figure which shows the structure of the crossbar switch by background art.

  In order to clarify the above and other objects, features and advantages of the present invention, embodiments of the present invention will be described in detail below with reference to the accompanying drawings. In addition to the above-described object of the present invention, other technical problems, means for solving the technical problems, and operational effects thereof will become apparent from the disclosure of the following embodiments.

  In all the drawings, the same reference numerals are given to the same components, and the description will be omitted as appropriate.

(First embodiment)
A first embodiment of the present invention will be described in detail with reference to the drawings.

  The crossbar switch 100 according to the present embodiment includes a crosspoint buffer having two words in the depth direction (see FIG. 1).

  FIG. 15 shows a portion corresponding to one output buffer of the two-word crosspoint buffer shown in FIG. X00 to X15 (3-1) in the first word of the crosspoint buffer correspond to Y00 to Y15 (3-3) in the second word of the crosspoint buffer.

  As described above, since it is assumed that the order of elements must be guaranteed, in the configuration shown in FIG. 15, all elements are issued from Y00 to Y15 (3-3) in the second word of the crosspoint buffer. Otherwise, it is not possible to move from X00 to X15 (3-1) of the first word of the crosspoint buffer to Y00 to Y15 (3-3) of the second word of the crosspoint buffer. FIG. 14 shows this example.

  In order to perform such an operation, there is a case where the cross-point buffer per output buffer has a 32-element buffer of 16 × 2 words, but the performance is not good.

  For example, even if only 2 elements in Y14 and Y15 and 1 element in X00 are filled, the first word element has to wait because the second word in the buffer is not empty. Further, even if a subsequent element is directed to the same output buffer, it cannot enter X00 to X15, resulting in performance degradation. This is because the cross buffer cannot be effectively used.

  In order to solve this problem, the present invention implements a shift function at the second word of the crosspoint buffer as shown in FIG.

  The shift function of the second word operates as follows.

  First, the element to be issued is selected from the second word. The selection priority order is Y00> Y01...> Y15.

  Second, when an element is issued from the second word, the left entry is shifted to the left (because the Y00 side has a high priority).

  Third, if the number of words in the first word is smaller than the number of words in the second word, the highest priority entry for the first word is placed in Y15 for the second word.

  Fourth, if the number of words in the first word> = the number of words in the second word, after all the entries in the second word are issued, they are put into X00-> Y00, X01-> Y01,... X15-> Y15, respectively ( Depending on the number of entries in the first word and the second word, an appropriate selection is made based on performance.)

  Fifth, the subsequent input is accepted when all entries in the first word are empty.

  FIG. 2 shows the effect when the shift function is implemented.

  The first elements S00 to S15 pass through the crosspoint buffer 1 (X00 to X15) and reach the crosspoint buffer 2 (Y00 to Y15). Here, in the present invention, since there is a shift function, every time a preceding element is issued, it is shifted to the Y00 side. Subsequent L0 and L1 are also inserted into the crosspoint buffer 1 (X00 to X01) after S00 to S15.

  In FIG. 14 before the improvement, L0 and L1 can only be held in the crosspoint buffer 1 (X00 to X01) until the elements of the crosspoint buffer 2 (Y00 to Y15) are swept. Since Y15 of the crosspoint buffer 2 (Y00 to Y15) is free, the L0 element can be inserted into Y15. Similarly, L1 can be inserted into Y15 after one cycle, so that the following M0 passes only after waiting for one cycle in the input buffer.

  The N0 element further behind M0 is easy to understand as the effect difference. In FIG. 14, which does not have the shift function, the N0 element is not issued until the preceding M0 enters the crosspoint buffer 1, and as a result, 21 cycles pass when viewed in the output buffer. Yes. On the other hand, in FIG. 2 where the preceding element M0 is quickly inserted into the crosspoint buffer 1, N0 passes through the output buffer in 7 cycles.

  As described above, the performance effect of adding the shift function to the crosspoint buffer 2 is great.

  However, there are cases where performance is better when this shift function is not used. Generally speaking, the shift function works effectively when the number of elements in the crosspoint buffer 2 (Y00 to Y15) is compared with the number of elements in the crosspoint buffer 1 (X00 to X15), and the crosspoint buffer 2 The shift function works effectively when there are more elements. On the other hand, when the number of elements of the crosspoint buffer 1 is larger, the method that does not use the shift function has better performance.

  FIG. 3 shows a case where the shift function is used to reduce the performance when the number of elements of the crosspoint buffer 1 is larger. In the example of FIG. 3, the movement from the crosspoint buffer 1 to the crosspoint buffer 2 requires 16 cycles, and the performance is deteriorated.

  FIG. 4 shows a case where the shift function is not used for the same instruction sequence. The movement from the crosspoint buffer 1 to the crosspoint buffer 2 is completed in two cycles, that is, one cycle of waiting and one cycle of movement.

  From the above, this shift function works effectively when (number of elements of crosspoint buffer 1) <(number of elements of crosspoint buffer 2). Therefore, in the present invention, a selection circuit for determining (number of elements of the crosspoint buffer 1) <(number of elements of the crosspoint buffer 2) is also added. The third and fourth operations described above are part of this selection circuit, which will be described in detail in the following embodiments.

(Description of the operation of the first embodiment)
Next, the operation of the crossbar switch 100 according to the present embodiment will be described in detail with reference to the drawings.

  Next, the operation of this embodiment will be described using specific examples.

(Description of configuration)
FIG. 1 shows a crosspoint buffer for one output buffer and a shift function. Since this circuit exists per output buffer, in the case of a logical 16 × 16 crossbar, there are 16 such circuits.

X00 to X15 of reference numeral 41 is the first word of the cross point buffer. In order to guarantee the element order, the new insertion starts from the timing when X00 to X15 are all free.

  Reference numeral 42 denotes a 3-way selector. One is a hold of Y00 to Y15 itself, which will be described later, and one is a path corresponding to each of X00... X15 and Y00... Y15, and these two are ways also existing in the conventional crosspoint buffer. The last third way is a path that realizes the shift function. Y00 is connected to Y01, and Y01 is connected to the path from Y02. However, for Y15, the result of selecting the highest priority among X00 to X15 is connected as a shift path.

  Y00 to Y15 of reference numeral 43 is the second word of the crosspoint buffer. In order to guarantee the element order, a shift is executed in the crosspoint buffer 2 every time an element is issued from the crosspoint buffer 2.

  Reference numeral 44 denotes a 16-way selector. Since it is necessary to issue from the first element, the existence of elements from Y00 to Y15 is checked, the highest priority element is selected (Leading0 circuit), and then the first element in the crosspoint buffer 2 is issued To do.

  Reference numeral 45 is a 2-way selector. From the output buffer OUT (output register 46), there are cases where it can be issued and cases where it cannot be issued due to the congestion of the previous circuit. This 2-way selector realizes a hold when it cannot be issued.

  Reference numeral 47 denotes a 16-way selector used when elements are inserted from the crosspoint buffer 1 to the crosspoint buffer 2 when the shift function is used. After selecting the highest-priority element (Leading 0 circuit), it has a function that can issue the first element of the crosspoint buffer 1, and the issue is not always performed. It also has a function of determining whether or not to issue based on the relationship of the number of elements of 2.

  The above is the component of the present invention.

(Description of operation)
The operation of the constituent elements shown in FIG. 1 will be described with reference to the flowcharts of FIGS.

  FIG. 5 shows the operation of the 2-way selector 45 with the output register 46 as the center.

  FIG. 6 shows operations of the 3-way selector 42, the 16-way selector 44, and the 16-way selector 47 with the cross point buffer 2 (cross point buffer 44) as the center.

  FIG. 7 shows the operation of the 3-way selector 42 and the 16-way selector 47 centering on the crosspoint buffer 1 (crosspoint buffer 41).

  FIG. 8 shows the operation of the input buffer (I00 to I15 in FIGS. 9, 11, and 13).

  FIG. 5 is a flowchart mainly showing the output buffer 46. First, there is a power source On, reset (step SO-1), and there is no element (step SO-2).

  It is determined whether or not there is an element in the cross-point buffer 2 corresponding to the higher-order register (step SO-3). If there is no element, there is no element and if there is an element (step SO-4).

  From the output buffer OUT, it is determined whether or not it can be issued to a further stage (step SO-5). If it is not possible, nothing is done, but if possible, the element is issued (step SO-6). Thereafter, the process is repeated until the system stops (step SO-7).

  FIG. 6 is a flowchart mainly showing the crosspoint buffer 2. First, there is a power source On, a reset (step SY-1), and a transition is made to a state where there are no elements (step SY-2).

  It is determined whether or not there is an element in the crosspoint buffer 1 corresponding to the upper register (step SY-3). If there is no element, the element remains in the absence of the element (step SY-4).

  It is determined whether or not the output buffer is empty at the next timing (step SY-5). If it is not empty, the process proceeds to the next step.

  If elements can be issued from the second word, it is determined whether or not the number of elements in the second word is two or more (step SY-6). If there is only one element, the element is issued (step SY-7), the process returns to step SY-3, and is repeated until the system stops (step SY-8).

  If there are two or more elements, the number of elements in the crosspoint buffer 1 and the crosspoint buffer 2 is compared (step SY-9). In the case of crosspoint buffer 1> = crosspoint buffer 2, one element is issued from crosspoint buffer 2, and only the other elements are shifted to proceed to step SY-4 (step SY-10). When crosspoint buffer 1 <crosspoint buffer 2, one element is issued from crosspoint buffer 2, the other elements are shifted, and the highest priority element of crosspoint buffer 1 is the oldest of crosspoint buffer 2. Insert into the number Y15 (step SY-11).

  FIG. 7 is a flowchart mainly showing the crosspoint buffer 1. First, there is a power source On, reset (step SX-1), and there is no element (step SX-2).

  It is determined whether or not there is an element in the input buffer corresponding to the upper register (step SX-3). If there is no element, if there is no element, the element is present if there is no element (step SX-4).

  At the next timing, it is determined whether or not the cross point buffer 2 is all empty (step SX-5). If it is empty, all elements of the first word are inserted into the second word (step SX-6). On the contrary, if it is not empty, the process proceeds to step SX-8, and it is confirmed whether or not an element is issued from the crosspoint buffer 2 (step SX-8).

  If no element is issued, the process returns to step SX-4. If issued, the number of elements in the crosspoint buffer 1 and the number of elements in the crosspoint buffer 2 are compared.

  If (the number of buffers 1)> = (the number of buffers 2), nothing is done and the process returns to step SX-4. If (the number of buffers 1) <(the number of buffers 2), the highest priority element of the crosspoint buffer 1 is inserted into Y15 which is not the highest priority of the crosspoint buffer 2 (step SX-10).

  As a result of inserting the highest priority element in Y15 in step SX-10, it is checked whether or not all entries in the crosspoint buffer 1 are empty (step SX-11). If empty, proceed to state step SX-3 from no element, and if there are still elements, proceed to state step SX-4 with elements.

  FIG. 8 is a flowchart mainly showing the input buffer (I00 to I15 in FIGS. 9, 11, and 13).

  First, there is a power supply On, a reset (step SI-1), and a transition is made to a state where there are no elements (step SI-2).

  It is determined whether or not there is an element to be registered in the input buffer in a circuit (buffer or register) higher than the input buffer (step SI-3). (Step SI-4).

  Next, it is confirmed whether or not all the cross-point buffers 1 to which the input buffer elements should go are empty at the next timing (step SI-5). If it is not empty, do nothing and return to SI-4. If it is empty, issue an element from the input buffer. After issuing, return to the step of whether there is a new element.

  The above is the operation timing seen in each buffer.

(Effects of the first embodiment)
According to the present embodiment, it is possible to improve the utilization efficiency of the crossbar by mounting the shift function in the crosspoint buffer.

  In this embodiment, for random performance (the output buffer to be arbitrated is random), the effective performance without the shift function is 57.1%, while the effective performance with the shift function is 65.1%, which improves the performance. To do. Further, when a vector type computer is considered, a performance improvement of 18 to 45% can be seen even in a specific instruction pattern.

  The present invention has been described above with reference to preferred embodiments. However, the present invention is not necessarily limited to the above embodiments, and various modifications can be made within the scope of the technical idea. it can.

  It should be noted that any combination of the above-described constituent elements and a conversion of the expression of the present invention between a method, an apparatus, a system, a recording medium, a computer program, etc. are also effective as an aspect of the present invention.

  The various components of the present invention do not necessarily have to be independent of each other. A plurality of components are formed as a single member, and a single component is formed of a plurality of members. It may be that a certain component is a part of another component, a part of a certain component overlaps with a part of another component, or the like.

  Moreover, although the several procedure is described in order in the method and computer program of this invention, the order of the description does not limit the order which performs a several procedure. For this reason, when implementing the method and computer program of this invention, the order of the several procedure can be changed in the range which does not interfere in content.

  The plurality of procedures of the method and the computer program of the present invention are not limited to being executed at different timings. For this reason, another procedure may occur during the execution of a certain procedure, or some or all of the execution timing of a certain procedure and the execution timing of another procedure may overlap.

  According to the present invention, a computer having a multi-input to multi-output communication network such as a crossbar and requiring an arrival order guarantee between packets (command sequence or data sequence) passing through the communication network. Possible use in system or network switch.

100: Crossbar switch 41: Crosspoint buffer 42: Selector 43: Crosspoint buffer 44: Selector 45: Selector 46: Output register 47: Selector

Claims (4)

A crosspoint buffer of 2 words or more in the depth direction is provided between the crossbar input buffer and the crossbar output buffer,
A shift function is implemented in each crosspoint buffer after the second word of the crosspoint buffer .
The number of elements the elements of the crossbar input buffer is stored in the first word of the entry of the crosspoint buffer to be entered, stored in the second word of the entry cross-point buffer the first word of the element is inputted If and are greater than the number of elements, look at including a selection means you choose not to use the shift function,
The shift function is
From the second word of the crosspoint buffer, select an element to be issued based on a predetermined priority,
When the element is issued, each element of the second word is shifted to the higher priority side with respect to the entry that is empty by the issue, and the highest priority entry of the first word is emptied by the shift. Into the second word entry,
The priority order is determined in the order of arrival in the crossbar input buffer, and the elements of simultaneous arrival are determined in the order of the youngest number in the input buffer . A crossbar switch including a crosspoint buffer of 2 words or more in the depth direction is provided between the crossbar input buffer and the crossbar output buffer.
A shift function is implemented in each crosspoint buffer after the second word of the crosspoint buffer of the crossbar switch,
The crossbar switch is
The number of elements stored in the first word entry of the crosspoint buffer to which the crossbar input buffer element is input is stored in the second word entry of the crosspoint buffer to which the first word element is input. Including a selection means for selecting not to use the shift function when there are more elements than
The shift function is
From the second word of the crosspoint buffer, select an element to be issued based on a predetermined priority,
When the element is issued, each element of the second word is shifted to the higher priority side with respect to the entry that is empty by the issue, and the highest priority entry of the first word is emptied by the shift. Into the second word entry,
The priority order is determined in the order of arrival at the crossbar input buffer, and elements of simultaneous arrival are determined in ascending order of the input buffer.
A vector processing device characterized by that . A crossbar control method using a crossbar switch having a crosspoint buffer of two words or more in the depth direction between a crossbar input buffer and a crossbar output buffer,
A shift function is implemented in each crosspoint buffer after the second word of the crosspoint buffer.
The number of elements stored in the first word entry of the crosspoint buffer to which the crossbar input buffer element is input is stored in the second word entry of the crosspoint buffer to which the first word element is input. When the number of elements is larger than the number of elements, the selection means executes a selection step for selecting not to use the shift function,
The shift function is
From the second word of the crosspoint buffer, select an element to be issued based on a predetermined priority,
When the element is issued, each element of the second word is shifted to the higher priority side with respect to the entry that is empty by the issue, and the highest priority entry of the first word is emptied by the shift. Into the second word entry,
The priority order is determined in the order of arrival at the crossbar input buffer, and elements of simultaneous arrival are determined in ascending order of the input buffer.
A crossbar control method characterized by the above . A vector processing device having a crossbar switch including a crosspoint buffer of 2 words or more in the depth direction between a crossbar input buffer and a crossbar output buffer, and implementing a shift function in each of the crosspoint buffers after the second word of the crosspoint buffer A crossbar control method according to
The number of elements stored in the first word entry of the crosspoint buffer to which the crossbar input buffer element is input is stored in the second word entry of the crosspoint buffer to which the first word element is input. When the number of elements is larger than the number of elements, the selection unit of the crossbar switch executes a selection step of selecting not to use the shift function,
The shift function is
From the second word of the crosspoint buffer, select an element to be issued based on a predetermined priority,
When the element is issued, each element of the second word is shifted to the higher priority side with respect to the entry that is empty by the issue, and the highest priority entry of the first word is emptied by the shift. Into the second word entry,
The priority order is determined in the order of arrival at the crossbar input buffer, and elements of simultaneous arrival are determined in ascending order of the input buffer.
A crossbar control method characterized by the above .

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