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JP5404124B2 - Semiconductor device - Google Patents
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JP5404124B2 - Semiconductor device - Google Patents

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JP5404124B2
JP5404124B2 JP2009077355A JP2009077355A JP5404124B2 JP 5404124 B2 JP5404124 B2 JP 5404124B2 JP 2009077355 A JP2009077355 A JP 2009077355A JP 2009077355 A JP2009077355 A JP 2009077355A JP 5404124 B2 JP5404124 B2 JP 5404124B2
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electrode
semiconductor device
semiconductor element
metal plate
semiconductor
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JP2010232365A (en
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弘幸 山岸
康宏 岡田
穣二 中島
大裕 竹内
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Honda Motor Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink

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Description

本発明は、例えば、電気自動車や電動機を用いるハイブリッド車等の電動機の電力変換装置として用いられる半導体装置に関するものである。   The present invention relates to a semiconductor device used as a power conversion device for an electric motor such as an electric vehicle or a hybrid vehicle using an electric motor.

電気自動車やハイブリッド車等の電動機の電力変換装置として、従来、半導体パワー素子等の半導体素子を主電極となる一対の金属板で挟持し、該半導体素子が該主電極に圧接されるようにした圧接型半導体装置が知られている。   Conventionally, as a power conversion device for an electric motor such as an electric vehicle or a hybrid vehicle, a semiconductor element such as a semiconductor power element is sandwiched between a pair of metal plates serving as main electrodes, and the semiconductor element is pressed against the main electrode. A pressure contact type semiconductor device is known.

前記圧接型半導体装置において、前記半導体素子は例えばｐｎ接合を有するＳｉからなり、前記金属板は例えばＣｕにより構成される。このとき、前記半導体素子を前記金属板で直接挟持すると、該半導体素子の発熱により該金属板が熱膨張したときに、ＳｉとＣｕとの熱膨張係数の相違から、該半導体素子が破壊されるおそれがある。そこで、前記半導体素子と前記金属板との間に、Ｍｏからなる熱緩衝板を介在させるようにした圧接型半導体装置が知られている（例えば特許文献１参照）。   In the press contact type semiconductor device, the semiconductor element is made of Si having a pn junction, for example, and the metal plate is made of Cu, for example. At this time, if the semiconductor element is directly sandwiched by the metal plate, the semiconductor element is destroyed due to the difference in thermal expansion coefficient between Si and Cu when the metal plate thermally expands due to heat generation of the semiconductor element. There is a fear. Therefore, a pressure contact type semiconductor device is known in which a thermal buffer plate made of Mo is interposed between the semiconductor element and the metal plate (see, for example, Patent Document 1).

前記圧接型半導体装置において、前記半導体素子はそのアノード（またはエミッタ）電極側の端面がカソード（またはコレクタ）電極と同電位になる。また、前記半導体素子は、アノード（またはエミッタ）電極側の端面と、該アノード（またはエミッタ）電極に接続される主電極との間の間隙が小さくなる。この結果、前記半導体装置に大電圧が印加された場合には、該半導体素子と、前記カソード（またはコレクタ）電極に接続される主電極との間で放電や絶縁破壊が生じることがある。   In the press contact type semiconductor device, the end face of the semiconductor element on the anode (or emitter) electrode side has the same potential as the cathode (or collector) electrode. In the semiconductor element, a gap between the end face on the anode (or emitter) electrode side and the main electrode connected to the anode (or emitter) electrode is reduced. As a result, when a large voltage is applied to the semiconductor device, discharge or dielectric breakdown may occur between the semiconductor element and the main electrode connected to the cathode (or collector) electrode.

前記放電や絶縁破壊は、前記熱緩衝板の厚さを大きくすることにより防止することができる。しかし、前記半導体素子は、前記半導体装置に大電圧が印加されることに伴って発熱量も大になるので、前記熱緩衝板の厚さを大きくすると、放熱性が低下するという問題がある。   The discharge and dielectric breakdown can be prevented by increasing the thickness of the thermal buffer plate. However, since the semiconductor element generates a large amount of heat as a large voltage is applied to the semiconductor device, there is a problem that heat dissipation is reduced when the thickness of the thermal buffer plate is increased.

一方、前記ＳｉとＣｕ等の金属板との熱膨張係数の相違を低減するために、セラミックス基板等の絶縁基板の表裏両面にＣｕ等の金属板を備える材料が知られている。このような材料によれば、前記セラミックス基板及び前記金属板の材質、厚さ等を適宜選択することにより、該金属板の熱膨張係数を調整することができ、前記Ｓｉからなる半導体素子と同等の熱膨張係数とすることができる。   On the other hand, in order to reduce the difference in thermal expansion coefficient between the Si and the metal plate such as Cu, a material provided with a metal plate such as Cu on both front and back surfaces of an insulating substrate such as a ceramic substrate is known. According to such a material, the coefficient of thermal expansion of the metal plate can be adjusted by appropriately selecting the material and thickness of the ceramic substrate and the metal plate, which is equivalent to the semiconductor element made of Si. The thermal expansion coefficient of

そこで、前記圧接型半導体装置において、表裏両面に金属板を備える一対の絶縁基板の一方の金属板を主電極として、該主電極の間に前記半導体素子を挟持させることが考えられる。このようにするときには、前記半導体素子と前記主電極との間に、Ｍｏからなる熱緩衝板を介在させる必要がないので、優れた放熱性を得ることができると期待される。   Therefore, in the press contact type semiconductor device, it is conceivable to use one metal plate of a pair of insulating substrates provided with metal plates on both front and back surfaces as a main electrode, and sandwich the semiconductor element between the main electrodes. In doing so, it is not necessary to interpose a heat buffer plate made of Mo between the semiconductor element and the main electrode, and it is expected that excellent heat dissipation can be obtained.

しかしながら、前記構成の半導体装置では前記熱緩衝板を用いないため、前記半導体素子のアノード（またはエミッタ）電極側の端面と該アノード（またはエミッタ）電極に接続される主電極との間隙が小さくなり、該半導体素子と該主電極との間に放電や絶縁破壊が起きやすくなるという不都合がある。   However, since the semiconductor device having the above configuration does not use the thermal buffer plate, the gap between the end surface of the semiconductor element on the anode (or emitter) electrode side and the main electrode connected to the anode (or emitter) electrode is reduced. There is an inconvenience that electric discharge and dielectric breakdown are likely to occur between the semiconductor element and the main electrode.

特開平９−２１３８８０号公報Japanese Patent Laid-Open No. 9-213880

本発明は、かかる不都合を解消して、優れた放熱性を備えると共に、半導体素子のアノード（またはエミッタ）電極側の端面と該アノード（またはエミッタ）電極に接続される主電極との間の絶縁を確保し、優れた電気的信頼性を備える半導体装置を提供することを目的とする。   The present invention eliminates such inconvenience, has excellent heat dissipation, and insulation between the end surface of the semiconductor element on the anode (or emitter) electrode side and the main electrode connected to the anode (or emitter) electrode. An object of the present invention is to provide a semiconductor device having high electrical reliability.

かかる目的を達成するために、本発明の半導体装置は、表裏両面に金属板を備え一方の金属板を主電極とすると共に、該主電極に接続されたリード電極を備える一対の絶縁基板と、各絶縁基板の該主電極とされる金属板の間に挟持されて、該主電極に圧接されている半導体素子と、各絶縁基板の該主電極とされる金属板と反対側の金属板表面と、各リード電極の一部とを露出して、各絶縁基板と該半導体素子と各リード電極とを封止する樹脂層とを備える半導体装置であって、一方の該絶縁基板の該主電極は、該半導体素子のアノードまたはエミッタ電極に対する接続部として周囲の部分から隆起している隆起部と、該周囲の部分として該隆起部の周囲に形成され、その底面と該半導体素子の周囲の部分側の表面との間に絶縁に十分な空間距離を確保する溝部とを備え、該隆起部の表面が該リード電極の半導体素子側の表面と面一となるように形成されていることを特徴とする。 In order to achieve such an object, a semiconductor device of the present invention comprises a pair of insulating substrates each having a metal plate on both front and back surfaces and having one metal plate as a main electrode and a lead electrode connected to the main electrode, A semiconductor element sandwiched between the metal plates that are the main electrodes of each insulating substrate and pressed against the main electrode; and a metal plate surface opposite to the metal plate that is the main electrode of each insulating substrate; A part of each lead electrode is exposed, and is a semiconductor device including a resin layer that seals each insulating substrate, the semiconductor element, and each lead electrode, and the main electrode of one of the insulating substrates is: A raised portion protruding from a peripheral portion as a connection portion to the anode or emitter electrode of the semiconductor element , and a peripheral portion formed around the raised portion , the bottom surface of the semiconductor element and the peripheral portion side of the semiconductor element Sufficient clearance between the surface and insulation And a groove to secure the surface of the raised portion is characterized in that it is formed so as to be flush with the surface of the semiconductor device side of the lead electrode.

本発明の半導体装置は、表裏両面に金属板を備える一対の絶縁基板の一方の金属板を主電極として、該主電極とされる金属板の間に挟持されて、該主電極に圧接されている半導体素子を備える。このような構成によれば、前記主電極とされる各金属板と前記半導体素子との間に熱緩衝板が介在しないので、前記半導体装置に大電圧が印加されたときにも優れた放熱性を得ることができる。   The semiconductor device of the present invention is a semiconductor in which one metal plate of a pair of insulating substrates provided with metal plates on both front and back surfaces is used as a main electrode and is sandwiched between the metal plates used as the main electrode and is in pressure contact with the main electrode The device is provided. According to such a configuration, since no thermal buffer plate is interposed between each metal plate serving as the main electrode and the semiconductor element, excellent heat dissipation even when a large voltage is applied to the semiconductor device. Can be obtained.

また、本発明の半導体装置は、前記各絶縁基板と前記半導体素子と前記各リード電極とを封止する樹脂層とを備えると共に、一方の該絶縁基板の前記主電極は、該半導体素子のアノードまたはエミッタ電極に対する接続部として周囲の部分から隆起している隆起部と、該周囲の部分として該隆起部の周囲に形成され、その底面と該半導体素子の周囲の部分側の表面との間に絶縁に十分な空間距離を確保する溝部とを備える。そこで、本発明の半導体装置は、前記隆起部及び前記溝部により該半導体素子のアノードまたはエミッタ電極側の表面と該アノードまたはエミッタ電極に前記主電極として接続される前記金属板との間に絶縁に十分な空間距離を確保することができる。 The semiconductor device of the present invention further includes a resin layer that seals each of the insulating substrates, the semiconductor element, and the lead electrodes, and the main electrode of one of the insulating substrates is an anode of the semiconductor element. Or a raised portion protruding from a peripheral portion as a connection portion to the emitter electrode , and a periphery of the raised portion as the peripheral portion, between the bottom surface and the surface of the peripheral portion side of the semiconductor element And a groove portion that secures a sufficient spatial distance for insulation . Accordingly, the semiconductor device of the present invention, the insulation between the metal plate is connected as the main electrode by the ridges and the groove on the front surface and the anode or the emitter electrode of the anode or emitter electrode of the semiconductor element A sufficient spatial distance can be secured.

しかも、本発明の半導体装置は前記樹脂層により封止されているので、前記溝部の底面と該半導体素子の周囲の部分側の表面との間には、前記前記樹脂層が空隙なく充填されている。従って、本発明の半導体装置は、該半導体素子のアノードまたはエミッタ電極側の表面と該アノードまたはエミッタ電極に前記主電極として接続される前記金属板との間に絶縁に十分な空間距離を確保し、優れた電気的信頼性を得ることができる。 In addition, since the semiconductor device of the present invention is sealed by the resin layer, the resin layer is filled without a gap between the bottom surface of the groove and the surface of the portion around the semiconductor element. Yes. Accordingly, the semiconductor device of the present invention, adequate clearance distance insulation between the metal plate is connected as the main electrode on the front surface and the anode or the emitter electrode of the anode or emitter electrode of the semiconductor element Thus, excellent electrical reliability can be obtained.

また、本発明の半導体装置において、前記隆起部の表面が該リード電極の半導体素子側の表面と面一となるように形成されている。これにより、該半導体素子の側面と該リード電極の側面とが対向して配置されていないので、両側面の間に絶縁を確保するための空間距離を確保する必要はない。 In the semiconductor device of the present invention, the surface of the raised portion is formed to be flush with the surface of the lead electrode on the semiconductor element side. Thereby, since the side surface of the semiconductor element and the side surface of the lead electrode are not arranged to face each other, it is not necessary to secure a space distance for ensuring insulation between both side surfaces .

前記樹脂層を形成する樹脂として、例えば、ポリフェニレンサルファイド系樹脂、ポリイミド系樹脂、ポリアミド系樹脂からなる群から選択される１種の樹脂を挙げることができる。   Examples of the resin that forms the resin layer include one type of resin selected from the group consisting of polyphenylene sulfide-based resins, polyimide-based resins, and polyamide-based resins.

本発明の半導体装置の一構成例を示す説明的断面図。FIG. 6 is an explanatory cross-sectional view illustrating a structural example of a semiconductor device of the present invention. 図１に示す半導体装置において、半導体素子のアノード（またはエミッタ）電極に接続される主電極の構成を示す斜視図。FIG. 2 is a perspective view showing a configuration of a main electrode connected to an anode (or emitter) electrode of a semiconductor element in the semiconductor device shown in FIG. 1. 本発明の半導体装置の他の構成例を示す説明的断面図。FIG. 10 is an explanatory cross-sectional view illustrating another example of the structure of the semiconductor device of the present invention. 図３に示す半導体装置において、半導体素子のアノード（またはエミッタ）電極に接続される主電極の構成を示す斜視図。FIG. 4 is a perspective view showing a configuration of a main electrode connected to an anode (or emitter) electrode of a semiconductor element in the semiconductor device shown in FIG. 3.

次に、添付の図面を参照しながら本発明の実施の形態についてさらに詳しく説明する。   Next, embodiments of the present invention will be described in more detail with reference to the accompanying drawings.

まず、本実施形態の第１の態様について説明する。図１に示すように、本実施形態の半導体装置１ａは、半導体素子としての半導体パワー素子２が、一対の絶縁基板３，４により挟持されている。絶縁基板３は、セラミックス基板５の表裏両面に金属板６，７を備え、金属板６が主電極として半導体パワー素子２のアノード（またはエミッタ）電極２ａ（以下、アノード電極２ａと略記する）に接続されると共に、金属板６に接続されたリード電極８を備えている。   First, the first aspect of the present embodiment will be described. As shown in FIG. 1, in the semiconductor device 1 a of this embodiment, a semiconductor power element 2 as a semiconductor element is sandwiched between a pair of insulating substrates 3 and 4. The insulating substrate 3 includes metal plates 6 and 7 on both front and back surfaces of the ceramic substrate 5, and the metal plate 6 serves as an anode (or emitter) electrode 2a (hereinafter abbreviated as the anode electrode 2a) of the semiconductor power element 2 as a main electrode. A lead electrode 8 connected to the metal plate 6 is provided.

一方、絶縁基板４は、セラミックス基板９の表裏両面に金属板１０，１１を備え、金属板１０が主電極として半導体パワー素子２のカソード（またはコレクタ）電極２ｂに接続されると共に、金属板１０に接続されたリード電極１２を備えている。   On the other hand, the insulating substrate 4 includes metal plates 10 and 11 on both front and back surfaces of the ceramic substrate 9, and the metal plate 10 is connected to the cathode (or collector) electrode 2 b of the semiconductor power element 2 as a main electrode. The lead electrode 12 is provided.

そして、半導体装置１ａは、主電極となる金属板６，１０に半導体パワー素子２が圧接された状態で、樹脂層１３により封止されている。ただし、絶縁基板３，４の金属板６，１０と反対側に備えられた金属板７，１１の表面と、各リード電極８，１２の端部とは、樹脂層１３から露出されている。   The semiconductor device 1a is sealed with a resin layer 13 in a state where the semiconductor power element 2 is pressed against the metal plates 6 and 10 serving as main electrodes. However, the surfaces of the metal plates 7 and 11 provided on the opposite sides of the insulating substrates 3 and 4 from the metal plates 6 and 10 and the end portions of the lead electrodes 8 and 12 are exposed from the resin layer 13.

半導体装置１ａにおいて、セラミックス基板５，９は、Ｓｉ３Ｎ４、ＡｌＮ、Ａｌ２Ｏ３からなる群から選択される１種のセラミックスからなるものを用いることができる。また、金属板５，６，１０，１１は、ＣｕまたはＡｌのいずれか１種の金属からなるものを用いることができる。前記絶縁基板３，４において、金属板５，６，１０，１１がＣｕからなるものはＤＣＢ(Direct Copper Brazed)基板として公知である。 In the semiconductor device 1a, the ceramic substrates 5 and 9 can be made of one kind of ceramic selected from the group consisting of Si 3 N 4 , AlN, and Al 2 O 3 . The metal plates 5, 6, 10, and 11 may be made of any one of Cu and Al. Of the insulating substrates 3 and 4, the metal plates 5, 6, 10, and 11 made of Cu are known as DCB (Direct Copper Brazed) substrates.

また、樹脂層１３は、例えば、金属板６，１０を介して絶縁基板３，４に挟持された状態の半導体パワー素子２をインサート成形金型（図示せず）のキャビティ内の所定の位置に装着し、該キャビティに溶融樹脂を射出することにより形成することができる。樹脂層１３を形成する樹脂としては、例えば、ポリフェニレンサルファイド系樹脂、ポリイミド系樹脂、ポリアミド系樹脂からなる群から選択される１種の樹脂を挙げることができる。   In addition, the resin layer 13 is placed at a predetermined position in the cavity of the insert molding die (not shown), for example, with the semiconductor power element 2 held between the insulating substrates 3 and 4 via the metal plates 6 and 10. It can be formed by mounting and injecting molten resin into the cavity. Examples of the resin that forms the resin layer 13 include one type of resin selected from the group consisting of polyphenylene sulfide-based resins, polyimide-based resins, and polyamide-based resins.

半導体装置１ａでは、金属板６は、図１，２に示すように隆起部６ａを備えており、隆起部６ａにより半導体パワー素子２のアノード電極２ａに接続されている。隆起部６ａは、周囲の部分６ｂに対して隆起して形成されている。部分６ｂはリード電極８と面一に形成されている。隆起部６ａを備える金属板６は、エッチング、プレス加工、レーザー加工等のそれ自体公知の方法により形成することができる。   In the semiconductor device 1a, the metal plate 6 includes a raised portion 6a as shown in FIGS. 1 and 2, and is connected to the anode electrode 2a of the semiconductor power element 2 by the raised portion 6a. The raised portion 6a is formed to be raised with respect to the surrounding portion 6b. The portion 6b is formed flush with the lead electrode 8. The metal plate 6 provided with the raised portions 6a can be formed by a method known per se such as etching, press working, laser processing or the like.

この結果、半導体装置１ａでは、半導体パワー素子２のアノード電極２ａが形成されている端面と、隆起部６ａの周囲の部分６ｂの表面との間に、絶縁に十分な空間距離が確保される。また、半導体パワー素子２のアノード電極２ａが形成されている端面と、隆起部６ａの周囲の部分６ｂの表面との間には、樹脂層１３を形成する前記樹脂が空隙無く充填されている。   As a result, in the semiconductor device 1a, a sufficient spatial distance for insulation is ensured between the end surface where the anode electrode 2a of the semiconductor power element 2 is formed and the surface of the portion 6b around the raised portion 6a. Further, the resin forming the resin layer 13 is filled without a gap between the end surface of the semiconductor power element 2 where the anode electrode 2a is formed and the surface of the portion 6b around the raised portion 6a.

従って、半導体装置１ａでは、半導体パワー素子２のアノード電極２ａが形成されている端面と、金属板６との間の絶縁を確保し、優れた電気的信頼性を得ることができる。   Therefore, in the semiconductor device 1a, the insulation between the end surface where the anode electrode 2a of the semiconductor power element 2 is formed and the metal plate 6 can be ensured, and excellent electrical reliability can be obtained.

次に、本実施形態の第２の態様について説明する。図３に示すように、本実施形態の半導体装置１ｂは、金属板６が隆起部６ａの周囲に溝部６ｃを備え、隆起部６ａの表面がリード電極８の表面と面一になるように形成されている以外は、図１に示す半導体装置１ａと全く同一の構成を備えている。隆起部６ａ及び溝部６ｃを備える金属板６は、エッチング、プレス加工、レーザー加工等のそれ自体公知の方法により形成することができる。   Next, a second aspect of the present embodiment will be described. As shown in FIG. 3, in the semiconductor device 1 b of this embodiment, the metal plate 6 is provided with a groove 6 c around the raised portion 6 a, and the surface of the raised portion 6 a is flush with the surface of the lead electrode 8. Except for this, the semiconductor device 1a has the same configuration as the semiconductor device 1a shown in FIG. The metal plate 6 including the raised portions 6a and the groove portions 6c can be formed by a method known per se such as etching, press working, laser processing, or the like.

この結果、半導体装置１ｂでは、半導体パワー素子２のアノード電極２ａが形成されている端面と、隆起部６ａの周囲の溝部６ｃの底面との間に、絶縁に十分な空間距離が確保される。また、半導体パワー素子２のアノード電極２ａが形成されている端面と、隆起部６ａの周囲の溝部６ｃの底面との間には、樹脂層１３を形成する前記樹脂が空隙無く充填されている。   As a result, in the semiconductor device 1b, a sufficient spatial distance for insulation is ensured between the end surface where the anode electrode 2a of the semiconductor power element 2 is formed and the bottom surface of the groove 6c around the raised portion 6a. Further, the resin for forming the resin layer 13 is filled without a gap between the end surface of the semiconductor power element 2 where the anode electrode 2a is formed and the bottom surface of the groove 6c around the raised portion 6a.

従って、半導体装置１ｂでは、半導体パワー素子２のアノード電極２ａが形成されている端面と、金属板６との間の絶縁を確保し、優れた電気的信頼性を得ることができる。   Therefore, in the semiconductor device 1b, it is possible to ensure insulation between the end face where the anode electrode 2a of the semiconductor power element 2 is formed and the metal plate 6, and to obtain excellent electrical reliability.

１ａ，１ｂ…半導体装置、 ２…半導体パワー素子、 ２ａ…アノード（またはエミッタ）電極、３，４…絶縁基板、 ５，６，１０，１１…金属板、 ６ａ…隆起部、 ６ｃ…溝部、 ８，１２…リード電極、 １３…樹脂層。   DESCRIPTION OF SYMBOLS 1a, 1b ... Semiconductor device, 2 ... Semiconductor power element, 2a ... Anode (or emitter) electrode, 3, 4 ... Insulating substrate, 5, 6, 10, 11 ... Metal plate, 6a ... Raised part, 6c ... Groove part, 8 , 12 ... lead electrode, 13 ... resin layer.

Claims (2)

表裏両面に金属板を備え一方の金属板を主電極とすると共に、該主電極に接続されたリード電極を備える一対の絶縁基板と、
各絶縁基板の該主電極とされる金属板の間に挟持されて、該主電極に圧接されている半導体素子と、
各絶縁基板の該主電極とされる金属板と反対側の金属板表面と、各リード電極の一部とを露出して、各絶縁基板と該半導体素子と各リード電極とを封止する樹脂層とを備える半導体装置であって、
一方の該絶縁基板の該主電極は、該半導体素子のアノードまたはエミッタ電極に対する接続部として周囲の部分から隆起している隆起部と、該周囲の部分として該隆起部の周囲に形成され、その底面と該半導体素子の周囲の部分側の表面との間に絶縁に十分な空間距離を確保する溝部とを備え、
該隆起部の表面が該リード電極の半導体素子側の表面と面一となるように形成されていることを特徴とする半導体装置。 A pair of insulating substrates provided with metal plates on both the front and back sides and having one metal plate as a main electrode, and a lead electrode connected to the main electrode,
A semiconductor element sandwiched between the metal plates to be the main electrodes of each insulating substrate and pressed against the main electrodes;
Resin that exposes the surface of the metal plate opposite to the metal plate that is the main electrode of each insulating substrate and a part of each lead electrode to seal each insulating substrate, the semiconductor element, and each lead electrode A semiconductor device comprising a layer,
The main electrode of one of the insulating substrates is formed as a connection portion to the anode or emitter electrode of the semiconductor element from a surrounding portion, and as a surrounding portion, the main electrode is formed around the protruding portion. A groove portion that secures a sufficient spatial distance for insulation between the bottom surface and the surface of the peripheral portion side of the semiconductor element ;
A semiconductor device, wherein the surface of the raised portion is formed to be flush with the surface of the lead electrode on the semiconductor element side . 前記樹脂層は、ポリフェニレンサルファイド系樹脂、ポリイミド系樹脂、ポリアミド系樹脂からなる群から選択される１種の樹脂からなることを特徴とする請求項１記載の半導体装置。 2. The semiconductor device according to claim 1 , wherein the resin layer is made of one kind of resin selected from the group consisting of polyphenylene sulfide resin, polyimide resin, and polyamide resin .
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