JP5406554B2 - Imaging apparatus and imaging system - Google Patents

Description

  The present invention relates to an imaging apparatus and an imaging system.

  In recent years, video cameras for business use and home use using an imaging device have been widely used. In order to support television systems such as the NTSC system and the PAL system, an imaging device used for a video camera has an interlace operation mode in which signals are read every other row from a pixel array in which a plurality of pixels are arrayed in a two-dimensional manner. There is something to have. The interlace operation mode is also called an interlace readout mode, a field readout mode, and an interlace scanning readout mode.

  On the other hand, recently, an image input camera using an imaging device for a personal computer has been actively developed. Some image pickup apparatuses used for image input cameras have a progressive operation mode in which signals are read from each row of a pixel array in order to support a computer display method such as a progressive method. The progressive operation mode is also called a non-interlace readout mode or an all-pixel readout mode. In the progressive operation mode, the imaging device reads signals of pixels in all rows in the pixel array.

  Patent Document 1 describes a solid-state imaging device corresponding to both readout operations of an all-row readout operation (in a progressive operation mode) and a vertical addition readout operation (in an interlace operation mode).

  In the all-row reading operation, odd rows and even rows in the pixel array 407 shown in FIG. 1 of Patent Document 1 are alternately and sequentially selected by the vertical scanning circuits 420o and 420e, and signals at the respective pixels are read out. That is, as shown in FIG. 2 of Patent Document 1, the signal φEVEN for turning on the MOS switch 421o and the signal φODD for turning on the MOS switch 421e alternately become high level. When the MOS switch 421o is turned on, the signals of the selected pixels in the odd-numbered rows are transferred to both the capacitive element 412o and the capacitive element 412e. When the MOS switch 421e is turned on, the signals of the selected pixels in the even-numbered rows are transferred to both the capacitive element 412o and the capacitive element 412e. In the all-row read operation, since signals are input to two capacitors, the S / N ratio can be improved by increasing the gain at the column amplifier as compared with the case where a signal is input to only one of the two capacitors. It is supposed to be possible.

  In the vertical addition readout operation, odd rows and even rows in the pixel array 407 shown in FIG. 1 of Patent Document 1 are simultaneously selected by the vertical scanning circuits 420o and 420e, and signals in the respective pixels are read out simultaneously. That is, as shown in FIG. 3 of Patent Document 1, the signal φEVEN for turning on the MOS switch 421o and the signal φODD for turning on the MOS switch 421e are simultaneously set to the high level. At this time, since the signal φOE is at a low level and the MOS switch 422 is in an off state, when the MOS switches 421o and 421e are simultaneously turned on, the signals of the selected odd-numbered and even-numbered pixels are respectively connected to the capacitive elements 412o, 412e is simultaneously transferred. The signals transferred to the capacitive elements 412o and 412e are averaged at the inverting input terminal (−) of the operational amplifier 211. In the vertical addition read operation, the field read time is half that of the all-row read operation.

On the other hand, Patent Document 2, signals amplified by the configured column amplifier MOS transistors M1 and the MOS transistor M2 Metropolitan outputted from the photoelectric conversion element is described to be stored in the temporary storage capacitors C _T . Thus, according to Patent Document 2, without increasing the value of the temporary storage capacitor C _T, it is possible to increase the read gain, preventing the S / N ratio degradation due to noise charge of the output signal line It is supposed to be possible.

JP 2005-348040 A JP-A-2-296470

  In the solid-state imaging device described in Patent Document 1, when the MOS switch 421o is turned on in the vertical addition reading operation (in the interlace operation mode), the signal is transferred to the capacitive element 412o and not transferred to the capacitive element 412e. When the MOS switch 421e is turned on, the signal is transferred to the capacitor 412e and not transferred to the capacitor 412o. That is, the signal of each pixel is input to only one of the capacitor 412o and the capacitor 412e. For this reason, in the interlaced operation mode (first mode), the gain of the column amplifier becomes lower and the S / N ratio of the signal becomes worse than in the progressive operation mode (second mode). Deteriorates.

  An object of the present invention is to improve the S / N ratio of a signal output from a pixel in the first mode.

An imaging apparatus according to a first aspect of the present invention includes a photoelectric conversion unit, a charge-voltage conversion unit, a transfer unit that transfers charges generated in the photoelectric conversion unit to the charge-voltage conversion unit, and a voltage of the charge-voltage conversion unit. An imaging apparatus comprising: a pixel array in which a plurality of pixels each including an output unit that outputs a corresponding signal is two-dimensionally arrayed; and a plurality of column amplifiers that amplify signals from the pixel array, The column amplification unit includes an input capacitance unit and a feedback capacitance unit, and each column of the pixel array includes a plurality of first pixels from which the output unit outputs a signal to a first signal line, and And an output unit including a plurality of second pixels that respectively output signals to the second signal line, the imaging device having a first imaging mode and a second imaging mode, wherein the imaging device When in the first shooting mode and when in the second shooting mode In each case, the column amplification unit is configured to amplify a signal according to a ratio of a capacitance value of the input capacitance unit and a capacitance value of the feedback capacitance unit, and the first signal The capacitance value of the feedback capacitor in the first mode for amplifying the sum of the signal transmitted via the line and the signal transmitted via the second signal line is obtained via the first signal line. And the column amplifying unit is configured to reduce the capacitance value of the feedback capacitance unit in a second mode for amplifying the signal transmitted via the second signal line and the signal transmitted via the second signal line at different timings. wherein the capacitance value of the feedback capacitance section in the first mode, the feedback capacitance in the second mode when the imaging device is in the second imaging mode when the image device is in a first imaging mode With the same capacitance value That.

  An imaging system according to a second aspect of the present invention processes the imaging device according to the first aspect of the present invention, an optical system that forms an image on the imaging surface of the imaging device, and a signal output from the imaging device. And a signal processing unit for generating image data.

  According to the present invention, it is possible to improve the S / N ratio of the signal output from the pixel in the first mode.

1 is a diagram illustrating a configuration of an imaging apparatus 100 according to a first embodiment of the present invention. The figure which shows the structure of each pixel in 1st Embodiment of this invention. 6 is a timing chart showing an operation in the second mode of the imaging apparatus 100 according to the first embodiment of the present invention. 3 is a timing chart showing an operation in the first mode of the imaging apparatus 100 according to the first embodiment of the present invention. The figure which shows the other structure of each pixel in 1st Embodiment of this invention. 1 is a configuration diagram of an imaging system to which an imaging apparatus according to a first embodiment is applied. The figure which shows a part of structure of the column amplifier 110i in 2nd Embodiment of this invention.

  An imaging apparatus 100 according to a first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a diagram illustrating a configuration of an imaging apparatus 100 according to the first embodiment of the present invention.

  The imaging apparatus 100 includes a pixel array 107, a drive unit 120, a plurality of column amplification units 110, a plurality of holding units 140, a horizontal scanning circuit 130, and an output amplifier 119.

  In the pixel array 107, a plurality of pixels P11 to Pmn are two-dimensionally arranged. Each column of the pixel array 107 includes a plurality of first pixels P2k-1, p (k = 1, 2,..., M / 2, p = 1, 2,..., N) and a plurality of first pixels. 2 pixels P2k, p (k = 1, 2,..., M / 2, p = 1, 2,..., N). In each column of the pixel array 107, the first pixels P2k-1, p and the second pixels P2k, p are alternately arranged in the direction along the column. The first pixels P <b> 2 k-1, p are pixels in odd rows in the pixel array 107. The second pixels P <b> 2 k and p are pixels in even rows in the pixel array 107. For each column of the pixel array 107, the first signal line 106o to which the first pixels P2k-1 and p are connected and the second signal line 106e to which the second pixels P2k and p are connected. Two signal lines are provided.

  Here, the imaging apparatus 100 has a first mode and a second mode as operation modes. The first mode is, for example, an interlace operation mode. In the first mode, the signal of the first pixel and the signal of the second pixel adjacent in the column direction in the pixel array 107 are read in parallel and the sum of the two is amplified. The second mode is, for example, a progressive operation mode. In the second mode, the signal of the first pixel and the signal of the second pixel adjacent in the column direction in the pixel array 107 are read and amplified at different timings.

  The first pixel P2k-1, p and the second pixel P2k, p each include a configuration as shown in FIG. 2, for example. FIG. 2 is a diagram showing a configuration of each pixel in the first embodiment of the present invention.

  As shown in FIG. 2, the first pixel P2k-1, p includes a photoelectric conversion unit 201o, a transfer unit 203o, a charge-voltage conversion unit 207o, a reset unit 204o, an output unit 202o, and a selection unit 205o.

  The photoelectric conversion unit 201o generates and accumulates charges corresponding to light. The photoelectric conversion unit 201o is, for example, a photodiode.

  The transfer unit 203o transfers the charge generated in the photoelectric conversion unit 201o to the charge / voltage conversion unit 207o. The transfer unit 203o is, for example, a transfer transistor, and is turned on when an active level transfer control signal is supplied to the gate from a vertical scanning circuit 121o to be described later, whereby charge generated in the photoelectric conversion unit 201o is converted into a charge voltage. Forward to the unit 207o.

  The charge-voltage converter 207o converts the transferred charge into a voltage. The charge voltage conversion unit 207o is, for example, a floating diffusion.

  The reset unit 204o resets the charge voltage conversion unit 207o. The reset unit 204o is, for example, a reset transistor, and resets the charge-voltage conversion unit 207o by turning on when an active level reset control signal is supplied from the vertical scanning circuit 121o to the gate.

  The output unit 202o outputs a signal corresponding to the voltage of the charge-voltage conversion unit 207o to the first signal line 106o. The output unit 202o is, for example, an amplification transistor, and performs a source follower operation together with the current source load 109o connected to the first signal line 106o, so that a signal corresponding to the voltage of the charge voltage conversion unit 207o is output to the first signal line 106o. The signal is output to the signal line 106o. That is, the output unit 202o outputs a noise signal corresponding to the voltage of the charge voltage conversion unit 207o to the first signal line 106o in a state where the charge voltage conversion unit 207o is reset by the reset unit 204o. The output unit 202o outputs an optical signal corresponding to the voltage of the charge voltage conversion unit 207o to the first signal line 106o in a state where the charge generated in the photoelectric conversion unit 201o is transferred to the charge voltage conversion unit 207o by the transfer unit 203o. To do.

  The selection unit 205o puts the first pixels P2k-1, p into the selected state / non-selected state. The selection unit 205o is, for example, a selection transistor, and is turned on when an active level selection control signal is supplied from the vertical scanning circuit 121o to the gate, thereby bringing the first pixels P2k-1 and p into a selected state. . The selection unit 205o turns off when the selection control signal of the non-active level is supplied from the vertical scanning circuit 121o to the gate, thereby deselecting the first pixels P2k-1, p.

  Note that the first pixel P2k-1, p may have a configuration without the selection unit 205o as shown in FIG. In this case, the selection state / non-selection state of the first pixels P2k-1, p is controlled according to the voltage level of the charge-voltage conversion unit 207o. The reset unit 204o resets the charge-voltage conversion unit 207o and puts the first pixels P2k-1 and p into the selected / non-selected state according to the power level. The reset unit 204o selects the first pixels P2k-1 and p by resetting the potential of the charge voltage conversion unit 53 to the first potential according to the supplied first potential (for example, L level). Put it in a state. The reset unit 54 resets the potential of the charge-voltage conversion unit 53 to the second potential in accordance with the supplied second potential (for example, H level), so that the first pixels P2k-1 and p are not turned on. Select.

  As shown in FIG. 2, the second pixel P2k, p includes a photoelectric conversion unit 201e, a transfer unit 203e, a charge-voltage conversion unit 207e, a reset unit 204e, an output unit 202e, and a selection unit 205e.

  The photoelectric conversion unit 201e generates and accumulates charges corresponding to light. The photoelectric conversion unit 201e is, for example, a photodiode.

  The transfer unit 203e transfers the charge generated in the photoelectric conversion unit 201e to the charge voltage conversion unit 207e. The transfer unit 203e is, for example, a transfer transistor, and is turned on when an active level transfer control signal is supplied to the gate from a vertical scanning circuit 121e described later, thereby converting the charge generated in the photoelectric conversion unit 201e into a charge-voltage converter. Forward to the unit 207e.

  The charge-voltage conversion unit 207e converts the transferred charge into a voltage. The charge-voltage conversion unit 207e is, for example, a floating diffusion.

  The reset unit 204e resets the charge voltage conversion unit 207e. The reset unit 204e is, for example, a reset transistor, and resets the charge-voltage conversion unit 207e by turning on when an active level reset control signal is supplied from the vertical scanning circuit 121e to the gate.

  The output unit 202e outputs a signal corresponding to the voltage of the charge-voltage conversion unit 207e to the second signal line 106e. The output unit 202e is, for example, an amplification transistor, and performs a source follower operation together with the current source load 109e connected to the second signal line 106e, so that a signal corresponding to the voltage of the charge-voltage conversion unit 207e is output to the second signal line 106e. The signal is output to the signal line 106e. That is, the output unit 202e outputs a noise signal corresponding to the voltage of the charge voltage conversion unit 207e to the second signal line 106e in a state where the charge voltage conversion unit 207e is reset by the reset unit 204e. The output unit 202e outputs an optical signal corresponding to the voltage of the charge voltage conversion unit 207e to the second signal line 106e in a state where the charge generated in the photoelectric conversion unit 201e is transferred to the charge voltage conversion unit 207e by the transfer unit 203e. To do.

  The selection unit 205e puts the second pixels P2k and p into a selected state / non-selected state. The selection unit 205e is, for example, a selection transistor, and is turned on when an active level selection control signal is supplied from the vertical scanning circuit 121e to the gate, thereby bringing the second pixels P2k and p into a selected state. The selection unit 205e turns off when the non-active level selection control signal is supplied to the gate from the vertical scanning circuit 121e, thereby deselecting the second pixels P2k and p.

  Note that the second pixels P2k and p may have a configuration without the selection unit 205e as illustrated in FIG. In this case, the selection state / non-selection state of the second pixels P2k, p is controlled according to the voltage level of the charge voltage conversion unit 207e. The reset unit 204e resets the charge-voltage conversion unit 207e and sets the second pixels P2k and p in the selected / non-selected state according to the power level. The reset unit 204e puts the second pixels P2k and p into a selected state by resetting the potential of the charge-voltage conversion unit 53 to the first potential according to the supplied first potential (for example, L level). To do. The reset unit 54 resets the potential of the charge-voltage conversion unit 53 to the second potential according to the supplied second potential (for example, H level), so that the second pixels P2k and p are not selected. To.

  The driving unit 120 performs the first operation and the second operation in parallel in each column of the pixel array 107 in the first mode, and performs the first operation in each column of the pixel array 107 in the second mode. The pixel array 107 is driven so that the second operation and the second operation are performed at different timings. In the first operation, a signal is transmitted from the first pixel P2k−1, p to the column amplifier 110 via the first signal line 106o. In the second operation, a signal is transmitted from the second pixel P2k, p to the column amplifier 110 via the second signal line 106e. The drive unit 120 includes vertical scanning circuits 121o and 121e. The driving unit 120 may further include a timing generation unit 98 described later.

  The vertical scanning circuit 121o scans the pixels in the odd rows, that is, the 2k-1 (k = 1, 2,..., M / 2) rows in the pixel array 107 in the vertical direction, thereby performing the 2k-1 row. The pixels are sequentially selected, and a signal is output from the selected pixel on the 2k-1 row. That is, the vertical scanning circuit 121o drives the first pixels P2k-1 and p so that the first operation is performed.

  The vertical scanning circuit 121e sequentially scans the pixels in the 2k row by scanning the pixels in the even row, that is, the 2k (k = 1, 2,..., M / 2) row in the pixel array 107 in the vertical direction. A signal is output from the selected pixel in the 2k row. That is, the vertical scanning circuit 121e drives the second pixels P2k and p so that the second operation is performed.

  In the first mode, driving of the first operation by the vertical scanning circuit 121o and driving of the second operation by the vertical scanning circuit 121e are performed in parallel. In the second mode, the driving of the first operation by the vertical scanning circuit 121o and the driving of the second operation by the vertical scanning circuit 121e are performed at different timings.

  The plurality of column amplifying units 110 includes a plurality of signals transmitted from the pixel array 107 via the plurality of first signal lines 106o and a plurality of signals transmitted from the pixel array 107 via the plurality of second signal lines 106e. Amplify at least one of the signals. The plurality of column amplification units 110 correspond to the plurality of columns in the pixel array 107.

  The column amplifier 110 of each column amplifies the sum of the signal transmitted via the first signal line 106o and the signal transmitted via the second signal line 106e in the first mode. In the second mode, the column amplifier 110 amplifies the signal transmitted via the first signal line 106o and the signal transmitted via the second signal line 106e at different timings.

  Specifically, the column amplifier 110 includes vertical transfer switches 122o and 122e, a differential amplifier 111, an input capacitor 112, a feedback capacitor 113, a switching unit 114, and a clamp control switch 115. The column amplifying unit 110 is configured to amplify a signal according to the ratio between the capacitance value of the input capacitance unit 112 and the capacitance value of the feedback capacitance unit 113, and the capacitance of the feedback capacitance unit 113 in the first mode. The value is made smaller than the capacitance value of the feedback capacitor 113 in the second mode. That is, in the column amplification unit 110, the capacitance value of the input capacitance unit 112 in the first mode is larger than the capacitance value of the input capacitance unit 112 in the second mode. In response to this, the column amplification unit 110 sets the capacitance value of the feedback capacitance unit 113 so that the capacitance value of the feedback capacitance unit 113 in the first mode is smaller than the capacitance value of the feedback capacitance unit 113 in the second mode. Switch. That is, the column amplification unit 110 switches the capacitance value of the feedback capacitance unit 113 so that the amplification factor of the signal in the first mode is equal to the amplification factor of the signal in the second mode.

  The vertical transfer switch 122o is turned on when an active level control signal φODD is supplied from the vertical scanning circuit 121o (or a timing generation unit 98 described later), thereby transmitting a signal transmitted via the first signal line 106o. Is transferred to the first input capacitor 112o.

  The vertical transfer switch 122e is turned on when an active level control signal φEVEN is supplied from the vertical scanning circuit 121e (or a timing generation unit 98 described later), whereby a signal transmitted via the second signal line 106e. Is transferred to the second input capacitor 112e.

  The differential amplifier 111 has a first input terminal 111a, a second input terminal 111b, and an output terminal 111c. A first input capacitor 112o and a second input capacitor 112e are connected to the first input terminal 111a. The first input terminal 111a is, for example, a non-inverting input terminal (−). A reference voltage VREF is supplied to the second input terminal 111b. The second input terminal 111b is, for example, an inverting input terminal (+). A holding unit 140 is connected to the output terminal 111c.

  The input capacitor unit 112 includes a first input capacitor 112o, a second input capacitor 112e, and a first switch 123. The first input capacitor 112o includes a first electrode 112o1 and a second electrode 112o2. The first electrode 112o1 receives a signal transmitted via the first signal line 106o when the vertical transfer switch 122o is turned on. The second electrode 112o2 is connected to the fourth electrode 112e2 and the first input terminal 111a of the differential amplifier 111.

  The second input capacitor 112e has a third electrode 112e1 and a fourth electrode 112e2. The third electrode 112e1 receives a signal transmitted through the second signal line 106e when the vertical transfer switch 122e is turned on. The fourth electrode 112e2 is connected to the second electrode 112o2 and the first input terminal 111a of the differential amplifier 111.

  The first switch 123 is turned on when an active level control signal φOE is supplied from the vertical scanning circuit 121o (or the vertical scanning circuit 121e or a timing generation unit 98 described later). In the first mode, the first switch 123 is turned off so as to block the first electrode 112o1 and the third electrode 112e1. In the second mode, the first switch 123 is turned on so as to connect the first electrode 112o1 and the third electrode 112e1.

  The feedback capacitor 113 is disposed between the output terminal 111c of the differential amplifier 111 and the first input terminal 111a. The feedback capacitor 113 includes a feedback capacitor (third capacitor) 113a and a feedback capacitor (fourth capacitor) 113b. The feedback capacitor 113a includes a fifth electrode 113a1 and a sixth electrode 113a2. The fifth electrode 113 a 1 is disposed on the first input terminal 111 a side of the differential amplifier 111. The sixth electrode 113a6 is disposed on the output terminal 111c side of the differential amplifier 111. The feedback capacitor 113b includes a seventh electrode 113b1 and an eighth electrode 113b2. The seventh electrode 113b1 is disposed on the first input terminal 111a side of the differential amplifier 111. The eighth electrode 113b6 is disposed on the output terminal 111c side of the differential amplifier 111. Here, the capacitance value of the feedback capacitor 113b is smaller than the capacitance value of the feedback capacitor 113a. The capacitance value of the feedback capacitor 113b is substantially equal to half the capacitance value of the feedback capacitor 113a, for example.

  The switching unit 114 switches the capacitance value of the feedback capacitance unit 113 so that the capacitance value of the feedback capacitance unit 113 in the first mode is smaller than the capacitance value of the feedback capacitance unit 113 in the second mode. The switching unit 114 includes a plurality of switches 114a and 114b.

  The switching unit 114 switches to the first state by turning off the switch 114a and turning on the switch 114b in the first mode. In the first state, the seventh electrode 113b1 in the feedback capacitor 113b is connected to the first input terminal 111a of the differential amplifier 111, and the eighth electrode 113b6 is connected to the output terminal 111c of the differential amplifier 111. In the first state, the fifth electrode 113a1 in the feedback capacitor 113a is cut off from the first input terminal 111a of the differential amplifier 111, or the sixth electrode 113a6 is cut off from the output terminal 111c of the differential amplifier 111. ing.

  The switching unit 114 switches to the second state by turning on the switch 114a and turning off the switch 114b in the first mode. In the second state, the fifth electrode 113a1 in the feedback capacitor 113a is connected to the first input terminal 111a of the differential amplifier 111, and the sixth electrode 113a6 is connected to the output terminal 111c of the differential amplifier 111. In the second state, the seventh electrode 113b1 in the feedback capacitor 113b is cut off from the first input terminal 111a of the differential amplifier 111, or the eighth electrode 113b6 is cut off from the output terminal 111c of the differential amplifier 111. ing.

  The clamp control switch 115 controls the clamp operation in the column amplification unit 110. When the clamp control switch 115 is turned on, the clamp control switch 115 short-circuits between the output terminal 111c and the first input terminal 111a in the differential amplifier 111, and a noise signal to the first input capacitor 112o and the second input capacitor 112e. To be sampled. When the clamp control switch 115 is turned off, the clamp control switch 115 cancels the short circuit between the output terminal 111c and the first input terminal 111a in the differential amplifier 111, and the first input capacitor 112o and the second input capacitor 112e. The noise signal is held. Thereafter, when an optical signal is transferred from the pixel, the first input capacitor 112o and the second input capacitor 112e generate a differential signal and transmit it to the differential amplifier 111. The difference signal is a signal obtained by taking the difference between the optical signal output from the pixel and the noise signal.

  That is, the column amplifier 110 outputs the offset of the differential amplifier 111 as an N signal in the first period. In the second period, the column amplification unit 110 obtains a differential signal between the optical signal output from the pixel and the noise signal, and outputs a signal in which the offset of the differential amplifier 111 is superimposed on the differential signal as an S signal. . Thereby, a differential signal from which the noise signal is removed from the optical signal can be obtained.

  The plurality of holding units 140 temporarily hold a plurality of signals (a plurality of N signals and a plurality of S signals) output from the plurality of column amplification units 110. The plurality of holding units 140 correspond to the plurality of column amplification units 110 and correspond to the plurality of columns in the pixel array 107. The plurality of holding units 140 function as line memories for holding signals output from selected rows in the pixel array 107. Each column holding unit 140 includes transfer switches 116s and 116n, holding capacitors 117s and 117n, and horizontal transfer switches 118s and 118n.

  The transfer switch 116n is turned on when an active level control signal φTN is supplied in the first period, thereby transferring the N signal output from the column amplifier 110 to the holding capacitor 117n. Thereafter, the transfer switch 116n is turned off. Thereby, the holding capacitor 117n holds the N signal.

  The transfer switch 116s is turned on when the active level control signal φTS is supplied in the second period, thereby transferring the S signal output from the column amplifier 110 to the storage capacitor 117s. Thereafter, the transfer switch 116s is turned off. As a result, the holding capacitor 117s holds the S signal.

  The horizontal transfer switch 118n is turned on when the active level control signal φH is supplied, thereby transferring the N signal held in the holding capacitor 117n to the horizontal output line 131n. The horizontal transfer switch 118s is turned on when an active level control signal φH is supplied to transfer the S signal held in the holding capacitor 117s to the horizontal output line 131s.

  The horizontal scanning circuit 130 sequentially turns on the horizontal transfer switches 118s and 118n of each column by scanning the plurality of holding units 140 in the horizontal direction (the control signal φH of each column is sequentially set to the active level). As a result, the signals (S signal and N signal) held in the holding capacitors 117s and 117n of each column are sequentially transferred to the horizontal output lines 131s and 131n.

  The output amplifier 119 generates an image signal by taking the difference between the S signal transmitted through the horizontal output line 131s and the N signal transmitted through the horizontal output line 131n. Thereby, an image signal obtained by removing the offset (N signal) of the differential amplifier 111 from the S signal can be obtained. The output amplifier 119 outputs the generated image signal to a subsequent stage (an imaging signal processing circuit 95 described later).

  Here, in the first mode, the first switch 123 in the column amplifier 110 is turned off so as to block the first electrode 112o1 and the third electrode 112e1. Thereby, in the first mode, a signal output from the first pixel P2k-1, p is input to the first electrode 112o1 in the first input capacitor 112o and output from the second pixel P2k, p. The received signal is input to the third electrode 112e1 in the second input capacitor 112e. Then, the second electrode 112o2 in the first input capacitor 112o and the fourth electrode 112e2 in the second input capacitor 112e add or average the signals of the two to obtain a first input terminal 111a of the differential amplifier 111. To communicate.

  In the first mode, the switching unit 114 switches to the first state by turning off the switch 114a and turning on the switch 114b. Accordingly, the capacitance value of the first input capacitor 112o, the capacitance value of the second input capacitor 112e, the capacitance value of the feedback capacitor 113a, and the capacitance value of the feedback capacitor 113b are respectively C1, C1, C2, and (C2 / 2). Then, the amplification factor of the signal of the column amplification unit 110 in the first mode is as follows.

AF = k × (C1) / (C2 / 2)
= 2k × (C1) / (C2) Equation 1
In Equation 1, k is a proportionality constant.

  In addition, the first switch 123 in the column amplification unit 110 is turned on so as to connect the first electrode 112o1 and the third electrode 112e1 in the second mode. As a result, in the second mode, the signals output from the first pixels P2k-1, p are the first electrode 112o1 in the first input capacitor 112o and the third electrode 112e1 in the second input capacitor 112e. And is input to. Then, the second electrode 112 o 2 in the first input capacitor 112 o and the fourth electrode 112 e 2 in the second input capacitor 112 e transmit the signals to the first input terminal 111 a of the differential amplifier 111. Alternatively, a signal output from the second pixel P2k, p is input to the first electrode 112o1 in the first input capacitor 112o and the third electrode 112e1 in the second input capacitor 112e. Then, the second electrode 112 o 2 in the first input capacitor 112 o and the fourth electrode 112 e 2 in the second input capacitor 112 e transmit the signals to the first input terminal 111 a of the differential amplifier 111.

  In the second mode, the switching unit 114 switches to the second state by turning on the switch 114a and turning off the switch 114b. Accordingly, the capacitance value of the first input capacitor 112o, the capacitance value of the second input capacitor 112e, the capacitance value of the feedback capacitor 113a, and the capacitance value of the feedback capacitor 113b are respectively C1, C1, C2, and (C2 / 2). Then, the amplification factor of the signal of the column amplification unit 110 in the second mode is as follows.

AF = k × (C1 + C1) / (C2)
= 2k × (C1) / (C2) Equation 2
In Equation 2, k is the same proportionality constant as in Equation 1.

  As described above, the switching unit 114 switches the capacitance value of the feedback capacitance unit 113 so that the capacitance value of the feedback capacitance unit 113 in the first mode is smaller than the capacitance value of the feedback capacitance unit 113 in the second mode. That is, as shown in Equation 1 and Equation 2, the column amplification unit 110 has a capacitance value of the feedback capacitance unit 113 so that the amplification factor of the signal in the first mode is equal to the amplification factor of the signal in the second mode. Is switched to switch the signal. Thereby, the S / N ratio of the signal in the first mode can be improved to the same level as the S / N ratio of the signal in the second mode. Therefore, the S / N ratio of the signal output from the pixel in both the first mode and the second mode can be improved.

  Next, the operation in the second mode of the imaging apparatus 100 according to the first embodiment of the present invention will be described with reference to FIG. FIG. 3 is a timing chart showing an operation in the second mode of the imaging apparatus 100 according to the first embodiment of the present invention. The second mode is, for example, a progressive operation mode.

  In the second mode, pixels in odd rows, that is, 2k-1 rows (k = 1, 2,... M / 2) and even rows, that is, 2k rows (k = 1, 2,... M / 2). ) Pixels are sequentially selected alternately by the drive unit 120, and signals are read out from the respective pixels at different timings.

  In FIG. 3, φSEL (2k−1), φRES (2k−1), and φTX (2k−1) are supplied from the vertical scanning circuit 121o to the first pixels P2k−1 and p in the 2k−1 row. It is a control signal. φSEL (2k), φRES (2k), and φTX (2k) are control signals supplied from the vertical scanning circuit 121e to the second pixels P2k and p in the second k row. φOE, φODD, φEVEN, φCLMP, φTN, and φTS are signals supplied from the vertical scanning circuit 121o, the vertical scanning circuit 121e, or the timing generation unit 98 to corresponding elements.

  At time t0, the control signal φODD becomes active level, and the vertical transfer switch 122o is turned on. Further, the control signal φOE is at the active level, and the first switch 123 is turned on.

  The reset control signal φRES (2k−1) is at an active level, and the reset unit 204o in the first pixels P2k−1 and p in the 2k−1 row resets the charge voltage conversion unit 207o. The reset control signal φRES (2k) is at the active level, and the reset unit 204e in the second pixels P2k and p in the 2k row resets the charge voltage conversion unit 207e.

  At time t1, the reset control signal φRES (2k−1) becomes a non-active level, and the reset operation of the charge voltage conversion unit 207o by the reset unit 204o in the first pixels P2k−1 and p in the 2k−1 row is completed. .

  At time t2, the selection control signal φSEL (2k−1) becomes an active level, and the selection unit 205 in the first pixel P2k−1, p in the second k−1 row selects the first pixel P2k−1, p. To. The source of the output section (amplification transistor) 202o in the first pixel P2k-1, p is in a state of being electrically connected to the first signal line 206o. A source follower circuit is formed by the output unit 202o and the current source load 109o in the selected first pixel P2k-1, p. The output unit 202o in the selected first pixel P2k-1, p receives a noise signal corresponding to the voltage of the charge voltage conversion unit 207o as the first signal in a state where the charge voltage conversion unit 207o is reset by the reset unit 204o. Output to line 106o. The noise signal output to the first signal line 106o is transmitted to the first electrode 112o1 in the first input capacitor 112o and the first electrode 112o1 in the second input capacitor 112e.

  On the other hand, the selection control signal φSEL (2k) remains at the non-active level, and the selection unit 205 in the second pixels P2k, p in the second k row keeps the second pixels P2k, p in a non-selected state. .

  When the control signal φCLMP becomes active level at time t3, the first input terminal 111a and the output terminal 111c of the differential amplifier 111 are short-circuited, so that the noise signal is clamped to the reference voltage VREF. At this time, the differential amplifier 111 outputs the offset. That is, the column amplifier 110 outputs the offset of the differential amplifier 111 as an N signal.

  At time t4, the control signal φTN becomes an active level. When the transfer switch 116n is turned on, the N signal is transferred to the holding capacitor 117n. Thereafter, when the control signal φTN becomes a non-active level, the transfer switch 116n is turned off. Thereby, the holding capacitor 117n holds the N signal.

  At time t5, the transfer control signal φTX (2k−1) becomes an active level, and the transfer unit 203o in the first pixel P2k−1, p in the 2k−1th row charges the charge generated in the photoelectric conversion unit 201o. Transfer to the voltage converter 207o. The output unit 202o outputs an optical signal corresponding to the voltage of the charge voltage conversion unit 207o to the first signal line 106o in a state where the charge generated in the photoelectric conversion unit 201o is transferred to the charge voltage conversion unit 207o by the transfer unit 203o. To do. The optical signal output to the first signal line 106o is transmitted to the first electrode 112o1 in the first input capacitor 112o and the first electrode 112o1 in the second input capacitor 112e. The first input capacitor 112o and the second input capacitor 112e generate a differential signal and transmit it to the differential amplifier 111. The difference signal is a signal obtained by taking the difference between the optical signal output from the pixel and the noise signal. The differential amplifier 111 outputs a signal in which an offset is superimposed on the differential signal. That is, the column amplification unit 110 outputs a signal in which the offset of the differential amplifier 111 is superimposed on the differential signal as an S signal.

  At time t6, the control signal φTS becomes an active level. When the transfer switch 116s is turned on, the transfer signal is transferred to the storage capacitor 117s. Thereafter, when the control signal φTS becomes an inactive level, the transfer switch 116s is turned off. As a result, the holding capacitor 117s holds the S signal.

  At time t7, the control signal φODD becomes inactive level, and the vertical transfer switch 122o is turned off.

  Thereafter, during the horizontal scanning period from time t7 to time t8, the N signal and S signal of the column selected by the horizontal scanning circuit 130 are read, and the output amplifier 119 calculates the difference between the correlated N signal and S signal. By taking this, an image signal is obtained.

  At time t8, the control signal φEVEN becomes active level and the vertical transfer switch 122e is turned on. After time t8, the same operation as that in which the first pixel P2k-1, p in the operation from time t0 to t8 is replaced with the second pixel P2k, p is performed.

In the operation of the second mode shown in FIG. 3, φgain1 is set to the active level and φgain2 is set to the active level. As a result, the feedback capacitor 113 a is taken into the feedback path of the differential amplifier 111, and the feedback capacitor 113 b cannot be taken into the feedback path of the differential amplifier 111. For example, the capacitance values of the first input capacitor 112o and the second input capacitor 112e are both 200 fF, and the capacitance value of the feedback capacitor 113a is 100 fF. Since the first electrode 112o1 in the first input capacitor 112o and the third electrode 112e1 in the second input capacitor 112e are used by being short-circuited, the gain of the column amplifier 110 in the above numerical example is
AF = (200 fF + 200 fF) / (100 fF)
= 4 Equation 3
It becomes.

  Next, the operation in the first mode of the imaging apparatus 100 according to the first embodiment of the present invention will be described with reference to FIG. FIG. 4 is a timing chart showing the operation in the first mode of the imaging apparatus 100 according to the first embodiment of the present invention. The first mode is, for example, an interlace operation mode. Below, it demonstrates centering on a different part from the operation | movement in a 2nd mode.

  At time t10, the control signal φODD and the control signal φEVEN are at the active level, and the vertical transfer switches 122o and 122e are turned on. Further, the control signal φOE is at the non-active level, and the first switch 123 is off.

  At time t11, in addition to the reset control signal φRES (2k−1), the reset control signal φRES (2k) becomes a non-active level. The reset operation of the charge voltage conversion unit 207e by the reset unit 204e in the second pixels P2k, p in the second k row is completed.

  At time t12, in addition to the selection control signal φSEL (2k−1), the selection control signal φSEL (2k) becomes an active level. The selection unit 205e in the second pixels P2k, p in the second k row sets the second pixels P2k, p in a selected state. The output unit 202o in the first pixel P2k-1, p outputs a noise signal to the first signal line 106o, and the output unit 202e in the second pixel P2k, p sends the noise signal to the second signal line 106e. Output. The noise signal output to the first signal line 106o is transmitted to the first electrode 112o1 in the first input capacitor 112o, and the noise signal output to the second signal line 106e is transmitted to the second input capacitor 112e. Is transmitted to the third electrode 112e1.

  At time t15, in addition to the transfer control signal φTX (2k−1), the transfer control signal φTX (2k) becomes an active level. The transfer unit 203e in the second pixels P2k, p in the 2k-th row transfers charges generated in the photoelectric conversion unit 201e to the charge-voltage conversion unit 207e. The output unit 202o in the first pixel P2k-1, p outputs an optical signal to the first signal line 106o, and the output unit 202e in the second pixel P2k, p sends the optical signal to the second signal line 106e. Output. The optical signal output to the first signal line 106o is transmitted to the first electrode 112o1 in the first input capacitor 112o, and the optical signal output to the second signal line 106e is the second input capacitor 112e. Is transmitted to the third electrode 112e1. The first input capacitor 112o and the second input capacitor 112e each generate a differential signal. Then, the second electrode 112o2 in the first input capacitor 112o and the fourth electrode 112e2 in the second input capacitor 112e add or average the difference signals of the two, and the first input terminal of the differential amplifier 111 To 111a.

  At time t17, the control signals φODD and φEVEN remain at the active level.

  The operation at times t10 to t17 can be regarded as a superposition of the operation at times t0 to t7 and the operation at times t8 to t9 in FIG. That is, in the first mode, the signal is read every two rows in the pixel array 107, so that the readout time for one field is half that of the second mode.

In the operation of the first mode shown in FIG. 4, φgain1 is set to the non-active level and φgain2 is set to the active level. As a result, the feedback capacitor 113 b is taken into the feedback path of the differential amplifier 111, and the feedback capacitor 113 a cannot be taken into the feedback path of the differential amplifier 111. For example, the capacitance values of the first input capacitor 112o and the second input capacitor 112e are both 200 fF, and the capacitance value of the feedback capacitor 113a is 100 fF. The capacitance value of the feedback capacitor 113b is 50 fF, which is half the capacitance value of the feedback capacitor 113a. The gain of the column amplification unit 110 in this numerical example is
AF = 200 fF / (50 fF)
= 4 Equation 4
It becomes.

  Note that the feedback capacitor 113 may include a plurality of fifth capacitors (not shown) having the same capacitance value. Each fifth capacitor has a ninth electrode and a tenth electrode. In each fifth capacitor, the ninth electrode is disposed on the first input terminal 111 a side of the differential amplifier 111, and the tenth electrode is disposed on the output terminal 111 c side of the differential amplifier 111.

  In this case, the switching unit 114 includes a plurality of second switches corresponding to a plurality of fifth capacitors. Each of the plurality of second switches switches to either the third state or the fourth state. In the third state, the ninth electrode in the fifth capacitor is connected to the first input terminal 111a of the differential amplifier 111, and the tenth electrode is connected to the output terminal 111c of the differential amplifier 111. Yes. In the fourth state, the ninth electrode in the fifth capacitor is disconnected from the first input terminal 111a of the differential amplifier 111, or the tenth electrode is disconnected from the output terminal 111c of the differential amplifier 111. Has been.

  Here, in the switching unit 114, the number of second switches to be switched to the third state in the first mode is smaller than the number of second switches to be switched to the third state in the second mode.

  For example, consider a case where the feedback capacitor 113 includes two fifth capacitors and the switching unit 114 includes two second switches. In the first mode, the switching unit 114 switches one fifth capacitor to the third state when one second switch is turned on. Accordingly, assuming that the capacitance value of the first input capacitor 112o, the capacitance value of the second input capacitor 112e, and the capacitance value of the fifth capacitor are C1, C1, and C3, respectively, the column amplifier 110 in the first mode The amplification factor of the signal is as follows.

AF = k1 × (C1) / (C3) Equation 5
In Equation 5, k1 is a proportionality constant.

  In the second mode, the switching unit 114 switches the two fifth capacitors to the third state by turning on the two second switches. Accordingly, assuming that the capacitance value of the first input capacitor 112o, the capacitance value of the second input capacitor 112e, and the capacitance value of the fifth capacitor are C1, C1, and C3, respectively, the column amplifier 110 in the second mode The amplification factor of the signal is as follows.

AF = k1 × (C1 + C1) / (2 × C3)
= K1 × (C1) / (C3) Equation 6
In Equation 6, k1 is the same proportionality constant as in Equation 5.

  Even with such a configuration, as shown in Equation 5 and Equation 6, the column amplifier 110 allows the signal amplification factor in the first mode to be equal to the signal amplification factor in the second mode. Amplify. Thereby, the S / N ratio of the signal in the first mode can be improved to the same level as the S / N ratio of the signal in the second mode. Therefore, the S / N ratio of the signal output from the pixel in both the first mode and the second mode can be improved.

  Further, although the imaging device can be provided on the same semiconductor substrate, the differential amplifier 111 is placed on a different substrate from other components in the imaging device so that noise generated by the differential amplifier 111 does not affect other circuit members. May be provided.

  In the second mode, an interlace operation is realized by alternately performing an operation of reading a signal from an odd row in the pixel array 107 and an operation of reading a signal from an even row in the pixel array 107 for each field period. May be.

  The configuration of the pixel is not limited to the MOS configuration, and may be the following configuration. VMIS (Threshold Voltage Modulation Image Sensor) may be used. It may be BCAST (Buried Charge Accumulator and Sensing Transistor array). It may be LBCAST (Lateral Buried Charge Accumulator and Sensing Transistor array). In particular, BCAST and LBCAST can be realized without substantial change by replacing the output unit (amplification transistor) with a JFET transistor. In addition, a sensor of a type that guides signal charges accumulated in the photoelectric conversion unit to a control electrode of a transistor provided in the pixel and outputs an amplified signal from the main electrode can be used for the pixel of this embodiment. For example, well-known examples include SIT and BASIS.

  Next, an example of an imaging system to which the imaging apparatus of the present invention is applied is shown in FIG. As shown in FIG. 6, the imaging system 90 mainly includes an optical system, an imaging device 86, and a signal processing unit. The optical system mainly includes a shutter 91, a lens 92, and a diaphragm 93. The signal processing unit mainly includes an imaging signal processing circuit 95, an A / D converter 96, an image signal processing unit 97, a memory unit 87, an external I / F unit 89, a timing generation unit 98, an overall control / calculation unit 99, and a recording. A medium 88 and a recording medium control I / F unit 94 are provided. The signal processing unit may not include the recording medium 88.

  The shutter 91 is provided in front of the lens 92 on the optical path, and controls exposure.

  The lens 92 refracts the incident light and forms an image of the subject on the pixel array (imaging surface) of the imaging device 86.

  The diaphragm 93 is provided between the lens 92 and the imaging device 86 on the optical path, and adjusts the amount of light guided to the imaging device 86 after passing through the lens 92.

  The imaging device 86 converts the image of the subject formed in the pixel array into an image signal. The imaging device 86 reads the image signal from the pixel array and outputs it.

  The imaging signal processing circuit 95 is connected to the imaging device 86 and processes the image signal output from the imaging device 86.

  The A / D converter 96 is connected to the imaging signal processing circuit 95 and converts the processed image signal (analog signal) output from the imaging signal processing circuit 95 into an image signal (digital signal).

  The image signal processing unit 97 is connected to the A / D converter 96, and performs various kinds of arithmetic processing such as correction on the image signal (digital signal) output from the A / D converter 96 to generate image data. To do. The image data is supplied to the memory unit 87, the external I / F unit 89, the overall control / calculation unit 99, the recording medium control I / F unit 94, and the like.

  The memory unit 87 is connected to the image signal processing unit 97 and stores the image data output from the image signal processing unit 97.

  The external I / F unit 89 is connected to the image signal processing unit 97. Thus, the image data output from the image signal processing unit 97 is transferred to an external device (such as a personal computer) via the external I / F unit 89.

  The timing generation unit 98 is connected to the imaging device 86, the imaging signal processing circuit 95, the A / D converter 96, and the image signal processing unit 97. Thereby, a timing signal is supplied to the imaging device 86, the imaging signal processing circuit 95, the A / D converter 96, and the image signal processing unit 97. The imaging device 86, the imaging signal processing circuit 95, the A / D converter 96, and the image signal processing unit 97 operate in synchronization with the timing signal.

  The overall control / arithmetic unit 99 is connected to the timing generation unit 98, the image signal processing unit 97, and the recording medium control I / F unit 94, and the timing generation unit 98, the image signal processing unit 97, and the recording medium control I / F. The unit 94 is controlled as a whole.

  The recording medium 88 is detachably connected to the recording medium control I / F unit 94. As a result, the image data output from the image signal processing unit 97 is recorded on the recording medium 88 via the recording medium control I / F unit 94.

  With the above configuration, if a good image signal is obtained in the imaging device 86, a good image (image data) can be obtained.

  Next, an imaging device 100i according to a second embodiment of the present invention will be described. Below, it demonstrates centering on a different part from 1st Embodiment.

  The imaging device 100i includes a plurality of column amplification units 110i. As shown in FIG. 7, the configuration of the column amplification unit 110i of each column is different from that of the first embodiment. FIG. 7 is a diagram illustrating a part of the configuration of the column amplification unit 110i in the second embodiment of the present invention. The column amplification unit 110i of each column includes a feedback capacitance unit 113i and a switching unit 114i.

  The feedback capacitor unit 113i further includes a feedback capacitor 113ci. The capacitance value of the feedback capacitor 113ci is smaller than the capacitance value of the feedback capacitor 113b. The capacitance value of the feedback capacitor 113ci is substantially equal to, for example, half the capacitance value of the feedback capacitor 113b. Further, the capacitance value of the feedback capacitor 113ci is smaller than the capacitance value of the feedback capacitor 113a. The capacitance value of the feedback capacitor 113ci is substantially equal to ¼ of the capacitance value of the feedback capacitor 113a, for example. The switching unit 114i further includes a switch 114ci. Thereby, many gain settings are possible.

  For example, the capacitance values of the first input capacitor 112o and the second input capacitor 112e are both 200 fF, and the capacitance values of the feedback capacitors 113a, 113b, and 113ci are 100 fF, 50 fF, and 25 fF, respectively.

Here, when the switch 114a is turned on and the switches 114b and 114ci are turned off, the gain of the column amplification unit 110i in the first mode is
AF = 200 fF / (100 fF)
= 2 Equation 7
It becomes. When the switch 114b is turned on and the switches 114a and 114ci are turned off, the gain of the column amplification unit 110i in the first mode is
AF = 200 fF / (50 fF)
= 4 Equation 8
It becomes. When the switch 114ci is turned on and the switches 114a and 114b are turned off, the gain of the column amplification unit 110i in the first mode is
AF = 200 fF / (25 fF)
= 8 Equation 9
It becomes. Although other gain settings are possible, in consideration of the user's usability, an integer multiple gain setting is appropriate for an imaging system such as a camera.

  Further, in order to make the gain in the first mode (interlaced operation mode) equal to the gain in the second mode (progressive operating mode), the capacitance value of the feedback capacitance unit has a relationship of a power of two. It is preferable to switch with a plurality of values.

  For example, the capacitance values of the first input capacitor 112o and the second input capacitor 112e are both C1, and the capacitance values of the feedback capacitors 113a, 113b, 113ci are C2, (C2 / 2), and (C4 / 4), respectively. .

Here, when the switch 114b is turned on and the switches 114a and 114ci are turned off in the first mode, the amplification factor (gain) of the signal of the column amplification unit 110i in the first mode is
AF = k × (C1) / (C2 / 2)
= 2k × (C1) / (C2) Equation 10
It becomes. Further, in the second mode, when the switch 114a is turned on and the switches 114b and 114ci are turned off, the amplification factor (gain) of the signal of the column amplification unit 110i in the second mode is
AF = k × (C1 + C1) / (C2)
= 2k × (C1) / (C2) Expression 11
Thereby, the amplification factors of the signals in the first mode and the second mode are both equal to “2k × (C1) / (C2)”.

Alternatively, when the switch 114ci is turned on and the switches 114a and 114b are turned off in the first mode, the amplification factor (gain) of the signal of the column amplification unit 110i in the first mode is
AF = k × (C1) / (C2 / 4)
= 4k × (C1) / (C2) Equation 12
It becomes. In the second mode, when the switch 114b is turned on and the switches 114a and 114ci are turned off, the amplification factor (gain) of the signal of the column amplification unit 110i in the second mode is
AF = k × (C1 + C1) / (C2 / 2)
= 4k × (C1) / (C2) Equation 13
Thereby, the amplification factors of the signals in the first mode and the second mode are both equal to “4k × (C1) / (C2)”.

  Thus, by providing a large number of gain settings, it becomes easy to switch the gain according to the shooting mode.

  For example, in a scene where the exposure needs to be increased, such as shooting at night, the signal amplification factors in the first mode and the second mode are both equal to “4k × (C1) / (C2)”. In a scene where exposure is low, such as shooting outdoors during the daytime, the signal amplification factors in the first mode and the second mode are both equal to “2k × (C1) / (C2)”. Thereby, an image with appropriate exposure according to the shooting mode can be obtained.

  Although the present invention has been described with reference to specific embodiments, the present invention can be modified as appropriate without departing from the scope of the invention. For example, the circuit of the column amplifier is not limited to the above embodiment. For example, when the amplification factor of the column amplification unit in the first mode and the amplification factor of the column amplification unit in the second mode are different from each other, any configuration may be used as long as they are close to each other.

90 Imaging System 100, 100i Imaging Device

Claims (13)

A plurality of units each including a photoelectric conversion unit, a charge voltage conversion unit, a transfer unit that transfers charges generated in the photoelectric conversion unit to the charge voltage conversion unit, and an output unit that outputs a signal corresponding to the voltage of the charge voltage conversion unit An image pickup apparatus comprising: a pixel array in which the pixels are arrayed two-dimensionally; and a plurality of column amplification units that amplify signals from the pixel array,
The column amplification unit includes an input capacitance unit and a feedback capacitance unit,
Each column of the pixel array includes a plurality of first pixels in which the output unit outputs a signal to the first signal line, and a plurality of second pixels in which the output unit outputs a signal to the second signal line. Including, and
The imaging device has a first shooting mode and a second shooting mode,
In each of the case where the imaging device is in the first imaging mode and the second imaging mode, the column amplification unit includes a capacitance value of the input capacitance unit and a capacitance value of the feedback capacitance unit. And amplifies the sum of the signal transmitted through the first signal line and the signal transmitted through the second signal line. A second amplifying the capacitance value of the feedback capacitance section in the first mode at a different timing between the signal transmitted via the first signal line and the signal transmitted via the second signal line; Smaller than the capacitance value of the feedback capacitor in the mode of
The column amplification unit, and a capacitance value of the feedback capacitance section in the first mode when the imaging device is in the first imaging mode, if the imaging device is in the second imaging mode An imaging apparatus characterized in that a capacitance value of the feedback capacitor in the second mode is made equal. In each of the case where the imaging device is in the first shooting mode and the second shooting mode, the column amplification unit sets the capacitance value of the input capacitance unit in the first mode to the capacitance value of the input capacitance unit. The capacitance value of the input capacitance section in the second mode is halved, and the capacitance value of the feedback capacitance section in the first mode is halved of the capacitance value of the feedback capacitance section in the second mode. The imaging apparatus according to claim 1. The column amplifying unit includes a differential amplifier having a first input terminal, a second input terminal to which a reference voltage is supplied, and an output terminal, and a capacitance value of the feedback capacitor unit in the first mode is A switching unit that switches the capacitance value of the feedback capacitance unit so as to be smaller than the capacitance value of the feedback capacitance unit in the second mode,
The imaging apparatus according to claim 1, wherein the feedback capacitor unit and the switching unit are arranged between the output terminal and the first input terminal of the differential amplifier. 4. The column amplifying unit switches a capacitance value of the feedback capacitor unit so that a signal amplification factor in the first mode is equal to a signal amplification factor in the second mode. The imaging device described in 1. The input capacitance unit is
A first input capacitor having at least a first electrode for receiving a signal transmitted via the first signal line and a second electrode connected to the first input terminal of the differential amplifier;
A second input capacitor having at least a third electrode for receiving a signal transmitted via the second signal line and a fourth electrode connected to the first input terminal of the differential amplifier;
In the first mode, the first electrode and the third electrode are turned off so as to be cut off, and in the second mode, the first electrode and the third electrode are connected to each other. The imaging device according to claim 3, further comprising: a first switch that performs the operation. The feedback capacitor unit includes a fifth electrode and a sixth electrode, the fifth electrode is disposed on the first input terminal side of the differential amplifier, and the sixth electrode is A third capacitor disposed on the output terminal side of the differential amplifier; a seventh electrode; and an eighth electrode, wherein the seventh electrode is the first input terminal of the differential amplifier. A fourth capacitor disposed on the output terminal side of the differential amplifier, and the eighth electrode disposed on the output terminal side of the differential amplifier,
In the first mode, the switching unit includes the seventh electrode of the fourth capacitor connected to the first input terminal of the differential amplifier, and the eighth electrode of the differential amplifier. The fifth electrode of the third capacitor connected to the output terminal is disconnected from the first input terminal of the differential amplifier, or the sixth electrode is disconnected from the output terminal of the differential amplifier. Switch to the first state, and in the second mode, the fifth electrode of the third capacitor is connected to the first input terminal of the differential amplifier, and the sixth electrode is the differential amplifier. The seventh electrode of the fourth capacitor connected to the output terminal of the differential amplifier is cut off from the first input terminal of the differential amplifier, or the eighth electrode is cut off from the output terminal of the differential amplifier. Second state Switching,
6. The imaging apparatus according to claim 3, wherein a capacitance value of the fourth capacitor is smaller than a capacitance value of the third capacitor. The feedback capacitance section includes a ninth electrode and a tenth electrode, respectively, and the ninth electrode is disposed on the first input terminal side of the differential amplifier, and the tenth electrode Includes a plurality of fifth capacitors respectively disposed on the output terminal side of the differential amplifier,
In the switching unit, the ninth electrode in the fifth capacitor is connected to the first input terminal of the differential amplifier, and the tenth electrode is connected to the output terminal of the differential amplifier. 3 and the ninth electrode in the fifth capacitor is disconnected from the first input terminal of the differential amplifier or the tenth electrode is disconnected from the output terminal of the differential amplifier Including a plurality of second switches for switching to any of the fourth states,
In the switching unit, the number of the second switches for switching to the third state in the first mode is smaller than the number of the second switches for switching to the third state in the second mode. The imaging apparatus according to claim 3, wherein the imaging apparatus is characterized. In each column of the pixel array, the first pixel and the second pixel are alternately arranged in a direction along the column,
The first mode is an interlaced operation mode;
The imaging apparatus according to claim 1, wherein the second mode is a progressive operation mode. In the first mode, in each column of the pixel array, a first operation in which a signal is transmitted from the first pixel to the column amplifier via the first signal line and the second pixel A second operation in which a signal is transmitted from the first signal line to the column amplifier via the second signal line is performed in parallel, and the first operation is performed in each column of the pixel array in the second mode. The imaging apparatus according to claim 1, further comprising: a drive unit that drives the pixel array so that the operation of the second and the second operation are performed at different timings. . The imaging device according to any one of claims 1 to 9,
An optical system for forming an image on the imaging surface of the imaging device;
A signal processing unit that processes the signal output from the imaging device to generate image data;
An imaging system comprising: A method for driving an imaging apparatus,
The imaging device includes a photoelectric conversion unit, a charge-voltage conversion unit, a transfer unit that transfers charges generated in the photoelectric conversion unit to the charge-voltage conversion unit, and an output that outputs a signal corresponding to the voltage of the charge-voltage conversion unit And a plurality of column amplification units that amplify signals from the pixel array, the column amplification unit including an input capacitance unit and a feedback capacitor And amplifying a signal according to a ratio of a capacitance value of the input capacitance unit and a capacitance value of the feedback capacitance unit, and each column of the pixel array has a signal to the first signal line by the output unit. A plurality of first pixels that respectively output; and a plurality of second pixels that each output a signal to the second signal line. The imaging device includes a first imaging mode and a second imaging mode. Shooting modes,
In the first mode, the driving method of the imaging apparatus is configured to connect the first signal line in each of the case where the imaging apparatus is in the first imaging mode and the second imaging mode. The signal transmitted through the second signal line and the signal transmitted through the second signal line are amplified. In the second mode, the signal transmitted through the first signal line and the first signal line are amplified. Amplify the signal transmitted via the two signal lines at different timings,
The capacitance value of the feedback capacitance unit in the first mode is smaller than the capacitance value of the feedback capacitance unit in the second mode,
And the capacitance value of the feedback capacitance section in the first mode when the imaging device is in the first imaging mode, the second mode when the imaging device is in the second imaging mode A driving method of an imaging apparatus, wherein the capacitance value of the feedback capacitor section is the same. An imaging apparatus comprising: a pixel array having a plurality of pixels that output signals according to incident light; and an amplifying unit that amplifies signals from the pixel array,
The amplification unit includes an input capacitance unit and a feedback capacitance unit,
The pixel array includes a first pixel that outputs a signal to a first signal line, and a second pixel that outputs a signal to a second signal line,
The imaging device has a first shooting mode and a second shooting mode,
In each of the case where the imaging device is in the first imaging mode and the second imaging mode, the amplifying unit calculates a capacitance value of the input capacitance unit and a capacitance value of the feedback capacitance unit. A first amplifier configured to amplify a signal according to a ratio and amplify a sum of a signal transmitted via the first signal line and a signal transmitted via the second signal line; A second value for amplifying the signal transmitted through the first signal line and the signal transmitted through the second signal line at different timings; Smaller than the capacitance value of the feedback capacitor in the mode,
The amplifying section, and the capacitance value of the feedback capacitance section in the first mode when the imaging device is in the first imaging mode, when the imaging device is in the second imaging mode An image pickup apparatus characterized in that a capacitance value of the feedback capacitor section in the second mode is made equal. A method for driving an imaging apparatus,
The imaging apparatus includes a pixel array having a plurality of pixels that output a signal corresponding to incident light, and an amplifier that amplifies a signal from the pixel array, and the amplifier includes an input capacitor and a feedback capacitor A first pixel that outputs a signal to a first signal line, and amplifies a signal according to a ratio of a capacitance value of the input capacitance unit and a capacitance value of the feedback capacitance unit; A second pixel that outputs a signal to a second signal line, and the imaging device has a first shooting mode and a second shooting mode;
In the first mode, the driving method of the imaging apparatus is configured to connect the first signal line in each of the case where the imaging apparatus is in the first imaging mode and the second imaging mode. The signal transmitted through the second signal line and the signal transmitted through the second signal line are amplified. In the second mode, the signal transmitted through the first signal line and the first signal line are amplified. Amplify the signal transmitted via the two signal lines at different timings,
The capacitance value of the feedback capacitance unit in the first mode is smaller than the capacitance value of the feedback capacitance unit in the second mode,
And the capacitance value of the feedback capacitance section in the first mode when the imaging device is in the first imaging mode, the second mode when the imaging device is in the second imaging mode A driving method of an imaging apparatus, wherein the capacitance value of the feedback capacitor section is the same.

Images