JP5407182B2 - High voltage vertical MOSFET - Google Patents

Description

  The present invention relates to a semiconductor device called a planar type high voltage MOS field effect transistor (hereinafter referred to as MOSFET).

The high breakdown voltage vertical MOSFET is generally connected to the high potential side of a circuit that operates at a frequency of about 10 kHz to 1 MHz in a power conversion circuit such as a switching power supply device, an inverter device, or a motor control device. FIG. 6 is a perspective sectional view of such a general high breakdown voltage vertical MOSFET. This high breakdown voltage vertical MOSFET is shown above from a low concentration n ⁻ drift layer 1 epitaxially formed on a semiconductor substrate which is a high concentration drain layer (not shown). In the surface layer of the n ⁻ drift layer 1, a p ⁻ base region 2 and n ⁺ source regions 3 formed in parallel on the surface layer of the p ⁻ base region 2 along the long side are formed. It is. A surface along the long side of the p ⁻ base region 2 sandwiched between the surface of the n ⁺ source region 3 and the surface of the n ⁻ drift layer 1 becomes a channel 4. The channel mentioned here is a region of the inversion layer formed on the surface of the p ⁻ base region 2 when a gate voltage higher than a threshold is applied to the gate electrode. A gate electrode (conductive Poly-Si) 6 is formed on the surface of the channel 4 via a gate oxide film (SiO ₂ film) 5. The source electrode (Al—Si) 8 is in common contact with the surface of the p ⁻ base region 2 and the surface of the n ⁺ source region 3 (source electrode contact region 9 in the frame of the one-dot chain line in FIG. 6), and the gate electrode 6 The upper layer is covered with an interlayer insulating film (PSG) 7. Further, in FIG. 6, in order to clearly show the surface pattern hidden under the gate oxide film 5, the gate electrode 6, and the source electrode 8, the parts 5, 6, and 7 are partially removed.

High-voltage vertical MOSFET shown in FIG. 6, the in order to improve the on-resistance performance and switching performance, p 6 ^- width Lp + p of the short side of the base region 2 ^- consisting distance Ln between the base region cell pitch Is made as small as possible to increase the channel density. It is also effective to design the p ^- base region 2 so as to be arranged in a dense pattern parallel to the active region surface layer through which the main current flows on the substrate surface. Further, the pn main junction between the p ⁻ base region 2 and the drift layer 1 is brought close to the planar junction so that a generated breakdown voltage close to the planar junction can be obtained to ensure a high breakdown voltage. Further, the interval Ln between the p ⁻ base regions 2 is narrowed to reduce the feedback capacitance Crss generated in the insulating film between the gate electrode 6 and the surface of the n ⁻ drift layer 1, thereby improving the switching performance. However, if the distance Ln between the p ^- base regions is too narrow to deplete due to the JFET effect, for example, if Ln is 1.5 μm or less, the on-resistance gradually increases. Is well known.
As described above, in order to improve the on-resistance performance and the switching performance, the high breakdown voltage vertical MOSFET has a p ^- base region densely arranged in a plane, resulting in an increase in channel density and an increase in gain characteristic Gm. ^- the spacing Ln of the base region is short, the feedback capacitance Crss is reduced.

を用いて説明すると以下のように言える。トランジョン周波数

は一般的に、

In this regard, the transition frequency of the high breakdown voltage vertical MOSFET

It can be said as follows if it explains using. Transition frequency

Is generally

は高くなる。
一方、前述のような高耐圧縦型ＭＯＳＦＥＴについての公知技術について、ｐ⁻ベース領域を前述のように稠密に平面配置にして、耐圧とオン抵抗とのトレードオフ関係を改善し、高耐圧、低オン抵抗でしかも高速スイッチングを可能にする技術については、既に公開されている（特許文献１、２）。
また、ＩＧＢＴをマルチエミッタショート構造にすることにより、ＩＧＢＴのラッチアップ電流を高くすることについての技術報告がされている（非特許文献１）。
特開２００２−３６８２１５号公報 特開２００３−８０１４号公報 Ｈ．ＹＩＬＭＡＺ，ＩＥＥＥ ＥＬＥＣＴＲＯＮ ＤＥＶＩＣＥ ＬＥＴＴＥＲＳ，ＶＯＬ．ＮＯ．８ ＡＵＧＵＳＴ １９８５ 「ＣＥＬＬ ＧＥＯＭＥＴＲＹ ＥＦＦＥＣＴ ＯＮ ＩＧＴ ＬＡＴＣＨ−ＵＰ」（ＦＩＧ２（ｄ）） Can be expressed as When the p ^- base region 2 is densely arranged in the plane as described above, that is, Gm increases and Crss decreases, from Equation 1, the transition frequency of the high voltage vertical MOSFET

Becomes higher.
On the other hand, with respect to the publicly known technology for the high breakdown voltage vertical MOSFET as described above, the p ^- base region is densely arranged in the plane as described above to improve the trade-off relationship between breakdown voltage and on-resistance. A technique that enables on-resistance and high-speed switching has already been disclosed (Patent Documents 1 and 2).
In addition, there has been a technical report about increasing the latch-up current of the IGBT by making the IGBT a multi-emitter short structure (Non-Patent Document 1).
JP 2002-368215 A JP 2003-8014 A H. YILMAZ, IEEE ELECTRON DEVICE LETTERS, VOL. NO. 8 AUGUST 1985 "CELL GEOMETRY EFFECT ON IGT LATCH-UP" (FIG2 (d))

が極端に高くなるので、一般的な電力変換回路に適用した場合、スイッチング動作過程における波形リンギングの増大、発振現象によるデバイス破壊などの異常動作がおき易くなるという問題が生じる。
本発明の目的は、オン抵抗性能とスイッチング性能を改善するために、高耐圧の縦型ＭＯＳＦＥＴのチャネル密度を高くした場合でも、これら性能を低下させずに、所要のゲイン特性が得られ、波形リンギングや発振現象などの異常動作の発生を抑制することができ、さらに寄生トランジスタの動作を抑制してアバランシェ耐量を向上させ、デバイス破壊の起き難い高耐圧縦型ＭＯＳＦＥＴを提供することにある。 However, in the high breakdown voltage vertical MOSFET as described above, when the channel density is increased, the transition frequency is increased.

Therefore, when it is applied to a general power conversion circuit, there arises a problem that abnormal operation such as increased waveform ringing in the switching operation process and device destruction due to oscillation phenomenon easily occurs.
The object of the present invention is to improve the on-resistance performance and switching performance, even when the channel density of a high breakdown voltage vertical MOSFET is increased, the required gain characteristics can be obtained without reducing these performances, and the waveform An object of the present invention is to provide a high-breakdown-voltage vertical MOSFET that can suppress the occurrence of abnormal operation such as ringing and oscillation phenomenon, further suppresses the operation of a parasitic transistor, improves the avalanche resistance, and hardly causes device breakdown.

According to the invention described in the appended claims, and the drift layer of the semiconductor substrate is lightly doped with a first conductivity type, the second conductive stripes which are parallel to plurality at predetermined intervals on the main surface of the drift layer A mold base region and a high impurity concentration first conductivity type source region disposed along the long side of the surface layer in the base region, and sandwiched between the drift layer surface and the source region surface The base region has a channel on the surface along the long side, the gate surface is provided with a gate electrode on the surface of the channel, respectively, and the surface portion of the base region excluding the channel and the base region In the high breakdown voltage vertical MOSFET having a main electrode in common contact so as to short-circuit the base region and the source region on the surface of the source region, the source region is the channel Min to contact channels throughout are in a pattern not in contact, wherein the short side width Lp of the base region is the sum of the width Ln of the base region spacing cell pitch (Lp + Ln) is 20μm or less, based on the Ln ≦ 7 [mu] m , Ln / Lp> 1 / 3.5, a portion of the surface pattern of the source region that is parallel to the long side of the base region, and a pattern bent portion that connects the parallel portions to each other The high-breakdown-voltage vertical MOSFET having a stripe shape having a vertical axis and in contact with the channel along the long side at a portion parallel to the channel .

Before Symbol bent portion may be I right angle der.
Before Symbol bent portion may be I right angle greater than the angle der.
A semiconductor substrate having a first conductivity type and a low impurity concentration drift layer, a plurality of stripe-shaped second conductivity type base regions provided in parallel to the main surface of the drift layer at predetermined intervals, and a surface in the base region A high impurity concentration first conductivity type source region disposed along the long side of the layer, the resistance component ratio of the drift layer to the entire on-resistance being 50% or more, and the drift layer surface and the source The channel has a channel along the long side of the base region sandwiched between the region surfaces, the resistance component ratio of the channel is 20%, and a gate insulating film is formed on the surface of the channel via a gate insulating film. A main electrode that has an electrode and is in common contact with the surface portion of the base region excluding the channel and the surface of the source region so as to short-circuit the base region and the source region; In the high breakdown voltage vertical MOSFET having the above structure, the source region has a pattern which is partially in contact with the channel and not in the entire channel, and is the sum of the short side width Lp of the base region and the width Ln of the base region interval. The cell pitch (Lp + Ln) is 20 μm or less, Ln ≦ 7 μm is used as a reference, and Ln / Lp> 1 / 3.5 is satisfied, and the surface pattern of the source region is parallel to the long side of the base region a a pattern, so as to contact alternately to each of the channels along the long side at regular intervals, high that having a respective pattern is moved on the long side alternating source regions of constant spacing A breakdown voltage vertical MOSFET is used .
A semiconductor substrate having a first conductivity type and a low impurity concentration drift layer, a plurality of stripe-shaped second conductivity type base regions provided in parallel to the main surface of the drift layer at predetermined intervals, and a surface in the base region A high impurity concentration first conductivity type source region disposed along the long side of the layer, the resistance component ratio of the drift layer to the entire on-resistance being 50% or more, and the drift layer surface and the source A channel is formed on the surface along the long side of the base region sandwiched between the surface of the regions, and the resistance component ratio of the channel is 20% or less, and a gate insulating film is interposed on the surface of the channel, respectively. A gate electrode is provided, and the surface portion of the base region excluding the channel and the surface of the source region are in common contact with each other so as to short-circuit the base region and the source region. In the high voltage vertical MOSFET having electrodes,
The source region has a pattern that is partially in contact with the channel and not in the entire channel, and the distance Ls−b between the channel and the source region is not in contact with the long side direction of the base region. The high breakdown voltage vertical MOSFET is longer than the distance Ls-a between the region where the channel and the source region are in contact.
Further, the relationship that the cell pitch (Lp + Ln), which is the sum of the short side width Lp of the base region and the width Ln of the base region interval, is 20 μm or less and satisfies Ln / Lp> 1 / 3.5 on the basis of Ln ≦ 7 μm. You may have.
The surface pattern of the source region has a discontinuous parallel pattern in which two stripe shapes each parallel to two long sides of the base region are alternately spaced at regular intervals, and the channel is You may contact | connect in the said discontinuous parallel pattern part.
The surface pattern of the source region has a portion that is parallel to the long side of the base region, and a connecting portion that connects the parallel portions to each other, and the source region includes the channel along the long side. , And may be in contact with a portion parallel to the channel.
The connecting portion may have a bent portion that is bent from a portion parallel to the long side of the base region.
The bent portion may be a right angle.
The bent portion may have an angle larger than a right angle.
The source region having a constant interval is formed so that the surface pattern of the source region is a pattern parallel to the long side of the base region, and alternately touches the channel along the long side at a constant interval. You may have the pattern moved to each long side alternately.
The distance Ls-b may be 10 times or more the channel distance Lch in the direction in which the current flows.

In order to solve the above problem, the present invention is in contact with a part of the channel of the high breakdown voltage vertical MOSFET in order to reduce the effective channel density while controlling the increase in the on-resistance and the increase in the feedback capacitance, A high breakdown voltage vertical MOSFET having a surface pattern shape of the source region not in contact with all sides is formed. Specifically, when forming the source region, masking is partially performed to form a portion where the source region is not formed. In the formation of the source region, the portion forming the source region, that is, the distance Ls-a in the long side direction of each n ⁺ source region and the portion without the source diffusion layer, that is, between each cut n ⁺ source region By setting the distance Ls−b in the long side direction to a predetermined ratio, the channel width can be changed regardless of the cell pitch (Lp + Ln). Thereby, a required gain characteristic Gm can be realized. Also, by making Ls-b larger than Ls-a, the contact area of the base region with the source electrode (Al-Si) is increased, and the avalanche current flowing into the parasitic bipolar transistor during the avalanche breakdown operation is reduced. Thus, the avalanche resistance is improved.

  According to the present invention, in order to improve the on-resistance performance and the switching performance, even when the channel density of the high breakdown voltage vertical MOSFET is increased, the required gain characteristics can be obtained without reducing these performances, and the waveform The occurrence of abnormal operations such as ringing and oscillation phenomenon can be suppressed, and further, the operation of the parasitic transistor can be suppressed to improve the avalanche resistance, thereby providing a high breakdown voltage vertical MOSFET that is unlikely to cause device breakdown.

Hereinafter, an embodiment according to a high breakdown voltage vertical MOSFET of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the description of the examples described below unless it exceeds the gist.
1 to 5 are perspective sectional views showing surface patterns of different source regions according to the n-channel high breakdown voltage vertical MOSFET of the present invention.
[Example 1]

1 is a perspective sectional view of an n-channel high breakdown voltage vertical MOSFET according to Embodiment 1. FIG. As in FIG. 6, the drain layer is also omitted in FIG. The difference from FIG. 6 is the surface pattern portion of the n ⁺ source region 3a. In FIG. 6, the surface pattern of the n ⁺ source region 3 is formed in a continuous stripe shape in parallel with each other along the long side on the surface layer of the p ⁻ base region 2. As shown in FIG. 1, two stripes are intermittently formed at regular intervals, and the two stripes are cut out so as to alternate with each other. The distance in the long side direction of each remaining n ⁺ source region 3a is Ls-a, and the distance in the long side direction between the individual n ⁺ source regions 3a is Ls-b. Further, in the first embodiment, the remaining individual n ⁺ source regions 3a and the cut regions between the n ⁺ source regions 3a are alternately arranged with respect to the two stripes as described above. It is characterized by having a surface pattern. By adopting such a surface pattern of the n ⁺ source region 3a, if the width of the effective channel through which the current flows (distance in the direction perpendicular to the direction of current flow) is appropriately changed while the cell pitch (Ln + Lp) is kept small, The total channel width per chip can be controlled, and the gain characteristics can be controlled.
In the first embodiment, such a surface pattern of the non-continuous n ⁺ source region 3a provides a gain compared to the conventional continuous striped n ⁺ source region 3 having no cut region without changing the cell pitch. it is possible to reduce the Gm, Trang John frequency f _T of the aforementioned low, it is possible to suppress the occurrence of abnormal operation such as waveform ringing or oscillation phenomenon.

On the other hand, there is a concern about an increase in on-resistance as the gain Gm decreases. However, the high breakdown voltage MOSFET according to the present invention is premised on that the resistance component of the drift layer 1 occupying the on-resistance is as large as 50% or more and the resistance component of the channel is as small as 20% or less. Therefore, by appropriately controlling the surface pattern of the n ⁺ source region, even if the resistance component of the channel portion slightly increases, there is no practical problem in increasing the resistance component of the channel portion in terms of the overall on-resistance. It can be suppressed sufficiently.
The concept for designing the shape of the surface pattern of the n ⁺ source region according to the high breakdown voltage vertical MOSFET of the present invention including Example 1 will be described.
In order to improve the on-resistance performance and switching performance of the high breakdown voltage vertical MOSFET of the present invention, the cell pitch (Lp + Ln) comprising the width Lp of the short side of the p ⁻ base region 2 and the interval Ln between the p ⁻ base regions is The channel density can be increased by making the interval as small as possible the increase in the on-resistance due to the JFET effect as small as possible. For example, in the range where the cell pitch (Lp + Ln) is 20 μm or less, the ratio Ln to Lp, Ln / Lp is larger than 1 / 3.5, with the distance Ln between the p ^- base regions being 7 μm or less. That is, it is preferable to determine the width Lp of the short side of the p ⁻ base region 2 that satisfies Ln / Lp> 1 / 3.5.

For example, if the interval Ln between the p ⁻ base regions is 7 μm, if 7 μm is subtracted from the cell pitch 20 μm, the remaining 13 μm is obtained, so the width Lp of the short side of the p ⁻ base region 2 is 13 μm or less. Accordingly, Lp ≦ 13 μm and Lp value, for example, Lp, in consideration of the area necessary for the source contact region and the photolithography ability to form the n ⁺ source region in a range satisfying Ln / Lp> 1 / 3.5. = 10 μm may be determined.
Further, regarding the pattern in which the surface pattern of the source region is partially in contact with the channel surface and not in the entire region, in Example 1 shown in FIG. 1, the distance Ls− in the longitudinal direction of the region where the channel and the source region do not contact b is not less than 10 times the channel length Lch, which is the distance of the channel in the direction of current flow, that is, Ls−b> 10 × Lch, and Ls−b is greater than Ls−a, that is, Ls It is preferable that -b / Ls-a> 1. In the case 10 times or less than Ls-b is Ls-a smaller, less impact on the reduction of the gain Gm, because the effect of reducing Trang John frequency f _T is small invention is not large.
Further, by setting Ls−b / Ls−a> 1, the surface area of the p ⁻ base region 2 is increased, and the contact area of the p ⁻ base region 2 with respect to the source electrode can be increased. As a result, the current flowing into the p ⁻ base region of the parasitic bipolar transistor (n ⁻ drift layer 1 −p ⁻ base region 2 −n ⁺ source region 3 a) at the time of avalanche breakdown can be reduced, and the transistor operation can be suppressed. Avalanche resistance can be improved and device destruction can be reduced.
[Example 2]

FIG. 2 is a perspective sectional view of an n-channel high breakdown voltage vertical MOSFET according to the second embodiment. FIG. 2 shows an n ⁺ source region surface pattern different from that in FIG. In Figure 2, as shown in FIG. 1, n ⁺ source region 3a becomes discontinuous pattern, on the area of the n ⁺ source region 3a becomes smaller than the conventional Figure 6n ⁺ source region 3, further individual There is a concern that the contact area with the source electrode 8 may decrease due to a photo process trouble such as pattern shift or resist peeling due to the decrease of the n ⁺ source region 3a. FIG. 2 is characterized by an n ⁺ source region 3b pattern that is a countermeasure against this concern. In order to deal with the concern, the n ⁺ source region 3b is formed into a non-continuous rectangular pattern that is intermittently cut at regular intervals as shown in FIG. That is, by providing an additional convex portion in the rectangular short side direction of the n ⁺ source region 3a in FIG. 1, there is no pattern in the longitudinal direction of the non-continuous n ⁺ source region 3a as described in FIG. It is characterized in that the interval between the portions is left as it is, and the pattern prevents the decrease of the n ⁺ source region 3a due to the photo process trouble. With such a pattern, the distance along the long side of the source region in contact with one channel is Ls-a, and the distance not in contact with this one channel (in contact with the other channel) is Ls-b. The relationship between Ls-a and Ls-b is the same as in the first embodiment.

In the second embodiment, such a surface pattern of the non-continuous n ⁺ source region 3b provides a gain compared to the conventional continuous stripe n ⁺ source region 3 having no cut-out region without changing the cell pitch. it is possible to reduce the Gm, Trang John frequency f _T of the aforementioned low, it is possible to suppress the occurrence of abnormal operation such as waveform ringing or oscillation phenomenon.
Moreover, since the transistor operation can be suppressed as in the first embodiment, the avalanche resistance can be improved and the device breakdown can be reduced.
[Examples 3 and 4]

3 and 4 are perspective sectional views of n-channel high voltage vertical MOSFETs according to Examples 3 and 4, respectively. 3 and 4 show surface patterns of n ⁺ source regions 3c and 3d different from those in FIGS. 3 and 4, two stripe patterns are formed so that the surface pattern in which the two non-continuous n ⁺ source regions 3a shown in FIG. 1 are alternately arranged becomes one stripe pattern. It is a pattern connected at non-continuous parts. FIG. 3 is a discontinuous portion of the source pattern of FIG. 1 and is a pattern connected in a region bent in a direction perpendicular to the stripe, and FIG. 4 is also a region bent at an angle larger than the right angle. It is a pattern connected alternately. With such a pattern, the distance along the long side of the source regions 3c and 3d that are in contact with one channel is Ls-a, and the distance that is not in contact with this one channel (is in contact with the other channel) is Ls-b. And The relationship between Ls-a and Ls-b is the same as in the first embodiment.
In the third and fourth embodiments, such a surface pattern of the n ⁺ source regions 3c and 3d makes it possible to obtain a gain Gm as compared with the n ⁺ source region 3 that is in contact with the entire area of the conventional channel without changing the cell pitch. it is possible to reduce, Trang John frequency f _T of the aforementioned low, it is possible to suppress the occurrence of abnormal operation such as waveform ringing or oscillation phenomenon.

In the third and fourth embodiments, the areas of the source regions 3c and 3d are continuous as compared with the source region 3a of the first embodiment. The feature is that the photo process trouble due to the small is reduced.
Further, since the transistor operation can be suppressed for the same reason as in the first embodiment, the avalanche resistance can be improved, and the device breakdown can be reduced.
Example 5

FIG. 5 is a perspective sectional view of an n-channel high breakdown voltage vertical MOSFET according to the fifth embodiment. FIG. 5 shows a surface pattern of the n ⁺ source region 3e different from those in FIGS. In FIG. 5, a single source region formed parallel to the long side of the base region 2 is moved at a fixed distance to at least one long side by a distance that does not separate the source region. It is characterized in that it is a surface pattern that is alternately in contact with the channels formed along the surface. By adopting such a pattern, the distance along the long side of the source region 3e in contact with one channel is Ls-a, and the distance not in contact with this one channel (in contact with the other channel) is Ls-b. . The relationship between Ls-a and Ls-b is the same as in the first embodiment.
Also in the fifth embodiment, by using such a surface pattern of the n ⁺ source region 3e, the gain Gm can be reduced as compared with the n ⁺ source region 3 that is in contact with the entire area of the conventional channel without changing the cell pitch. since it is, Trang John frequency f _T of the aforementioned low, it is possible to suppress the occurrence of abnormal operation such as waveform ringing or oscillation phenomenon.
Further, in the fifth embodiment, since the area of the source region 3e is larger than that of the source region 3a of the first embodiment, the photo process trouble due to the small area of the individual source regions 3a, which is a problem in the first embodiment. There is a feature that decreases. Further, since the transistor operation can be suppressed for the same reason as in the first embodiment, the avalanche resistance can be improved, and the device breakdown can be reduced.

  Further, in Examples 2 to 5, since there is a wider portion in the short side direction than the source region 3a of Example 1, contact between the source electrode and each source region is made even if there is a manufacturing deviation in the mask pattern. It can be done reliably.

It is a perspective sectional view showing the source region concerning n channel high breakdown voltage vertical MOSFET of the present invention. It is a perspective sectional view showing a different source region concerning the n-channel high breakdown voltage vertical MOSFET of the present invention. It is a perspective sectional view showing a different source region concerning the n-channel high breakdown voltage vertical MOSFET of the present invention. It is a perspective sectional view showing a different source region concerning the n-channel high breakdown voltage vertical MOSFET of the present invention. It is a perspective sectional view showing a different source region concerning the n-channel high breakdown voltage vertical MOSFET of the present invention. It is a perspective sectional view of a conventional n-channel high breakdown voltage vertical MOSFET.

Explanation of symbols

1 drift layer, n ⁻ drift layer 2 base region, p ⁻ base region 3, 3a, 3b, 3c, 3d, 3e source region, n ⁺ source region 4 channel 5 gate oxide film, SiO ₂ film 6 gate electrode, conductivity Poly-Si
7 Interlayer insulation film, PSG
8 Source electrode, Al-Si
9 Source electrode contact region 9
Lch channel length Lp short side width of base region Ln spacing between base regions Ls-a distance in the long side direction of individual n ⁺ source region Ls-b distance in long side direction of individual cut n ⁺ source region .

Claims (13)

A semiconductor substrate having a first conductivity type and a low impurity concentration drift layer, a plurality of stripe-shaped second conductivity type base regions provided in parallel to the main surface of the drift layer at predetermined intervals, and a surface in the base region A high impurity concentration first conductivity type source region disposed along the long side of the layer, the resistance component ratio of the drift layer to the entire on-resistance being 50% or more, and the drift layer surface and the source The channel has a channel along the long side of the base region sandwiched between the region surfaces, the resistance component ratio of the channel is 20%, and a gate insulating film is formed on the surface of the channel via a gate insulating film. A main electrode that has an electrode and is in common contact with the surface portion of the base region excluding the channel and the surface of the source region so as to short-circuit the base region and the source region; In the high voltage vertical MOSFET having,
The source region is in a pattern that is partially in contact with the channel and not in the entire channel ,
The cell pitch (Lp + Ln), which is the sum of the short side width Lp of the base region and the width Ln of the base region interval, is 20 μm or less, and satisfies a relationship satisfying Ln / Lp> 1 / 3.5 based on Ln ≦ 7 μm. And
The surface pattern of the source region has a stripe shape having a portion parallel to the long side of the base region, and a pattern bending portion connecting the parallel portions to each other, and the channel along the long side Is a high breakdown voltage vertical MOSFET, which is in contact with a portion parallel to the channel . 2. The high breakdown voltage vertical MOSFET according to claim 1, wherein the bent portion is a right angle . 2. The high breakdown voltage vertical MOSFET according to claim 1, wherein the bent portion has an angle larger than a right angle . A semiconductor substrate having a first conductivity type and a low impurity concentration drift layer, a plurality of stripe-shaped second conductivity type base regions provided in parallel to the main surface of the drift layer at predetermined intervals, and a surface in the base region A high impurity concentration first conductivity type source region disposed along the long side of the layer, the resistance component ratio of the drift layer to the entire on-resistance being 50% or more, and the drift layer surface and the source The channel has a channel along the long side of the base region sandwiched between the region surfaces, the resistance component ratio of the channel is 20%, and a gate insulating film is formed on the surface of the channel via a gate insulating film. A main electrode that has an electrode and is in common contact with the surface portion of the base region excluding the channel and the surface of the source region so as to short-circuit the base region and the source region; In the high voltage vertical MOSFET having,
The source region is in a pattern that is partially in contact with the channel and not in the entire channel,
The cell pitch (Lp + Ln), which is the sum of the short side width Lp of the base region and the width Ln of the base region interval, is 20 μm or less, and satisfies a relationship satisfying Ln / Lp> 1 / 3.5 based on Ln ≦ 7 μm. And
The source region having a constant interval is formed so that the surface pattern of the source region is a pattern parallel to the long side of the base region, and alternately touches the channel along the long side at a constant interval. A high breakdown voltage vertical MOSFET having a pattern that is alternately moved to the long side . A semiconductor substrate having a first conductivity type and a low impurity concentration drift layer;
A plurality of stripe-shaped second conductivity type base regions provided in parallel at predetermined intervals on the main surface of the drift layer;
A high impurity concentration first conductivity type source region disposed along the long side of the surface layer in the base region,
The resistance component ratio of the drift layer to the entire on-resistance is 50% or more,
Having a channel on the surface along the long side of the base region sandwiched between the drift layer surface and the source region surface;
The resistance component ratio of the channel is 20% or less,
On the surface of the channel, each has a gate electrode through a gate insulating film,
Further, in the high breakdown voltage vertical MOSFET having a main electrode that is in common contact with the surface portion of the base region excluding the channel and the source region surface so as to short-circuit the base region and the source region,
The source region is in a pattern that is partially in contact with the channel and not in the entire channel,
A distance Ls-b of a region where the channel and the source region are not in contact with each other along a long side direction of the base region is longer than a distance Ls-a of a region where the channel and the source region are in contact with each other. the high-voltage vertical MOSFET to be. The cell pitch (Lp + Ln), which is the sum of the short side width Lp of the base region and the width Ln of the base region interval, has a relationship satisfying Ln / Lp> 1 / 3.5 with reference to 20 μm or less and Ln ≦ 7 μm. The high breakdown voltage vertical MOSFET according to claim 5 . The surface pattern of the source region has a discontinuous parallel pattern in which two stripe shapes each parallel to two long sides of the base region are alternately spaced at regular intervals, and the channel is The high breakdown voltage vertical MOSFET according to claim 6, wherein the high-voltage vertical MOSFET contacts with the discontinuous parallel pattern portion . The surface pattern of the source region has a portion that is parallel to the long side of the base region, and a connecting portion that connects the parallel portions to each other,
The high breakdown voltage vertical MOSFET according to claim 6, wherein the source region is in contact with the channel along the long side at a portion parallel to the channel. 9. The high breakdown voltage vertical MOSFET according to claim 8, wherein the connection portion has a bent portion bent from a portion parallel to the long side of the base region. The high breakdown voltage vertical MOSFET according to claim 9, wherein the bent portion is a right angle. The high breakdown voltage vertical MOSFET according to claim 9, wherein the bent portion has an angle larger than a right angle. The source region having a constant interval is formed so that the surface pattern of the source region is a pattern parallel to the long side of the base region, and alternately touches the channel along the long side at a constant interval. 7. The high breakdown voltage vertical MOSFET according to claim 6, wherein the high withstand voltage vertical MOSFET has a pattern which is alternately moved to each long side. The high withstand voltage vertical MOSFET according to any one of claims 5 to 12, wherein the distance Ls-b is 10 times or more the distance Lch of the channel in the direction in which a current flows.

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