JP5407630B2 - D / A converter and operation test method thereof - Google Patents

Description

  The present invention relates to a technique for confirming the operation of a D / A converter.

  A conventional D / A (Digital / Analog) converter test method uses a high-precision voltmeter connected to the output of a D / A converter, and a predetermined voltage is applied to all combinations of digital code signals. It was to confirm that it was output.

  However, in the above method, since the time until the output voltage of the D / A converter reaches a predetermined voltage (hereinafter referred to as settling time) is long, the test time is long and the production efficiency is deteriorated. It was. Furthermore, as the number of bits of the D / A converter increases, this tendency becomes more prominent and has become a problem.

  Therefore, various techniques for reducing the test time of the D / A converter have been proposed. For example, one of the configurations is provided with two systems of Ach and Bch as a switch group for taking out one divided voltage by switch means for turning on / off a divided voltage by a resistor connected in series according to a digital code signal. (Patent Document 1). Here, the test of the Bch switch means is turned on together with any one of the Bch switch means SiB (i is an integer), the Ach switch means S (i−1) A, or S (i + 1) A. PASS / FAIL is determined based on the measurement result by the comparator regarding the magnitude relationship of the output voltage of each channel. Similarly, the test of the Ach switch means is performed by turning on the Ach switch means SiA together with any one of the Bch switch means S (i−1) B or S (i + 1) B, The quality is judged based on the measurement result by the comparator regarding the magnitude relation of the output voltage. These tests are repeated, and the test time is shortened only by the switch means test.

  On the other hand, the reference voltage is divided by a resistor connected in series, and one of the divided voltages is output via a plurality of switch means that are turned on / off according to a digital code signal. A converter has been proposed (Patent Document 2). The D / A converter includes a test mode switching signal input terminal for inputting a test mode switching signal for switching between a normal operation mode and a test mode, and a connection between the reference voltage and the series-connected resistor in the test mode. A test signal input terminal for inputting a test signal, and a test signal for directly outputting an output signal output via the switch means Since it has an output terminal, the voltage applied to the test signal input terminal can be observed from the test signal output terminal via any switch means by setting the digital code signal, and the test of the switch means becomes easy. .

  However, the above-described technique requires a two-channel D / A output of Ach and Bch, and is not applicable to a 1ch D / A converter. In addition, the above-described technique can test the resistance and the switch itself, but there is a problem that observation including a signal for controlling on / off of the switch is difficult.

  In view of the above problems, the present invention provides a D / A converter that does not require a high-precision voltmeter and can reduce test time even with a 1ch D / A converter, and an operation test method thereof. The purpose is to do.

One form of the disclosed D / A converter is a D / A converter that D / A converts an input digital code signal and outputs the digital code signal, and the input voltage is divided into a plurality of voltage dividing ratios by a plurality of resistors connected in series. And a D / A conversion circuit unit that outputs one of the divided voltages as an analog signal via a plurality of switches that are controlled to be turned on / off according to the digital code signal. The / A conversion circuit unit outputs the analog signal corresponding to the first test signal and the first test signal when the first test signal is input as the input voltage. The holding means holds on / off control states of the plurality of switches according to the digital code signal at the time, and the second number of pulse signals corresponds to the number of bits of the digital code signal. When the strike signal is input, said holding means in response to the second test signal by performing a bit shift, and outputs the state of the ON / OFF control of the plurality of switches.

Moreover, one form of the disclosed D / A converter has a plurality of the holding means .

Moreover, one form of the disclosed D / A converter is characterized in that the D / A conversion circuit section includes an off control unit that performs off control of all of the plurality of switches .

On the other hand, according to one mode of the disclosed D / A converter operation test method, a first test signal is input as the input voltage to the D / A converter circuit unit, and the first test signal is input from the D / A converter circuit unit. Determining whether or not the analog signal corresponding to the test signal is output; inputting the second test signal; and outputting the digital code signal and a desired digital code output from the D / A conversion circuit unit Determining whether or not the signals match .

  The disclosed D / A converter does not require a high-accuracy voltmeter, and the test time can be shortened even with a 1ch D / A converter.

It is a block diagram of the D / A converter concerning this embodiment. FIG. 3 is an internal circuit diagram of a reference voltage generation circuit according to the present embodiment. It is an internal circuit diagram of the D / A conversion circuit according to the present embodiment. It is an internal circuit diagram of the latch circuit according to the present embodiment. It is a timing chart which shows the waveform of the signal applied to the 1st test signal input terminal concerning this embodiment, and the waveform of the signal outputted from the 1st test signal output terminal. It is a timing chart which shows the waveform of the signal impressed to the 2nd test signal input terminal concerning this embodiment, and the waveform of the signal outputted from the 2nd test signal output terminal.

  The best mode for carrying out the present invention will be described with reference to the drawings. An outline of a D / A (Digital / Analog) converter 1 according to the present embodiment will be described with reference to FIG. Here, FIG. 1 is a block diagram of the D / A converter 1.

As shown in FIG. 1, the D / A converter 1 includes a D / A conversion circuit 10, a reference voltage generation circuit 20, a first switch means M1, a second switch means M2, and a 12-bit digital code signal input terminal D [11. : 0], clock input terminal CLK, sleep signal input terminal SLEEP, forced off signal input terminal T _set , four test mode switching signal input terminals TEST1 to TEST4, first test signal input terminal T _in , first test signal output terminal T _out , second test signal input terminals T _load and T _clk , second test signal output terminals T _outh and T _outl , and an analog output terminal AMP _out .

The reference voltage generation circuit 20 generates a reference voltage used in the D / A converter 1, and its output V _out is connected to the VRT terminal of the D / A conversion circuit 10. The reference voltage generation circuit 20 receives the sleep signal from the sleep signal input terminal SLEEP and the test mode switching signal from the test mode switching signal input terminal TEST3.

First switching means using the NMOS transistor M1 is connected between the VRT terminal of the first test signal input terminal _{T in} the D / A converter 10. The gate of the first switch means M1 is connected to the test mode switching signal input terminal TEST1.

The second switch means M2 using an NMOS transistor is connected between the first test signal output terminal T _out and the DA _out terminal of the D / A conversion circuit 10. The gate of the second switch means M2 is connected to the test mode switching signal input terminal TEST2.

In addition to the above, the D / A converter circuit 10 includes a 12-bit digital code signal input terminal D [11: 0], a clock signal terminal CLK, a sleep signal terminal SLEEP, a forced off signal input terminal T _set , a test mode switching signal. input terminal TEST4, second test signal input terminal _{T load} and _{T clk} is connected, the signal is inputted from the terminals. The D / A conversion circuit 10 is connected to the second test signal output terminals T _outh and T _outl, and a signal is output from each terminal. The analog conversion voltage D / A converted by the D / A conversion circuit 10 is output from the AMP _out terminal.

The configuration of the reference voltage generation circuit 20 according to the present embodiment will be described with reference to FIG. FIG. 2 is an internal circuit diagram of the reference voltage generation circuit 20. As shown in FIG. 2, the reference voltage generation circuit 20 includes a reference voltage generation circuit 21 using a band gap reference, an operational amplifier circuit 22, resistors R21 and R22 as feedback resistors, and switch means M21 using an NMOS transistor. . The reference voltage output from the reference voltage generation circuit 21 is amplified by the operational amplifier circuit 22 and output from the output terminal _Vout .

  A sleep signal can be input from the sleep signal input terminal SLEEP to the reference voltage generation circuit 21 and the operational amplifier circuit 22, and when the sleep signal is applied, the reference voltage generation circuit 21 and the operational amplifier circuit 22 operate together. It stops and the power consumption becomes almost zero. At this time, the output of the operational amplifier circuit 22 is in a high impedance state.

  The switch means M21 is connected between the resistor R22 and the ground potential, and a test mode switching signal is applied to the gate from the test mode switching signal input terminal TEST3. The switch means M21 is turned on when the signal from the test mode switching signal input terminal TEST3 is at a high level, and one end of the resistor R22 is connected to the ground potential. On the other hand, the switch means M21 is turned off when the signal from the test mode switching signal input terminal TEST3 is at a low level, and the connection between the resistor R22 and the ground potential is cut off.

  The configuration of the D / A conversion circuit 10 according to the present embodiment will be described with reference to FIG. FIG. 3 is an internal circuit diagram of the D / A conversion circuit 10. As shown in FIG. 3, the D / A converter circuit 10 includes a decoder 11 that decodes a low-bit digital code signal (D0 to D5) into 64 lines, and an output signal of the decoder 11 is synchronized with an input signal from a clock signal terminal CLK. Latch circuit 12 for latching, decoder 13 for decoding high-bit digital code signals (D6 to D11) into 64 lines, and latch circuit 14 for latching the output signal of decoder 13 in synchronization with the input signal from clock signal terminal CLK 3, a resistance voltage dividing circuit 15 surrounded by a broken line, an operational amplifier circuit 16 that amplifies an output voltage from the resistance voltage dividing circuit 15, resistors R11 and R12 that are feedback resistors of the operational amplifier circuit 16, a test mode switching signal Switch means M11 using an NMOS transistor which is ON / OFF controlled by an input signal from the input terminal TEST4; Equipped with an anti-R0.

  Further, the voltage dividing resistor circuit 15 includes 4096 resistors R1 to R4096, 64 switch means SL0 to SL63 using NMOS transistors that are ON / OFF controlled by the output of the latch circuit 12, and ON by the output of the latch circuit 14. 4096 switch means S1 to S4096 using NMOS transistors which are controlled to be turned off.

  The switch means M11 and the resistor R0 are connected in series, and the resistor R0 is connected to a resistor R1 that is one end of resistors R1 to R4096 connected in series to the ground potential.

The non-inverting input of the operational amplifier circuit 16 is connected to the DA _out terminal which is the output of the resistance voltage dividing circuit 15, and the inverting input is a connection node of resistors R11 and R12 connected in series between the output and the ground potential. It is connected to the.

The forced off signal input terminal T _set and the second test signal input terminals T _load and T _clk are connected to the latch circuits 12 and 14 as input sides, and the second test signal output terminals T _outh and T _outl are connected as output sides. Has been.

The configuration of the latch circuits 12 and 14 will be described with reference to FIG. FIG. 4 is an internal circuit diagram of the latch circuits 12 and 14 according to the present embodiment. As shown in FIG. 4, the latch circuits 12 and 14 latch the decoded 64-line signal in synchronization with the input signal from the clock signal terminal CLK, and the signal latched by the latch circuit 17 is the first. 2 A shift register circuit that holds the signal in synchronization with the load signal from the test signal input terminal T _load and then _performs bit shift in synchronization with the clock signal from the second test signal input terminal T _clk and sequentially outputs it to T _outh or T _outl 18 is provided. The latch circuit 17 can initialize the output value at the forced-off signal input terminal T _set .

  From here, with reference to FIG. 1 thru | or FIG. 4, operation | movement of the D / A converter 1 which concerns on this Embodiment is demonstrated. When the D / A converter 1 performs a normal operation, the states of the test mode switching signals from the test mode switching signal input terminals TEST1 and TEST2 are both low, and the test mode from the test mode switching signal input terminals TEST3 and TEST4. The state of the switching signal is high level.

  On the other hand, in the test mode in which the D / A converter 1 performs an operation test, the states of the test mode switching signals from the test mode switching signal input terminals TEST1 and TEST2 are both high level, and the test mode switching signal input terminals TEST3 and TEST4. The state of the test mode switching signal from is low level.

When the D / A converter 1 performs a normal operation, the states of the test mode switching signals from the test mode switching signal input terminals TEST1 and TEST2 are both at a low level, so that the first switch means M1 and the second switch means 2 shown in FIG. The switch means M2 is turned off, and the first test signal input terminal T _in and the first test signal output terminal T _out are disconnected from the internal circuit. Further, since the state of the test mode switching signal from the test mode switching signal input terminals TEST3 and TEST4 is at a high level, the switch means M21 shown in FIG. 2 is turned on, and the operational amplifier circuit 22 has resistance values of the feedback resistors R21 and R22. The output voltage of the reference voltage generation circuit 21 is amplified at an amplification factor determined by the above and applied to the VRT terminal of the D / A conversion circuit 10.

  At the same time, the switch means M11 shown in FIG. 3 is also turned on and one end of the resistor R0 is connected to the ground potential, so that the reference voltage is applied from the reference voltage generating circuit 20 to the resistors R0 to R4096 connected in series. The D / A converter 1 performs normal D / A conversion. Since the normal operation of the D / A converter 1 is well known, the description of the operation is omitted here. The operation of the D / A converter 1 when switching to the test mode will be described in detail below.

  First, when an operation test of the D / A converter 1 is performed, a sleep signal is input (applied) to the D / A converter 1 from the sleep signal input terminal SLEEP. Then, the operations of the reference voltage generation circuit 21 and the operational amplifier circuit 22 shown in FIG. 2 are stopped, and the output of the operational amplifier circuit 22 becomes high impedance as described above. At the same time, the operational amplifier circuit 16 shown in FIG.

  Next, the state of the test mode switching signal from the test mode switching signal input terminals TEST3 and TEST4 is set to a low level. Then, the switch means M21 shown in FIG. 2 and the switch means M11 shown in FIG. 3 are turned off. When the switch means M11 is turned off, the connection on the ground side of the resistors R0 to R4096 connected in series is disconnected. Further, when the switch means M21 is turned off, the connection where the VRT terminal side of the resistance voltage dividing circuit 15 is grounded via the feedback resistors R21 and R22 and the switch means M21 shown in FIG. 2 is also disconnected. As a result, the connections at both ends of the resistors R0 to R4096 are completely disconnected from other circuits.

Further, the state of the test mode switching signal from the test mode switching signal input terminals TEST1 and TEST2 is set to the high level. Then, the first switching means M1 and the second switching means M2 shown in FIG. 1 is turned on, the first test signal input terminal _{T in} is coupled to VRT terminal of the D / A conversion circuit 10, one end of the resistor R4096 is It is connected to the first test signal input terminal _{T in.}

Then, the next, and sets the arbitrary digital code signals D0-D11, the first test signal input terminal T _in a predetermined voltage is applied, the voltage is output to the first test signal output terminal T _out Make sure. At the same time, a predetermined signal is input from the second test signal input terminal T _load and the shift register circuit 18 holds the state of the on / off control signal of the switch means (the signal latched by the latch circuit 17). Thereafter, a predetermined signal is input from the second test signal input terminal T _clk to the shift register circuit 18 a predetermined number of times, and an ON / OFF control signal for the switch means is sequentially output from the second test signal output terminals T _outh and T _outl. To verify that. By performing the above confirmation for all combinations of the digital code signals D0 to D11, the operation test of the D / A converter 1 is completed.

  Hereinafter, an operation test of the D / A converter 1 will be specifically described. Here, all the digital code signals D0 to D11 are set to “0”, and the operation test of the D / A converter 1 is performed. Then, the switch means SL0 and S1 to S64 of the resistance voltage dividing circuit 15 are turned on.

At this time, by applying a voltage V1 to the first test signal input terminal _{T in,} applied voltage V1 passes through the first switching means M1, is applied to VRT terminal of the D / A conversion circuit 10, a series resistor R4096 The first test of the D / A converter 1 is passed through R1, further through the ON switch means S1 and SL0, and output to the DA _out terminal of the D / A converter circuit 10, and through the second switch means M2. The signal is output to the signal output terminal _Tout . That is, the voltage applied to the first test signal input terminal T _in is output to the test signal output terminal T _out as it is.

Further, in the digital code signal (switching means on / off control signal) in the above state, that is, the outputs of the latch circuits 12 and 14 (there are 64 outputs for each circuit), H0 is Hi logic, and H1 to H63 are Low logic, L0 is Hi logic, and L1 to L63 are Low logic. At this time, a pulse signal is input once to the second test signal input terminal T _load and the state of the on / off control signal is held in the shift register circuit 18. Then, the pulse signal is input 64 times from the second test signal input terminal T _clk to the shift register circuit 18 to perform 64 bit shifts. That is, the logic states of _H0 to _H63 are sequentially output from the second test signal output terminal Touth, and the logic states of _L0 to _L63 are sequentially output from the second test signal output terminal _Toutl .

Furthermore, the latch circuits 12 and 14 can be initialized from the forced off signal input terminal T _set to Low logic, and by turning all the on / off control signals of the switch means to the off state, the first test signal input terminal Hiz (high impedance) is output to the T _out.

Each bit of the digital code signal D0~D11 all until "1", a digital code signal D [11: 0] value when is sequentially increased, the pass voltage applied to the first test signal input terminal T _in is As the number of resistors decreases by one, the switch means that is turned on is sequentially switched, and the voltage applied to the first test signal input terminal T _in is always output to the first test signal output terminal T _out .

If, switch means SL0～SL63, when there is a faulty connection to S1～S4096, output and first test signal of the first test signal output terminal _{T out} when setting the digital code signal to which the switch means is turned on since the voltage applied to the input terminal T _in does not match, it is possible to detect the failure of the switching means.

Similarly, the result of decoding into 64 lines changes according to the state of the digital code signal, and the on / off control signal of the switch means also changes sequentially, and the state changes to the second test signal output terminal T _outh. And T _outl . If the switch means has a defect in the on / off control signal and the wrong switch means is selected, it can be detected because it is output from the second test signal output terminals T _outh and T _outl .

Further, by using the forced off signal input terminal T _set to initialize all outputs of the latch circuits 12 and 14 to low logic, when the switch means is always on and fails, the first test signal input terminal T _Since a voltage other than high impedance (Hiz) is output from out, a failure of the switch means can be detected.

The D / A converter 1 can be expected to operate at a higher speed as the voltage amplitude V1 of the input test signal is lower. However, the D / A converter 1 has a restriction due to the characteristics of the NMOS transistor used in the switch means, and therefore the input test signal is changed. The voltage amplitude V1 was set to about 2V. Also, assuming 50 pF as the load of the measuring instrument connected to the test signal output terminal T _out , the settling time due to the time constant is 100 μSec. For this reason, assuming that the period of the clock signal is 200 μSec, the time required for the inspection of all the switch means S1 to S4096 and SL0 to SL63 is about 0.8 Sec (= 200 μSec × number of switch means 4160).

Similarly, assuming that the settling time is 100 μSec, a pulse signal is input from the second test signal input terminal T _load every 200 μSec, and a total of 64 pulse signals are output from the second test signal input terminal T _clk every 3.125 μSec. If it is input, two types of operation tests can be performed at the same time, so the time required for the operation test does not increase from the above-mentioned about 0.8 seconds.

In actual operation test, the first test signal input terminal T _in applying the clock signal as shown on FIG. 5 as the test signal. Then, from the first test signal output terminal T _out signal dull the waveform as shown below FIG. 5 is output.

In an actual operation test, a test signal having a waveform as shown in the upper part of FIG. 6 is applied from the second test signal input terminals T _load and T _clk . Then, signals having waveforms as shown in the lower part of FIG. 6 are output from the second test signal output terminals T _outh and T _outl .

(Summary)
According to the disclosed D / A converter, a means for holding a signal for controlling the switch means in accordance with a digital code signal in a test mode, a second test signal input terminal for holding and outputting the control signal, Since the second test signal output terminal for outputting the holding signal is provided, the operation test of the switch means including the signal for controlling the on / off of the switch can be performed in a short time.
According to the disclosed D / A converter, since the plurality of second test signal output terminals are provided, all the bits can be tested in a short time by observing the plurality of second test signal output terminals simultaneously. .
According to the disclosed D / A converter, by separately providing means for holding and outputting in the test mode, even if the means malfunctions, the operation in the normal operation mode is not affected.
According to the disclosed D / A converter, by providing means for turning off all the plurality of switch means in the test mode, it is possible to observe a state in which the switch means is always on.
According to the disclosed D / A converter, it is possible to perform an operation test in a short time by making the periods of two different operation tests the same.
Although the embodiment of the present invention has been described in detail above, the present invention is not limited to the specific embodiment, and various modifications are possible within the scope of the gist of the present invention described in the claims.・ Change is possible.

DESCRIPTION OF SYMBOLS 1 D / A converter 10 D / A conversion circuit 20 Reference voltage generation circuit 11, 13 Decoder 12, 14 Latch circuit 15 Resistance voltage dividing circuit 16, 22 Operation amplifier circuit 17 Latch circuit 18 Shift register circuit 21 Reference voltage generation circuit S1 S4096, SL0 to SL63 Switch means M1 First switch means M2 Second switch means M11, M12 Switch means R0 to R4096 Voltage dividing resistors R11, R12, R21, R22 Feedback resistors

JP 2006-279132 A JP 2008-277940 A

Claims (4)

A D / A converter for D / A converting and outputting an input digital code signal,
An input voltage is divided by a plurality of voltage dividing ratios by a plurality of resistors connected in series, and one voltage among the divided voltages is supplied via a plurality of switches that are controlled to be turned on / off according to the digital code signal. A D / A conversion circuit unit that outputs as an analog signal is provided.
The D / A converter circuit section, when the first test signal as the input voltage is input, and outputs the analog signal corresponding to the first test signal, said first test signal input The state of ON / OFF control of the plurality of switches according to the digital code signal at the time of being held is held in a holding means, and the second pulse signal is a number corresponding to the number of bits of the digital code signal. When a test signal is input, the holding means outputs a state of on / off control of the plurality of switches by performing a bit shift according to the second test signal. A converter. The D / A converter according to claim 1 , comprising a plurality of the holding means. 3. The D / A converter according to claim 1, wherein the D / A conversion circuit unit includes an off control unit configured to turn off all of the plurality of switches. An operation test method for a D / A converter according to any one of claims 1 to 3 ,
Type the first test signal as the input voltage to the D / A converter circuit section, determining whether said analog signal corresponding to the first test signal is output from the D / A converter circuit unit And steps to
Receiving the second test signal and determining whether or not the digital code signal output from the D / A converter circuit unit matches a desired digital code signal. Test method.

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