JP5423478B2 - Pulse width modulation circuit - Google Patents

Description

  The present invention relates to a pulse width modulation circuit using an astable multivibrator circuit that converts an input signal such as an audio signal into a pulse width modulation signal.

  2. Description of the Related Art Conventionally, a pulse width modulation circuit using an astable multivibrator circuit is known as a pulse width modulation circuit used in a class D amplifier circuit for audio.

  FIG. 6 is a diagram illustrating an example of a pulse width modulation circuit using a conventional astable multivibrator circuit. The astable multivibrator circuit shown in the figure uses a comparator as a logic circuit for outputting a rectangular wave.

  The pulse width modulation circuit 101 shown in FIG. 6 converts the audio signal Sin (voltage signal) into two currents J1 and J2 using a differential amplifier circuit, and is included in the astable multivibrator circuit 103 with each current J1 and J2. The two PWM signals Spwm and / Spwm, in which the pulse width (high level period) is modulated by the amplitude of the audio signal Sin, are charged to the two capacitors C1 and C2 respectively, and the two comparators of the astable multivibrator circuit 103 This is a circuit for outputting from COMP1 and COMP2.

In the pulse width modulation circuit 101, as shown in FIG. 7, when the audio signal Sin varies in level between “+ S” and “−S” with reference to 0v, the level variation range 2S is used as the current value variation range. A current J1 having a current value Ip and a current value (2Io−Ip) proportional to 2Io and having a current value Ip apportioned at a ratio indicating the position of the voltage level Sp at an arbitrary point P in the level fluctuation range 2S is generated. Capacitors C1 and C2 having the same capacity with these currents J1 and J2 are charged until their charging voltage changes the same, and the charging time by current J1 is at a high level (hereinafter referred to as “High”). the period T _ON, low charging time by the current J2 level (hereinafter. to be referred to as "low") to generate a PWM signal Spwm to the period T _OFF of.

When the capacitance of the capacitor is C, there is a relationship of i = C × (Δv / Δt) between the current i flowing through the capacitor and the voltage v across the capacitor. If the time Δt for changing the voltage across the capacitor by Δv is very small, the current i at the time Δt can be considered to be almost constant. Therefore, the current value is I, the change width of the voltage across the capacitor is ΔVj, and the charging time is If Tj, the relationship of I × T = C × V is established. Therefore, when the capacitor C1 is charged with the current J1, Ip × T1 = C × V and when the capacitor C2 is charged with the current J2, (2Io -Ip) * T2 = C * V. Since T _ON : T _OFF = Ip: (2Io−Ip) is established from T1 = T _ON , T2 = T _OFF and Ip × T1 = (2Io−Ip) × T2, the current value and the PWM signal in FIG. As shown in the relationship of the pulse waveform of Spwm, the ratio of the high period T _ON and the low period T _OFF of the PWM signal Spwm is proportional to the ratio of the two current values Ip and the current value (2Io−Ip).

  In the example of FIG. 7, the current value Ip is Ip = (S−Sp) × 2Io / 2S = (S−Sp) × Io / S = Io × (1−Sp / S) = Io−k × Sp (however, , K = Io / S), and the current value (2Io−Ip) is expressed by (2Io−Ip) = 2Io− (Io−k × Sp) = Io + k × Sp. Then, a current J1 having a current value (Io−k × Sp) and a current J2 having a current value (Io + k × Sp) are generated.

  Returning to FIG. 6, the voltage-current conversion circuit 102 which converts the audio signal Sin (voltage signal) using the differential amplifier circuit of the pulse width modulation circuit 101 into two currents J1 and J2 includes the base voltage of the transistor Tr1 and the transistor An operation of amplifying the difference voltage between the base voltages of Tr2 and outputting as a difference voltage between the collector voltage of the transistor Tr1 and the collector voltage of the transistor Tr2 is performed. Focusing on the current of the voltage-current conversion circuit A, if the constant current supplied from the constant current source is “2 × Io” and the amplitude of the audio signal Sin is “Sin”, the collector current Ic1 of the transistor Tr1 is Ic1 = Io−i (where i = Sin / (2 × Re)), the collector current Ic2 of the transistor Tr2 is Ic2 = Io + i, and the collector currents Ic1 and Ic2 satisfy the relationship between the current J1 and the current J2. The collector current Ic1 of the transistor Tr1 and the collector current Ic2 of the transistor Tr2 are respectively charged with a current J1 for charging the capacitor C1 of the astable multivibrator circuit 103 (hereinafter referred to as “charging current J1”) and a current J2 for charging the capacitor C2 ( Hereinafter, it is used as “charging current J2”.

  Therefore, in the pulse width modulation circuit 101, the collector of the transistor Tr1 of the voltage-current conversion circuit 102 is connected to the connection point (A) between the capacitor C1 and the comparator COMP2, and the collector of the transistor Tr2 is connected to the connection point (the connection point between the capacitor C2 and the comparator COMP1 ( C) is connected.

  The reference voltage Vref is input to the positive input terminals of the two comparators COMP1 and COMP2 of the astable multivibrator circuit 103. In each of the comparators COMP1 and COMP2, the output terminal is at a high level when the voltage at the negative input terminal is smaller than the reference voltage Vref, and the output terminal is at a low level when the voltage at the negative input terminal is equal to or higher than the reference voltage Vref. In FIG. 6, since the drive voltages “Vhi (> 0)” and “Vlo (<Vhi)” are supplied to both the comparators COMP1 and COMP2, the high level voltage becomes “Vhi”, and the low level The voltage is “Vlo”.

  The diode D1 of the astable multivibrator circuit 103 stops the charging of the capacitor C1 by the charging current J1 when the charging voltage Vc1 (voltage at the connection point (A)) of the capacitor C1 rises to the reference voltage Vref, and the capacitor C1 This is for discharging the accumulated electric charge. When the charging voltage Vc1 of the capacitor C1 rises to the reference voltage Vref, the level of the output terminal of the comparator COMP2 is inverted to the low level Vlo, whereby the output level of the comparator COMP1 is inverted to the high level Vhi and the connection point (A) Although the voltage Vc1 jumps to (Vhi + Vref), the diode D1 is turned on by this voltage rise, the charging current J1 is bypassed to the power source of the driving voltage Vhi on the upper side of the comparator COMP2, and all the accumulated charge in the capacitor C1 is discharged. The voltage Vc1 at the connection point (A) is clamped to the voltage Vhi.

  The diode D2 also performs the same function as the diode D1. When the charging voltage Vc2 (voltage at the connection point (c)) of the capacitor C1 rises to the reference voltage Vref, the level of the output terminal of the comparator COMP1 is inverted to the low level Vlo, and thereby the output level of the comparator COMP2 becomes the high level Vhi. The voltage Vc2 at the connection point (c) jumps to (Vhi + Vref) by inversion, but this voltage rise causes the diode D2 to conduct and the charging current J2 is bypassed to the power supply of the driving voltage Vhi on the upper side of the comparator COMP2. At the same time, the accumulated charge in the capacitor C2 is completely discharged, and the voltage Vc2 at the connection point (c) is clamped to the voltage Vhi.

  FIG. 8 is a waveform diagram of voltages at connection points (A) to (D) during operation of the pulse width modulation circuit shown in FIG. The operation of the pulse width modulation circuit 101 shown in FIG. 6 will be briefly described with reference to FIG. 8. When the input level of the comparator COMP2 reaches the reference voltage Vref at the timing t1, and the output level is inverted to the low level Vlo (( D), the charging of the capacitor C1 by the collector current Ic1 (charging current J1) of the transistor Tr1 is started (see the voltage waveform in (a)). On the other hand, since the output level of the comparator COMP1 is inverted to the high level Vhi at the timing t1 (see the voltage waveform in (B)), the voltage Vc2 at the connection point (C) is changed from the charging voltage Vref of the capacitor C2 to the charging voltage Vref. Since it jumps to a value (Vhi + Vref) obtained by adding the output level Vhi of the comparator COMP1, the diode D2 becomes conductive, and the accumulated charge in the capacitor C2 is completely discharged, so that the voltage Vc2 at the connection point (c) is the driving voltage Vhi of the comparator COMP2. (See voltage waveform in (c)).

  When charging of the capacitor C1 is started at the timing t1, the voltage Vc1 at the connection point (A) increases at a speed (waveform slope) corresponding to the charging current J1. As described above, since the charging current J1 can be regarded as substantially constant, the voltage at the connection point (A) rises substantially linearly. The output level of the comparator COMP1 is maintained at the high level Vhi while the voltage Vc1 at the connection point (A) is smaller than the reference voltage Vref, but the voltage Vc1 at the connection point (A) reaches the reference voltage Vref at the timing t2. Then, it is inverted to the low level Vlo (refer to the voltage waveform in (b)). When the output level of the comparator COMP1 is inverted to the low level Vlo, the voltage Vc2 at the connection point (c) changes to the low level Vlo, and charging of the capacitor C2 by the collector current Ic2 (charging current J2) of the transistor Tr2 is started ( (See voltage waveform in (c)).

  On the other hand, when the voltage Vc2 at the connection point (c) changes to the low level Vlo at the timing t2, the output level of the comparator COMP2 is inverted to the high level Vhi (see the voltage waveform in (d)). At this time, the voltage Vc1 at the connection point (A) jumps from the charging voltage Vref of the capacitor C1 to a value obtained by adding the output level Vhi of the comparator COMP2 to the charging voltage Vref (Vhi + Vref). All the accumulated charges in C1 are discharged, and the voltage Vc1 at the connection point (A) is clamped to the drive voltage Vhi of the comparator COMP1 (see the voltage waveform in (A)).

  When charging of the capacitor C2 is started at the timing t2, the voltage Vc2 at the connection point (c) increases at a speed (waveform slope) corresponding to the charging current J2. Similarly to the charging current J1, the charging current J2 can be regarded as substantially constant, so that the voltage at the connection point (c) rises almost linearly. The output level of the comparator COMP2 is maintained at the high level Vhi while the voltage Vc2 at the connection point (c) is smaller than the reference voltage Vref, but the voltage Vc2 at the connection point (c) reaches the reference voltage Vref at the timing t3. Then, the voltage is inverted to the low level Vlo (see voltage waveform (d)), and thereafter, the charging operation of the capacitor C1 during the period from t1 to t2 and the charging operation of the capacitor C2 during the period from t2 to t3 are alternately repeated. It is. As a result, the PWM signal Spwm is output from the output terminal of the comparator COMP1 with the charging period T1 of the capacitor C1 as the High period and the charging time T2 of the capacitor C2 as the Low period, and the charging period T2 of the capacitor C2 from the output terminal of the comparator COMP2 Is the High period, and the PWM signal / Spwm is output with the charging time T1 of the capacitor C1 as the Low period.

JP 2007-28455 A

  The principle of pulse width modulation of the pulse width amplification circuit 101 shown in FIG. 6 is that the charging voltage range of the capacitors C1 and C2 is set to the same range (voltage Vlo on the assumption that the capacitance of the capacitor C1 and the capacitance of the capacitor C2 are the same. On the other hand, as shown in FIG. 7, a current J1 = Io− (k × Sin) and a current J2 whose current value varies in proportion to the amplitude of the audio signal Sin. = Io + (k.times.Sin), the capacitor C1 is charged by the current J1 from the lower drive voltage Vlo of the comparator COMP1 to the reference voltage Vref and converted to the charging time T1, and the capacitor C2 is compared with the comparator COMP2 by the current J2. By alternately performing the operation of charging from the lower drive voltage Vlo to the reference voltage Vref and converting to the charge time T2, The PWM signal Spwm and charge time T2 that the width is that to generate a PWM signal / Spwm to the pulse width.

  The charge voltage range from the lower drive voltage Vlo to the reference voltage Vref of the comparators COMP1 and COMP2 is “V” (= Vref−Vlo), and the capacitances of the capacitors C1 and C2 are “c1” and “c2”, respectively. If the accumulated charge at the start of charging of C1 and C2 is zero, the charge amount Q1 accumulated in the capacitor C1 by the charging current J1 is represented by Q1 = c1 × V, and the charge amount accumulated in the capacitor C2 by the charging current J2. Q2 is represented by Q2 = c2 × V. Since the conventional pulse width amplifier circuit 101 is based on the premise that c1 = c2, Q1 = Q2. Therefore, when Q1 = Q2 = Qo, the pulse width modulation principle of the pulse width amplifier circuit 101 is determined by the charging current J1. A PWM signal Spwm that generates a time T1 required to store the charge amount Qo in the capacitor C1 and a time T2 required to store the charge amount Qo in the capacitor C2 by the charging current J2 and uses the charging time T1 as a pulse width. A PWM signal / Spwm having a charging time T2 as a pulse width is generated.

Assuming that the capacities c1 and c2 of the capacitors C1 and C2 are c1 = c2 = Co, between the accumulated charge amount Qo, the charging currents J1 and J2, the charging times T1 and T2, and the charging voltage range V,
J1 * T1 = Co * V = Qo (1)
J2 × T2 = Co × V = Qo (2)
Therefore, the modulation degree m = | (T1-T2) from T1−T2 = Q ≠ × (J2−J1) / (J1 × J2) and T1 + T2 = Qo × (J2 + J1) / (J1 × J2). ) / (T1 + T2) |
M = | (J2−J1) / (J2 + J1) | (3)
It becomes.

Substituting J1 = Io−i = Io−k × Sin, J2 = Io + i = Io + k × Sin (where k = Io / S) into the above equation (3),
M = i / Io = Sin / S (4)
Thus, it can be seen that the degree of modulation m is proportional to the amplitude of the audio signal Sin.

  In practice, however, the capacitance c1 of the capacitor C1 and the capacitance c2 of the capacitor C2 are usually different due to individual differences between the elements, so that the capacitance difference between the capacitor C1 and the capacitor C2 appears in the difference between the charging times T1 and T2 and is modulated. The degree m is not exactly proportional to the amplitude of the audio signal Sin.

When (T1−T2) and (T1 + T2) are obtained by setting the charge amounts Q1 and Q2 stored in the capacitors C1 and C2 to Q1 ≠ Q2, T1−T2 = Q1 / J1−Q2 / J2, T1 + T2 = Q1 / J1 + Q2 / Since it becomes J2, the modulation degree m is
M = (Q1 * J2-Q2 * J1) / (Q1 * J2 + Q2 * J1) (5)
It becomes.

Substituting J1 = Io−i = Io−k × Sin, J2 = Io + i = Io + k × Sin (where k = Io / S) into the above equation (5),
M = {Qp × Io + Qq × k × Sin} / {Qq × Io + Qp × k × Sin] (6)
However, Qp = Q1-Q2, Qq = Q1 + Q2
Thus, it can be seen that the modulation degree m is not proportional to the amplitude of the audio signal Sin.

  Considering the case where the audio signal Sin is no signal (i = 0), when c1 = c2 = Co, J1 = J2 = Io. Therefore, the charging time T1 from the above equations (1) and (2). , T2 are T1 = (Co × V) / Io and T2 = (Co × V) / Io, so that T1 = T2. Therefore, the duty ratio of the PWM signals Spwm, / Spwm is 50%.

  When c1 ≠ c2, the charge amounts Q1 and Q2 accumulated in the capacitors C1 and C2, respectively, are Q1 = c1 × V and Q2 = c2 × V. Therefore, the charging times T1 and T2 are T1 = Q1 / Io = Since (c1 × V) / Io, T2 = Q2 / Io = (c2 × V) / Io, T1 = T2 is not satisfied. Therefore, the duty ratio of the PWM signals Spwm, / Spwm does not become 50%.

  When the audio signal Sin is no signal, if c1 = c2, T1 = T2 and the modulation degree m is zero, but if c1 ≠ c2, T1 ≠ T2 and the modulation degree m is zero. do not become. The fact that the degree of modulation m is not zero means that a DC offset component is included in the demodulated signals of the PWM signals Spwm, / Spwm.

  According to the above equation (6), unless Qp = Q1-Q2 = 0, m = i / Io, and in order to make the modulation degree m proportional to the amplitude of the audio signal Sin, Qp = It can be seen that Q1-Q2 = 0 needs to be set.

  Since Q1 = c1 × V and Q2 = c2 × V, and the capacitance c1 of the capacitor C1 and the capacitance c2 of the capacitor C2 are different, in order to set Q1-Q2 = 0, the range of the charging voltage of the capacitor C1 and the capacitor C2 When the charging voltage ranges are “V1” and “V2”, respectively, it is necessary to make them different from each other so as to satisfy c1 / c2 = V2 / V1.

  In the conventional pulse width amplifier circuit 101, the upper voltage that determines the charging voltage ranges V1 and V2 of the capacitors C1 and C2 is shared with the reference voltage “Vref”, and the lower voltage is the lower side of the comparators COMP1 and COMP2. Drive voltage “Vlo”, and at the end of charging, all the charges accumulated in the capacitors C1 and C2 are discharged and the voltage at the start of charging is set to the voltage Vlo. Therefore, V1 = V2 = V, and the modulation degree m cannot be exactly proportional to the amplitude of the audio signal Sin.

  In order to solve the above problem, the reference voltage Vref1 input to the positive input terminal of the comparator COMP1 is different from the reference voltage Vref2 input to the positive input terminal of the comparator COMP2, and the charge voltage range V1 = Vref1−Vlo of the capacitor C1. And the charging voltage range V2 = Vref2-Vlo of the capacitor C2 may satisfy the condition of c1 / c2 = (Vref2-Vlo) / (Vref1-Vlo).

  However, in this method, for example, when a semiconductor element composed of a CMOS-IC driven by the same power source such as an inverter element is used as a circuit that performs the functions of the comparators COMP1 and COMP2, the reference voltage Vref is applied to the semiconductor. Since it is uniquely determined by the threshold voltage of the element (the voltage approximately at the center of the upper drive power supply Vhi and the lower drive power supply Vlo), it is difficult to adopt.

  The present invention has been conceived under the circumstances described above, and the difference between the capacitance values of the two capacitors is obtained without completely discharging the accumulated charge at the end of charging of the two capacitors of the astable multivibrator. The charge voltage range of both capacitors is made different by leaving the corresponding charge, so that even if the capacitance values of the two capacitors are different, the modulation factor of the pulse width modulation signal is accurately proportional to the amplitude of the input signal. An object of the present invention is to provide a pulse width modulation circuit that can be made to operate.

  The pulse width modulation circuit according to claim 1, wherein a current value obtained by dividing a voltage signal whose level fluctuates in a predetermined level fluctuation range by dividing a predetermined constant current value by a ratio indicating a position of the level in the level fluctuation range. A voltage-current conversion circuit that converts two current signals, a first logic circuit that operates in an inverse relationship between an input level and an output level, and a second logic having the same configuration as the first logic circuit And the first current output from the voltage-current conversion circuit is connected between the output terminal of the circuit, the output terminal of the second logic circuit, and the input terminal of the first logic circuit. A first charge storage circuit supplied as a charging current from a connection point with the input terminal of the first logic circuit, connected between the output terminal of the first logic circuit and the input terminal of the second logic circuit, and the voltage-current The second output from the conversion circuit A second charge storage circuit in which a current is supplied as a charging current from a connection point with the input terminal of the second logic circuit; and a second charge storage circuit connected to the input terminal of the first logic circuit; When the input level of the first logic circuit reaches a predetermined threshold level by the charging operation of one charge storage circuit, the input terminal of the first logic circuit is connected to a first variable voltage power source to connect the first logic circuit. And the second current circuit is connected to an input terminal of the first logic circuit for stopping the charge operation of the first charge storage circuit and discharging the stored charge of the first charge storage circuit. When the input level of the second logic circuit reaches the threshold level by the charging operation of the second charge storage circuit according to the above, the input terminal of the second logic circuit is connected to a second variable voltage power source, and Charge operation of the second charge storage circuit And a second discharge circuit that discharges the accumulated charge of the second charge accumulation circuit, and the pulse width is modulated by the amplitude of the voltage signal from the output terminal of the first logic circuit. 1 pulse width modulation signal is output, and a second pulse width modulation signal whose phase is inverted with respect to the first pulse width modulation signal is output from the output terminal of the second logic circuit. The voltage of the first variable voltage power source and the voltage of the second variable voltage power source are the first pulse width modulation signal or the second pulse width when the amplitude of the voltage signal is zero. The high-level period and low-level period of the modulation signal are set to be the same.

  The pulse width modulation circuit according to claim 2 is the pulse width modulation circuit according to claim 1, wherein the first and second variable voltage power sources change a voltage value of the first variable voltage power source. And voltage adjusting means for changing the voltage value of the second variable voltage power supply in the same direction in the reverse direction as the first variable voltage power supply in conjunction with the first variable voltage power supply. The voltage of both variable power supplies is adjusted by adjusting the voltage of either of the second variable voltage power supplies.

  The pulse width modulation circuit according to claim 3 is the pulse width modulation circuit according to claim 2, wherein the first variable voltage power source outputs a voltage obtained by dividing a predetermined power source voltage. And the second variable voltage power supply is connected in parallel to the first semi-fixed resistor, and is composed of a second semi-fixed resistor that outputs a voltage obtained by dividing the power supply voltage, The movable terminal from which the divided voltage of the first semi-fixed resistor is output and the movable terminal from which the divided voltage of the second semi-fixed resistor is output are the same in the opposite directions. The voltage of the first variable voltage power supply and the second variable voltage power supply are adjusted by adjusting the fixed position of one of the movable terminals of the first and second semi-fixed resistors. Voltage is set.

  The pulse width modulation circuit according to claim 4 is the pulse width modulation circuit according to any one of claims 1 to 3, wherein the first logic circuit and the second logic circuit are driven by the same power source. It is composed of an inverter.

  According to the present invention, for example, when the input level of the second logic circuit reaches a predetermined threshold level and the output level is inverted to a low level, charging of the first charge storage circuit by the first current is started, When the input level of the first logic circuit reaches a predetermined threshold level by the charging operation of the first charge storage circuit, the output level of the first logic circuit is inverted to a low level. When the output level of the first logic circuit is inverted to the low level, the input level of the second logic circuit is changed to the low level, the output level of the second logic circuit is inverted to the high level, and the second current depends on the second current. Charging of the second charge storage circuit is started.

  When the output level of the second logic circuit is inverted to a high level, the voltage at the connection point of the first charge storage circuit with the input terminal of the first logic circuit rises, and the connection point becomes the first variable voltage power supply. And the charge operation of the first charge storage circuit is stopped, and the charge stored in the first charge storage circuit is discharged. That is, the charging operation of the first charge storage circuit is stopped when the input level of the first logic circuit reaches a predetermined threshold level, and the stored charge is discharged. When the input level of the first logic circuit is lowered to the voltage of the first variable voltage power supply due to the discharge of the accumulated charge of the first charge accumulation circuit, the voltage is held.

  On the other hand, when the charging of the second charge storage circuit by the second current is started and the input level of the second logic circuit reaches a predetermined threshold level by the charging operation of the second charge storage circuit, The output level of the logic circuit is inverted to the low level. When the output level of the second logic circuit is inverted to the low level, the input level of the first logic circuit becomes the low level, the output level of the first logic circuit is inverted to the high level, and Charging of the first charge storage circuit is started.

  When the output level of the first logic circuit is inverted to a high level, the voltage at the connection point between the second charge storage circuit and the input terminal of the second logic circuit rises, and the connection point becomes the second variable voltage power supply. And the charge operation of the second charge storage circuit is stopped, and the charge stored in the second charge storage circuit is discharged. That is, the charging operation of the second charge storage circuit is stopped when the input level of the second logic circuit reaches a predetermined threshold level, and the stored charge is discharged. When the input level of the second logic circuit is lowered to the voltage of the second variable voltage power source due to the discharge of the accumulated charge of the second charge accumulation circuit, the voltage is held.

  Thereafter, the charging operation of the first charge storage circuit and the charging operation of the second charge storage circuit are alternately repeated, so that the output level of the first logic circuit is alternately inverted, and the second logic circuit The output level is alternately inverted in the reverse relation to the first logic circuit, and a pulse width modulation signal in which the pulse width is modulated with the amplitude of the voltage signal is output from the first logic circuit. To output a pulse width modulation signal whose phase is opposite to that of the pulse width modulation signal output from the first logic circuit.

  In order to make the modulation degree of the pulse width modulation signal proportional to the amplitude of the voltage signal, the accumulated charge amount Q1 of the first charge accumulation circuit by the first current and the accumulated charge of the second charge accumulation circuit by the second current The quantity Q2 needs to be equal. If the modulation factor of the pulse width modulation signal is proportional to the amplitude of the voltage signal, the modulation factor m is zero when the amplitude of the voltage signal is zero.

When the amplitude of the voltage signal is zero, the first current and the second current are equal to a constant amount of current Io, so the range of the charging voltage of the first charge storage circuit (the input level of the first logic circuit) If the change range is “V1” and the charge voltage range of the second charge storage circuit (change range of the input level of the second logic circuit) is “V2”, the high period T1 of the first pulse width modulation signal Is T1 = Q1 / Io = c1 * V1 / Io, the low period T2 is T2 = Q2 / Io = c2 * V2 / Io, and the modulation degree m = (T1-T2) / (T1 + T2) is m = (c1 * V1-c2 × V2) /
(C1 × V1 + c2 × V2).

Therefore, when the amplitude of the voltage signal is zero, the first is set so as to satisfy c1 × V1 = c2 × V2.
It is necessary to set the charge voltage range V1 of the second charge storage circuit and the charge voltage range V2 of the second charge storage circuit.

  The charge voltage range V1 of the first charge storage circuit is such that the voltage that the first charge storage circuit holds by the first variable voltage power supply until the next charge starts is “Vr1”, and the predetermined threshold level is “Vth”. Then, V1 = Vth−Vr1, and the charge voltage range V2 of the second charge storage circuit is the voltage held by the second variable voltage power supply until the next charge is started by the second variable voltage power supply “Vr2”. , V2 = Vth−Vr2.

  According to the present invention, when the amplitude of the voltage signal is zero, the voltage Vr1 of the first variable voltage power supply and the voltage Vr2 of the second variable voltage power supply are c1 × (Vth−Vr1) = c2 × (Vth−Vr2). Therefore, even if c1 ≠ c2, the voltage Vr1 of the first variable voltage power supply and the voltage Vr2 of the second variable voltage power supply are set to different voltage values even when c1 ≠ c2. The modulation degree of the modulation signal can be made to be exactly proportional to the amplitude of the input voltage signal.

  Other features and advantages of the present invention will become more apparent from the detailed description given below with reference to the accompanying drawings.

It is a figure which shows the basic composition of 1st Embodiment of the pulse width modulation circuit using the astable multivibrator circuit which concerns on this invention. It is a figure which shows the waveform of the voltage of the connection points (A)-(D) at the time of operation | movement of the pulse width modulation circuit which concerns on 1st Embodiment. It is a figure which shows the modification of the current bypass circuit of the pulse width modulation circuit which concerns on 1st Embodiment. It is a figure which shows the basic composition of 2nd Embodiment of the pulse width modulation circuit using the astable multivibrator circuit which concerns on this invention. It is a figure which shows the waveform of the voltage of the connection points (A)-(D) at the time of operation | movement of the pulse width modulation circuit which concerns on 2nd Embodiment. It is a figure which shows an example of the pulse width modulation circuit using the conventional astable multivibrator. It is a figure for demonstrating the modulation principle of the pulse width modulation circuit using an astable multivibrator circuit. FIG. 7 is a waveform diagram showing an operation of the pulse width modulation circuit shown in FIG. 6.

  FIG. 1 is a diagram showing a basic configuration of a first embodiment of a pulse width modulation circuit using an astable multivibrator circuit according to the present invention. The astable multivibrator circuit 3 of the pulse width modulation circuit 1 shown in FIG. 1 uses a C-MOS inverter having the same characteristics as a circuit corresponding to the comparators COMP1 and COMP2 of the conventional pulse width modulation circuit 101 shown in FIG. It is. The circuits of the comparators COMP1 and COMP2 and the inverters INV1 and INV2 can use other logic circuits as long as they can output signals indicating the logic of the input level and the output level.

  Similar to the conventional pulse width modulation circuit 101 shown in FIG. 6, the pulse width modulation circuit 1 according to the first embodiment converts the audio signal Sin (voltage signal) into two currents J1 and J2. The pulse width (high period width) 2 is modulated by the amplitude of the audio signal Sin by charging the two capacitors C1 and C2 with the circuit 2 and the currents J1 and J2 output from the voltage-current conversion circuit 2, respectively. It comprises an astable multivibrator circuit 3 for outputting two PWM signals Spwm, / Spwm from inverters INV1, INV2, respectively.

  The basic circuit configuration of the pulse width modulation circuit 1 is the same as that of the conventional pulse width modulation circuit 101. However, in the pulse width modulation circuit 101, when the charging voltage of the capacitors C1 and C2 rises to the reference voltage Vref, the diodes D1 and D2 And the charging currents J1 and J2 are bypassed to the power source of the driving voltage Vhi on the upper side of the comparators COMP1 and COMP2, respectively, to stop the charging operation of the capacitors C1 and C2, and the charges accumulated in the capacitors C1 and C2 are In the pulse width modulation circuit 1 shown in FIG. 1, the voltage for bypassing the charging currents J1 and J2 is varied when the charging voltage of the capacitors C1 and C2 rises to the reference voltage Vref. The next charge of the capacitors C1 and C2 is started by varying the discharge amount of the charges accumulated in the capacitors C1 and C2 That each have a configuration to keep leaving a predetermined charge to differ.

  That is, in the pulse width modulation circuit 1, the upper limit value of the charging voltage range of the capacitors C1 and C2 is common to “Vref”, but the lower limit value (voltage at the start of charging) is made different so that both capacitors C1 and C2 The charging voltage ranges V1 and V2 satisfy c1 / c2 = V2 / V1. Therefore, if the lower limit value of the charging voltage range of the capacitor C1 is “Vl1” and the lower limit value of the charging voltage range of the capacitor C2 is “Vl2”, c1 / c2 = (Vref−Vl2) / (Vref−Vl1) The discharge amounts of the charges accumulated in the capacitors C1 and C2 are made different so as to satisfy the conditions.

  When c1 = c2, Vl1 = Vl2 = Vlo. Therefore, when c1 ≠ c2, if ΔV1 = Vl1−Vlo and ΔV2 = Vl2−Vlo, the amount of charge remaining in the capacitor C1 is c1 × ΔV1. The amount of charge remaining in the capacitor C2 is c2 × ΔV2.

  The current bypass circuit 4 provided in the pulse width modulation circuit 1 includes a voltage (clamp voltage Vk1) for bypassing the charging current J1 of the capacitor C1 and a voltage (clamp voltage Vk2) for bypassing the charging current J2 of the capacitor C2. In which the modulation degree m is not exactly proportional to the amplitude of the audio signal Sin due to the capacitance values of the capacitors C1 and C2 being different from each other by making the two voltages different. This circuit fulfills the function of eliminating

  Here, the principle of eliminating the above-described problems by the current bypass circuit 4 will be described with reference to the example of the pulse width modulation circuit 101 of FIG.

  As described above, when c1 ≠ c2, the charging voltage range V1 of the capacitor C1 and the charging voltage range V2 of the capacitor C2 are set to satisfy c1 × V1 = c2 × V2 in order to satisfy Q1 = Q2. There is a need.

Now, assuming that c2 <c1, since c1 / c2 = V2 / V1, V1 <V2. Therefore, if c1 = Co + ΔC, c2 = Co−ΔC (ΔC ≠ 0), V1 = Vo−ΔV, and V2 = Vo + ΔV (ΔV ≠ 0), the conditional expression for setting Q1 = Q2 is
(Co + ΔC) × (Vo−ΔV) = (Co−ΔC) × (Vo + ΔV) (7)
It becomes. And, by obtaining ΔV from the above equation (7),
ΔV = Vo × ΔC / Co (8)
It becomes.

  Therefore, when the capacitance c1 of the capacitor C1 and the capacitance c2 of the capacitor C2 are in the relationship of c1 = Co + ΔC and C1 = Co−ΔC (ΔC ≠ 0), the range of the charging voltage of the capacitor C1 by the charging current J1 is “Vo”. If the range of the charging voltage of the capacitor C2 by the charging current J2 is widened from “Vo” to “ΔV”, Q1 = Q2 and the modulation m is proportional to the amplitude of the audio signal Sin. Can do.

  The charging voltage range “Vo” is a charging voltage range when there is no difference between the capacitance c1 of the capacitor C1 and the capacitance c2 of the capacitor C2, that is, when ΔC = 0. In the conventional pulse width modulation circuit 101, This is a voltage corresponding to “Vref−Vlo”. In the conventional pulse width modulation circuit 101, this charging voltage range “Vref−Vlo” is the voltage at the connection points (A) and (C) of the capacitors C1 and C2 when the charging operation of the capacitors C1 and C2 is stopped. Vc1 and Vc2 are each clamped to a voltage Vhi to discharge all accumulated charges, and when the output levels of the comparators COMP2 and COMP1 are inverted to a high level (voltage Vhi), the connection points (a), ( The voltage Vc1, Vc2 (voltage at the start of charging) is set to the voltage Vlo.

  In order to narrow the range of the charging voltage of the capacitor C1 by “ΔV” from “Vo”, the voltage Vc1 at the connection point (A) of the capacitor C1 when the output level of the comparator COMP2 is inverted to the high level (voltage Vhi) is set. It is necessary to set to “Vlo + ΔV”. Similarly, in order to make the charging voltage range of the capacitor C2 wider by “ΔV” than “Vo”, the connection point (c) of the capacitor C2 when the output level of the comparator COMP1 is inverted to the high level (voltage Vhi) is set. It is necessary to set the voltage Vc2 to “Vlo−ΔV”.

  When all the accumulated charges in the capacitor C1 are discharged when the charging operation of the capacitor C1 is stopped, the voltage Vc1 at the connection point (A) is “Vlo” when the output level of the comparator COMP2 is inverted to the high level (voltage Vhi). Therefore, in order to set the voltage Vc1 at the connection point (a) at that time to “Vlo + ΔV”, the charge amount of the capacitor C1 is not discharged when the charging operation of the capacitor C1 is stopped. It can be seen that it is sufficient to leave q1 = c1 × ΔV. That is, a voltage Vk1 (hereinafter referred to as “clamp voltage Vk1”) that clamps the voltage Vc1 at the connection point (A) of the capacitor C1 when the charging operation of the capacitor C1 is stopped is higher than the voltage Vhi by ΔV ( It can be seen that Vhi + ΔV) may be set.

  Similarly, in order to set the voltage Vc2 at the connection point (c) when the output level of the comparator COMP1 is high (the voltage Vhi) to “Vlo−ΔV”, the charging operation of the capacitor C2 is stopped. It can be seen that it is sufficient to discharge all the accumulated charge of the capacitor C1 and accumulate the charge in the opposite direction by the amount of charge q2 = c2 × ΔV. That is, a voltage Vk2 (hereinafter referred to as “clamping voltage Vk2”) that clamps the voltage Vc2 at the connection point (c) of the capacitor C2 when the charging operation of the capacitor C2 is stopped is lower than the voltage Vhi by ΔV ( It can be seen that Vhi−ΔV) may be set.

Since the voltage ΔV is ΔV = Vo × ΔC / Co from the above equation (8), the clamp voltage Vk1 at the connection point (A) of the capacitor C1 and the clamp voltage Vk2 at the connection point (C) of the capacitor C2 is
Vk1 = Vhi + ΔV
= Vhi + Vo × ΔC / Co (9)
Vk2 = Vhi-ΔV
= Vhi-Vo × ΔC / Co (10)
It becomes. Furthermore, from Co = (c1 + c2) / 2, ΔC = (c1−c2) / 2, Vo = Vref−Vlo,
ΔV = (Vref−Vlo) × (c1−c2) / (c1 + c2) (11)
Therefore, the clamp voltages Vk1 and Vk2 are
Vk1 = Vhi + ΔV
= Vhi + (Vref-Vlo) * (c1-c2) / (c1 + c2) (12)
Vk1 = Vhi-ΔV
= Vhi- (Vref-Vlo) * (c1-c2) / (c1 + c2) (13)
It becomes.

  Therefore, in the pulse width modulation circuit 1 shown in FIG. 1, a circuit that clamps the connection points (a) and (c) of the capacitors C1 and C2 to the voltage Vlo by the diodes D1 and D2 is compared with the pulse width modulation circuit 101. By changing to the bypass circuit 4, the connection point (a) of the capacitor C1 is clamped to the clamp voltage Vk1 by the transistor Tr3 in the current bypass circuit 4 and the semi-fixed resistor TR1, and the transistor Tr4 in the current bypass circuit 4 and the semi-fixed resistor TR2 Thus, the connection point (c) of the capacitor C2 is clamped to the clamp voltage Vk2.

  Next, the circuit configuration of the pulse width modulation circuit 1 shown in FIG. 1 will be briefly described.

  The voltage-current conversion circuit 2 is a circuit that converts an audio signal Sin (voltage signal) into two currents J1 and J2 using a differential amplifier circuit. The voltage-current conversion circuit 2 has the same circuit configuration as the voltage-current conversion circuit 102 of the pulse width modulation circuit 101 shown in FIG.

  The voltage-current conversion circuit 2 is composed of a differential amplifier circuit in which the emitters of a pair of pnp transistors Tr1 and Tr2 having the same characteristics are connected to a constant current source 21 through emitter resistors Re. When the constant current supplied from the constant current source 21 is “2 × Io”, the voltage-current conversion circuit 2 charges the charging current J1 = Io−i of the capacitor C1 from the collector of the transistor Tr1 (where i = Sin / ( 2 × Re), and the charging current J2 = Io + i of the capacitor C2 is output from the collector of the transistor Tr2.

  The astable multivibrator circuit 103 charges the two capacitors C1 and C2 with the charging currents J1 and J2, respectively, thereby modulating two PWM signals Spwm, the pulse width (high period width) of which are modulated by the amplitude of the audio signal Sin. This circuit outputs / Spwm from two inverters INV1 and INV2, respectively. The output terminal of the inverter INV1 is connected to the input terminal of the inverter INV2 via the capacitor C2, and the output terminal of the inverter INV2 is connected to the input terminal of the inverter INV1 via the capacitor C1. Furthermore, the input terminal (connection point (A)) of the inverter INV1 and the input terminal (connection point (C)) of the inverter INV2 are connected to the collector of the transistor Tr1 and the collector of the transistor Tr2 of the voltage-current conversion circuit 2, respectively. .

  A pair of drive voltages (upper drive voltage “Vhi” and lower drive voltage “Vlo”) are supplied to the inverters INV1 and INV2, respectively. The inverters INV1 and INV2 have an output voltage at a high level of the drive voltage when the input voltage is equal to or higher than the threshold voltage Vth, and an output voltage at the low level of the drive voltage when the input voltage is lower than the threshold voltage Vth. Is a logic circuit. By controlling the input voltage of the inverter INV1, the output voltage of the inverter INV1 is switched between the voltage Vhi and the voltage Vlo and performs the same function as the comparator COMP1. Therefore, the inverter INV1 is used instead of the comparator COMP1 in FIG. ing. Similarly, by controlling the input voltage of the inverter INV2, the output voltage of the inverter INV2 is switched between the voltage Vhi and the voltage Vlo and performs the same function as the comparator COMP2. Therefore, in FIG. 1, instead of the comparator COMP2, the inverter INV2 is used.

  The threshold voltage Vth of the inverters INV1 and INV2 corresponds to the reference voltage Vref input to the positive input terminal of the comparator COMP1. The threshold voltage Vth of the inverters INV1 and INV2 is Vth≈ (Vhi + Vlo) / 2 because it is substantially at the center of the drive voltage range.

  Therefore, when the voltage Vc1 at the connection point (A) is increased from the voltage (Vlo + ΔV) by charging the capacitor C1 with the charging current J1, the inverter INV1 is at the high level (as long as the output voltage is lower than the threshold voltage Vth). The voltage Vhi) is reached (see the voltage waveforms (a) and (b) at t1 to t2 in FIG. 2), and when it becomes equal to or higher than the threshold voltage Vth, an operation to become a low level (voltage Vlo) is performed.

  On the other hand, when the voltage Vc2 at the connection point (c) is increased from the voltage (Vlo−ΔV) by charging the capacitor C2 with the charging current J2, the inverter INV2 is high while the output voltage is lower than the threshold voltage Vth. When the voltage reaches the level (voltage Vhi) (see voltage waveforms (c) and (d) at t2 to t3 in FIG. 2) and becomes the threshold voltage Vth or higher, the operation is performed to become the low level (voltage Vlo).

  The current bypass circuit 4 bypasses the charging current J1 and charges the capacitor C1 when the charging voltage Vc1 (voltage at the connection point (A)) of the capacitor C1 by the charging current J1 rises to the threshold voltage Vth of the inverter INV2. At the same time, the voltage Vc1 at the connection point (A) is clamped to the above-mentioned clamp voltage Vk1, and the charging voltage Vc2 (voltage at the connection point (C)) of the capacitor C2 by the charging current J2 is the threshold voltage Vth of the inverter INV1. In this circuit, the charging current J2 is bypassed and charging of the capacitor C2 is stopped, and the voltage Vc2 at the connection point (c) is clamped to the clamp voltage Vk2.

  The current bypass circuit 4 includes a first bypass circuit that bypasses the charging current J1 and a second bypass circuit that bypasses the charging current J2, and the first bypass circuit is configured by a pnp transistor Tr3 and a semi-fixed resistor TR1. The second bypass circuit is constituted by a pnp transistor Tr4 and a semi-fixed resistor TR2.

  The transistor Tr3 in the first bypass circuit has an emitter and a collector connected to a connection point (A) and a driving power supply (power supply that supplies the voltage Vlo) below the inverters INV1 and INV2, respectively, and a base that is a semi-fixed resistor. It is connected to the movable terminal of TR1. The transistor Tr4 in the second bypass circuit has an emitter and a collector connected to a connection point (c) and a driving power supply (power supply that supplies the voltage Vlo) below the inverters INV1 and INV2, respectively, and a base that is a semi-fixed resistor. It is connected to the movable terminal of TR2.

  The semi-fixed resistor TR1 and the semi-fixed resistor TR2 are connected in parallel. One connection point is connected to the driving power supply (power supply supplying the voltage Vlo) below the inverters INV1 and INV2, and the other connection point is a resistor. The voltage-current conversion circuit 2 is connected to a driving power supply (power supply for supplying the voltage Vcc) via R1.

  The semi-fixed resistor TR1 and the semi-fixed resistor TR2 have resistors that have substantially the same characteristic that the resistance value linearly changes with the movement of the movable terminal. The movable terminal and the semi-fixed resistor of the semi-fixed resistor TR1 There is provided a resistance adjusting mechanism in which the movable terminal of TR2 moves in conjunction with each resistor so that the moving directions are opposite to each other. That is, when the movable terminal of the semi-fixed resistor TR1 is moved downward by ΔR from the center position of the resistor of the semi-fixed resistor TR1, the movable terminal of the semi-fixed resistor TR2 becomes the resistance of the semi-fixed resistor TR2. If the movable terminal of the semi-fixed resistor TR2 is moved upward by ΔL from the center position of the resistor, the semi-fixed resistor TR1 is moved downward by ΔL from the center position of the resistor of the semi-fixed resistor TR2. Is provided with a resistance adjusting mechanism that moves upward by ΔL from the center position of the resistor of the semi-fixed resistor TR1.

Accordingly, the resistance values of the semi-fixed resistors TR1 and TR2 are set to “2R”, the movable amount of the movable terminal is set to “2L”, and for example, the movable terminal of the semi-fixed resistor TR1 is moved downward by ΔL from the center position of the resistor. When adjusted to the shifted position, the resistance value R1 of the movable terminal of the semi-fixed resistor TR1 is R1 = R × (L−ΔL) / L, and the resistance value R2 of the movable terminal of the semi-fixed resistor TR2 is R2 = R ×. (L + ΔL) / L. In this case, if the voltage supplied to both ends of the resistors of the semi-fixed resistors TR1 and TR2 is “2Vr”, the voltage of the movable terminal of the semi-fixed resistor TR1, that is, the base voltage Vr1 of the transistor Tr3 is
Vr1 = 2Vr * R1 / 2R = Vr * (L- [Delta] L) / L
= Vr−Vr × ΔL / L (14)
The voltage of the movable terminal of the semi-fixed resistor TR2, that is, the base voltage Vr2 of the transistor Tr4 is
Vr2 = Vr × R2 / 2R = Vr × (L + ΔL) / L
= Vr + Vr × ΔL / L (15)
It becomes.

The resistance values R1 and R2 of the movable terminals of the semi-fixed resistors TR1 and TR2 are adjusted when the pulse width modulation circuit 1 is manufactured. After the adjustment, the movable terminals are locked and the resistance values R1 and R2 are fixed.
The

The resistance values R1 and R2 of the semi-fixed resistors TR1 and TR2 are adjusted so that the voltages of the emitters of the transistor Tr3 and the transistor Tr4 become the clamp voltage Vk1 and the clamp voltage Vk2. When the voltage between the base and the emitter of the transistor Tr3 is “Vbe”, the base voltage of the transistor Tr3 adjusted by the semi-fixed resistor TR1 is “Vr1”, so that the emitter voltage of the transistor Tr3 is (Vr1 + Vbe). Since this emitter voltage is adjusted to “Vk1” shown in the equation (9), the base voltage Vr1 of the transistor Tr3 adjusted by the semi-fixed resistor TR1 from Vbe + Vr1 = Vhi + Vo × ΔC / Co is
Vr1 = Vhi−Vbe + Vo × ΔC / Co (16)
It becomes. Since “Vbe” is smaller than “Vhi”, if “Vbe” is ignored in equation (16) and the lower drive voltage Vlo of the inverters INV1 and INV2 is set to “0”, the transistor The base voltage Vr1 of Tr3 is
Vr1 = Vhi + Vhi × ΔC / Co (16 ′)
= Vhi + Vhi * (c1-c2) / (c1 + c2)
It becomes.

Similarly, when the voltage between the base and the emitter of the transistor Tr4 is “Vbe”, the voltage of the movable terminal after the resistance adjustment of the semi-fixed resistor TR2 is “Vr2”. Therefore, the emitter voltage of the transistor Tr4 is (Vr2 + Vbe). ) Since this emitter voltage is adjusted to “Vk2”, the voltage Vr2 of the movable terminal after the resistance adjustment of the semi-fixed resistor TR2 is calculated from Vbe + Vr1 = Vhi−Vo × ΔC / Co.
Vr2 = Vhi−Vbe−Vo × ΔC / Co (17)
It becomes. If “Vbe” is ignored in equation (17) and the lower drive voltage Vlo of the inverters INV1 and INV2 is set to “0”, the base voltage Vr2 of the transistor Tr4 is
Vr2 = Vhi−Vhi × ΔC / Co (17 ′)
= Vhi-Vhi * (c1-c2) / (c1 + c2)
It becomes.

According to the above equations (16 ′) and (17 ′), when c1 = c2, Vr1 = Vr2 = Vhi and when the movable terminals of the semi-fixed resistors TR1 and TR2 are adjusted to the center position of the resistor Since the voltages Vr1 and Vr2 are Vr1 = Vr2 = Vr, if the voltage supplied to both ends of the resistors of the semi-fixed resistors TR1 and TR2 is set to “2Vhi”, the voltage of the semi-fixed resistor TR1 When the movable terminal is adjusted to a position shifted by ΔL downward from the center position of the resistor, the voltage Vr1 of the movable terminal is
Vr1 = Vhi−Vhi × ΔL / L (18)
The voltage Vr2 at the movable terminal of the semi-fixed resistor TR2 is
Vr2 = Vhi + Vhi × ΔL / L (19)
It becomes.

  Vhi × ΔL / L in the equations (18) and (19) indicates that the voltage Vhi is divided at a ratio of ΔL / L by moving the movable terminal of the semi-fixed resistor TR1 by ΔL from the center position of the resistor. Vhi × (c1−c2) / (c1 + c2) = Vhi × ΔC / Co in the equations (16 ′) and (17 ′), the voltage Vhi is the capacitance difference 2ΔC = c1−c2 between the capacitor C1 and the capacitor C2. Since it is shown that the voltage is divided at a ratio to the sum Co = c1 + c2 of both capacitors, shifting the movable terminal of the semi-fixed resistor TR1 by ΔL from the center position of the resistor causes the voltage Vhi to be ΔC / Co. Corresponds to partial pressure.

  Therefore, the clamp voltage Vk1 can be easily and accurately changed from the voltage Vhi to Vhi × ΔC / Co by a resistance adjusting mechanism that slides the movable terminal of the semi-fixed resistor TR1 and the movable terminal of the semi-fixed resistor TR2 in opposite directions. It can be seen that the voltage can be adjusted to a voltage (Vhi−Vhi × ΔC / Co) decreased by a certain amount, and can be adjusted to a voltage (Vhi + Vhi × ΔC / Co) obtained by increasing the clamp voltage Vk2 from the voltage Vhi by Vhi × ΔC / Co.

Note that Vr1−Vr2 = 2 × Vhi × ΔC / Co = 2 × between the voltages Vr1 and Vr2 of the movable terminals after adjusting the semi-fixed resistors TR1 and TR2 and the capacitances c1 and c2 of the capacitors C1 and C2. From Vhi × (c1-c2) / (c1 + c2)
(Vr1-Vr2) / 2Vhi = (c1-c2) / (c1 + c2) (20)
There is a relationship.

  In the operation of adjusting the position of the movable terminal of the semi-fixed resistor TR1 or the movable terminal of the semi-fixed resistor TR2 and setting the appropriate voltages Vr1 and Vr2, for example, the pulse width modulation circuit is set so that the audio signal Sin is in the non-signal state. When the signals demodulated from the PWM signals Spwm and / Spwm output from 1 are monitored, if the voltages Vr1 and Vr2 are inappropriate, a DC offset component is output. The position may be adjusted. Alternatively, the position of the movable terminal may be adjusted so that the High period T1 and the Low period T2 become the same while monitoring the waveform of the PWM signal Spwm or PWM signal / Spwm output from the inverter INV1 or the inverter INV2.

  When the base voltage Vr1 of the transistor Tr3 is adjusted by the semi-fixed resistor TR1 as shown in the equation (14), when the charging of the capacitor C1 is started by the charging current J1, the voltage Vc1 at the connection point (A) is the inverter. Since the threshold voltage Vth of INV1 is lower and the emitter voltage of the transistor Tr3 is lower than the base voltage Vr1, the transistor Tr3 is in the OFF state. When the capacitor C1 is charged by the charging current J1, the voltage Vc1 at the connection point (A) rises and reaches the threshold Vth of the inverter INV1, the output level of the inverter INV1 is inverted to the low level Vlo. The output level is inverted to the voltage Vhi.

  When the output level of the inverter INV2 becomes the voltage Vhi, the voltage Vc1 at the connection point (A) jumps to a level (Vhi + Vth−Vlo) larger than the clamp voltage Vk1, so that the transistor Tr3 is turned on and the charging current J1 is The transistor Tr3 is bypassed to the power supply side of the lower voltage Vlo of the inverter INV1, the charging operation of the capacitor C1 is stopped, and the accumulated charge of the capacitor C1 is discharged through the transistor Tr3.

  When the voltage Vc1 at the connection point (A) decreases to Vk1 = Vbe + Vr1 due to the discharge of the accumulated charge in the capacitor C1, the transistor Tr3 is turned off, and the voltage Vc1 at the connection point (A) is held at the clamp voltage Vk1. It will be.

  When the base voltage Vr1 of the transistor Tr4 is adjusted by the semi-fixed resistor TR2 as shown in the equation (15), when the charging of the capacitor C2 is started by the charging current J2, the voltage Vc2 at the connection point (C) is the inverter. Since the threshold voltage Vth of INV2 is lower and the emitter voltage of the transistor Tr4 is lower than the base voltage Vr2, the transistor Tr4 is in the OFF state. When the capacitor C2 is charged by the charging current J2, the voltage Vc2 at the connection point (c) rises, and when the threshold Vth of the inverter INV2 is reached, the output level of the inverter INV2 is inverted to the low level Vlo. The output level is inverted to the voltage Vhi.

  When the output level of the inverter INV1 becomes the voltage Vhi, the voltage Vc2 at the connection point (c) jumps to a level (Vhi + Vth−Vlo) larger than the clamp voltage Vk2, so that the transistor Tr4 is turned on and the charging current J2 is The transistor Tr4 is bypassed to the power supply side of the drive voltage Vlo below the inverter INV2, the charging operation of the capacitor C2 is stopped, and the accumulated charge of the capacitor C2 is discharged via the transistor Tr4.

  When the voltage Vc2 at the connection point (c) is reduced to Vk2 = Vbe + Vr2 due to the discharge of the accumulated charge of the capacitor C2, the transistor Tr4 is turned off, and the voltage Vc2 at the connection point (c) is held at the clamp voltage Vk2. It will be.

  If the capacitors C1 and C2 are ideal and their capacitances are almost the same, the term of Vhi × ΔC / Co is zero in the above equations (16) and (17), so that Vr1 = Vr2 = Vhi Become. That is, the resistance values R1, R2 of the semi-fixed resistors TR1, TR2 are adjusted to R1 = R2 = R. In this case, the transistors Tr3 and Tr4 clamp the voltages Vc1 and Vc2 at the connection point (b) of the capacitor C1 and the connection point (c) of the capacitor C2 to the voltage Vhi when charging is stopped, respectively, and the transistors Tr3 and Tr4 are npn. Since the current flows only in the direction from the emitter to the base, the current bypass action is the same as that of the diodes D1 and D2 of the pulse width modulation circuit 101 in FIG.

  Next, the operation of the pulse width modulation circuit 1 will be described using the waveform diagram of FIG.

  The waveform diagram shown in FIG. 2 corresponds to the waveform diagram shown in FIG. 8. Compared to FIG. 8, the clamp voltage (for example, t2) after the charging of the voltage waveforms at the connection points (A) and (B) is stopped. (See (b) voltage during period t3 and (c) voltage during period t1 to t2) and voltages at connection points (a) and (c) at the start of charging (for example, (c) at timing t2) And the voltage of (b) at the timing of t3) are different.

  Therefore, in the following description, the operation of the pulse width modulation circuit 1 will be described focusing on the above differences.

  When the input level of the inverter INV2 reaches the threshold voltage Vth of the inverter INV2 at the timing t1 and the output level is inverted to the low level Vlo (see voltage waveform (d)), the charging of the capacitor C1 by the charging current J1 is performed. Since the output level of the inverter INV1 is inverted to the high level Vhi at the timing of t1 (refer to the voltage waveform in (B)), the voltage Vc2 at the connection point (C) is Since this jumps to (Vhi + Vth−Vlo), the transistor Tr4 in the current bypass circuit 4 is turned on, and the charging current J2 is bypassed by the transistor Tr4 to the power supply side of the lower drive voltage Vlo of the inverter INV2, and the capacitor C2 Is stopped, and the charge stored in the capacitor C2 is transferred to the transistor Tr4. It is discharged through.

  When the voltage Vc2 at the connection point (c) is reduced to Vk2 = Vbe + Vr2 due to the discharge of the accumulated charge of the capacitor C2, the transistor Tr4 is turned off, and the voltage Vc2 at the connection point (c) is the clamp voltage Vk2 shown in the equation (10). = Vhi−ΔV (refer to the voltage waveform in the period from t1 to t2 in (c)).

  If the clamp voltage Vk2 is Vk2 = Vhi, the charge stored in the capacitor C2 is zero, but since the clamp voltage Vk2 is Vk2 = Vhi-ΔV, the capacitor C2 is further charged in the opposite direction, and q2 = c2 × ΔV Are stored until the next charge start.

Since ΔV is ΔV = Vo × ΔC / Co = (Vhi−Vlo) × (c1−c2) / (c1 + c2) from the equation (8), the amount of charge q2 accumulated in the capacitor C2 is
q2 = c2 * (Vhi-Vlo) * (c1-c2) / (c1 + c2) (21)
It is.

  When charging of the capacitor C1 is started at the timing t1, the voltage Vc1 at the connection point (A) increases at a speed (waveform slope) corresponding to the charging current J1. Note that the switching frequency is set sufficiently higher than the fundamental frequency of the audio signal Sin, and the change in the charging current J1 during the charging period is minute, so that the voltage at the connection point (A) rises almost linearly. . The output level of the inverter INV1 is maintained at the high level Vhi while the voltage Vc1 at the connection point (A) is lower than the threshold voltage Vth of the inverter INV1, but the voltage Vc1 at the connection point (A) at the timing t2. When the voltage reaches the threshold voltage Vth of the inverter INV1, it is inverted to the low level Vlo (refer to the voltage waveform in (B)). When the output level of the inverter INV1 is inverted to the low level Vlo, the voltage Vc2 at the connection point (c) changes to (Vlo−ΔV), and charging of the capacitor C2 by the charging current J2 is started (voltage waveform of (c)). reference).

  On the other hand, when the voltage Vc2 at the connection point (c) changes to (Vlo−ΔV) at the timing t2, the output level of the inverter INV2 is inverted to the high level Vhi (refer to the voltage waveform in (d)). At this time, the voltage Vc1 at the connection point (A) jumps to (Vhi + Vth−Vlo), so that the transistor Tr3 in the current bypass circuit 4 is turned on, and the charging current J1 is applied to the lower side of the inverter INV1 by the transistor Tr3. Bypassing to the power supply side of the drive voltage Vlo, the charging operation of the capacitor C1 is stopped, and the accumulated charge of the capacitor C1 is discharged through the transistor Tr3.

  When the voltage Vc1 at the connection point (A) decreases to Vk1 = Vbe + Vr1 due to the discharge of the accumulated charge of the capacitor C1, the transistor Tr3 is turned off, and the voltage Vc1 at the connection point (A) is the clamp voltage Vk1 shown in the equation (9). = Vhi + ΔV (refer to the voltage waveform in the period from t1 to t2 in (a)).

If the clamp voltage Vk1 is Vk1 = Vhi, the accumulated charge of the capacitor C1 becomes zero. However, since the clamp voltage Vk1 is Vk1 = Vhi + ΔV, the capacitor C1 is discharged until a charge of q1 = c1 × ΔV remains. The charge remains until the next charge starts. Since ΔV is ΔV = Vo × ΔC / Co = (Vhi−Vlo) × (c1−c2) / (c1 + c2) from the equation (8), the amount of charge q1 accumulated in the capacitor C1 is
q1 = c1 * (Vhi-Vlo) * (c1-c2) / (c1 + c2) (22)
It is.

  When charging of the capacitor C2 is started at the timing t2, the voltage Vc2 at the connection point (c) increases at a speed (waveform slope) corresponding to the charging current J2. Note that the change in the charging current J2 during the charging period is as small as the charging current J1, so the voltage at the connection point (c) rises almost linearly. The output level of the inverter INV2 is maintained at the high level Vhi while the voltage Vc2 at the connection point (c) is lower than the threshold voltage Vth of the inverter INV2, but the voltage Vc2 at the connection point (c) at the timing of t3. When the voltage reaches the threshold voltage Vth of the inverter INV2, it is inverted to the low level Vlo (see the voltage waveform in (d)).

Since the capacitor C2 is charged by the charging current J2 from the voltage (Vlo−ΔV) to the threshold voltage Vth of the inverter INV1, the charging time T2 is
T2 = (Vth−Vlo + ΔV) × c2 / J2
= (Vo + ΔV) × c2 / J2 (23)
It becomes.

  When the output level of the inverter INV2 is inverted to the low level Vlo at the timing of t3 (refer to the voltage waveform in (d)), the voltage Vc1 at the connection point (A) changes to the voltage (Vlo + ΔV), and the capacitor C1 due to the charging current J1 Charging is started (see voltage waveform in (a)). When charging of the capacitor C1 is started, the voltage Vc1 at the connection point (A) rises linearly at a speed (waveform slope) corresponding to the charging current J1, but is lower than the threshold voltage Vth of the inverter INV1. During this time, the output level of the inverter INV1 is held at the high level Vhi, and when the voltage Vc1 at the connection point (A) reaches the threshold voltage Vth of the inverter INV2 at the timing t4, the output level of the inverter INV1 becomes the low level Vlo. Inverted (see voltage waveform in (b)).

Since the capacitor C1 is charged by the charging current J1 from the voltage (Vlo + ΔV) to the threshold voltage Vth of the inverter INV2, the charging time T1 is
T1 = (Vth−Vlo−ΔV) × c1 / J1
= (Vo-ΔV) × c1 / J1 (24)
It becomes.

  Thereafter, the charging operation of the capacitor C2 in the period from t2 to t3 and the charging operation of the capacitor C1 in the period from t3 to t4 are alternately repeated, and the charging period T1 of the capacitor C1 is set to the High period from the output terminal of the inverter INV1. PWM signal Spwm with the charging time T2 of the capacitor C2 as the low period is output, and the PWM terminal with the charging period T2 of the capacitor C2 as the high period and the charging time T1 of the capacitor C1 as the low period from the output terminal of the inverter INV2. The signal / Spwm is output.

From c1 = Co + ΔC, c2 = Co−ΔC, ΔV = Vo × ΔC / Co, (Vo−ΔV) = Vo × (Co−ΔC) / Co = Vo × c2 / Co, (Vo + ΔV) = Vo × (Co + ΔC ) / Co = Vo × c1 / Co, so if these are substituted into the above equations (23) and (24), T1 = (c2 × c1 / Co) × (Vo / J1), T2 = (c1) * C2 / Co) * (Vo / J2), T1-T2 = (Vo * c1 * c2 / Co) * (1 / J1-1 / J2), T1 + T2 = (Vo * c1 * c2 / Co) * (1 / J1 + 1 / J2), the modulation degree m is
M = | T1-T2 | / | T1 + T2 |
= | J1-J2 | / | J1 + J2 |
= I / Io = Sin / S
Needless to say, this is proportional to the amplitude of the audio signal Sin.

  As described above, according to the pulse width modulation circuit 1 according to the first embodiment, the clamp voltage Vk1 of the capacitor C1 after charging is different from the clamp voltage Vk2 of the capacitor C2, and the capacitance value c1 of the capacitors C1 and C2 is set. , C2 so that the clamp voltages Vk1, Vk2 are set so as to satisfy the above expression (12), (13) or (20), the capacitance values c1, c2 differ depending on the individual difference between the capacitors C1, C2. Even in this case, there is an effect that the modulation degree can be accurately proportional to the amplitude of the audio signal Sin.

  Therefore, when the audio signal Sin is silent, a DC offset component is not included in the demodulated signals of the PWM signals Spwm and / Spwm.

  In the first embodiment, the current bypass circuit 4 uses the npn transistors Tr3 and Tr4 to bypass the charging currents J1 and J2, and the voltages Vc1 and Vc2 at the connection points (A) and (B) are clamped to the clamp voltages Vk1 and Vk2, respectively. However, as shown in FIG. 3, a current bypass circuit 4 ′ that applies clamp voltages Vk1 and Vk2 to the cathodes of the diodes D1 and D2 via the voltage followers 41 and 42 may be used.

  In the current bypass circuit 4 ′ shown in FIG. 3, the anodes of the diodes D1 and D2 are connected to the connection points (A) and (B), respectively, and the cathode of the diode D1 is connected to the semi-fixed resistor TR1 via the voltage follower 41. The voltage Vr1 of the movable terminal is input, and the voltage Vr2 of the movable terminal of the semi-fixed resistor TR2 is input to the cathode of the diode D2 via the voltage follower 42.

In the first embodiment, since the inverters INV1 and INV2 are used, the threshold voltage Vth is at a level approximately between the upper drive voltage Vhi and the lower drive voltage Vlo. When the lower drive voltage Vlo is set to “0”, Vo = Vth = Vhi / 2. Therefore, when this is substituted into the above equations (9) and (10), the clamp voltages Vk1 and Vk2 are
Vk1 = Vhi + Vhi × ΔC / 2Co
= Vhi + (Vhi / 2) * (c1-c2) / (c1 + c2) (9 ')
Vk2 = Vhi−Vhi × ΔC / 2Co
= Vhi- (Vhi / 2) * (c1-c2) / (c1 + c2) (10 ')
It becomes.

  Therefore, when the lower drive voltage Vlo of the inverters INV1 and INV2 is set to “0” in the pulse width modulation circuit 1 ′ of FIG. 3, if the forward voltage of the diodes D1 and D2 is ignored, the current bypass circuit 4 ′ The voltage Vr1 of the movable terminal of the semi-fixed resistor TR1 is set to the clamp voltage Vk1 shown in the equation (9 ′), and the voltage Vr1 of the movable terminal of the semi-fixed resistor TR2 is set to the clamp voltage Vk2 shown in the equation (10 ′). Is set.

  In the current bypass circuit 4 ′, ignoring the forward voltages of the diodes D1 and D2, when the voltage Vc1 at the connection point (A) exceeds the voltage Vr1, the diode D1 becomes conductive and the charging current J1 is moved to the voltage follower 41 side. Bypassing and stopping the charging operation of the capacitor C1, the voltage Vc1 at the connection point (A) is clamped to the voltage Vr1. Similarly, when the voltage Vc2 at the connection point (c) exceeds the voltage Vr2, the diode D2 becomes conductive, the charging current J2 is bypassed to the voltage follower 42 side, and the charging operation of the capacitor C2 is stopped. The voltage Vc2 in (c) is clamped to the voltage Vr2.

  Therefore, the pulse width modulation circuit 1 ′ shown in FIG. 3 can achieve the same operations and effects as the pulse width modulation circuit 1 shown in FIG. 1.

  FIG. 4 is a diagram showing a basic configuration of a second embodiment of a pulse width modulation circuit using an astable multivibrator circuit according to the present invention. FIG. 5 is a diagram showing waveforms of voltages at the connection points (A) to (D) during the operation of the pulse width modulation circuit according to the second embodiment.

  The pulse width modulation circuit 1 according to the first embodiment shown in FIG. 1 is configured to charge charges so that the capacitors C1 and C2 are raised from the lower voltage Vlo ± ΔV to the threshold voltage Vth of the inverters INV1 and INV2. However, the pulse width modulation circuit 1 ′ according to the second embodiment shown in FIG. 4 lowers the capacitors C1 and C2 from the upper voltage Vhi ± ΔV to the threshold voltage Vth of the inverters INV1 and INV2. The circuit is configured to discharge electric charges.

The pulse width modulation circuit 1 ′ shown in FIG. 4 is drawn upside down with respect to the pulse width modulation circuit 1 shown in FIG.
(1) One connection point (e) of the semi-fixed resistors TR1 and TR2 is connected to the drive power supply (power supply for supplying the voltage Vhi) on the upper side of the inverters INV1 and INV2. (2) Connected to the constant current source 21. The power supply is changed to “Vss” (<Vlo), and the other connection point (f) of the semi-fixed resistors TR1 and TR2 is connected to the power supply Vss via the resistor R1. (3) The transistors Tr1 to Tr4 are npn type. The difference is that it is a transistor. Since the power source connected to the constant current source 21 is “Vss” (<Vlo), the current direction of the constant current source 21 and the directions of the charging currents J1 and J2 are different from those of the pulse width modulation circuit 1 of FIG. Vice versa.

  As described above, the circuit configuration of the pulse width modulation circuit 1 ′ according to the second embodiment is basically the same as that of the pulse width modulation circuit 1 according to the first embodiment, and the polarity of the power supply voltage is reversed between positive and negative. Accordingly, the type of the transistors Tr1 to Tr4 only changes to the npn type, so that the description of the circuit configuration is omitted, and the operation of the pulse width modulation circuit 1 ′ is simply described using the waveform diagram of FIG. .

  When the input level of the inverter INV2 reaches the threshold voltage Vth at the timing t1 (refer to the voltage waveform (c)) and the output level is inverted to the high level Vhi (refer to the voltage waveform (d)), the charging current J1 Charging of the capacitor C1 is started (see the voltage waveform in (A)), but the output level of the inverter INV1 is inverted to the low level Vlo at the timing of t1 (see the voltage waveform in (B)). ) Voltage Vc2 tends to decrease to Vth− (Vhi−Vlo), which turns on the transistor Tr4 in the current bypass circuit 4, and the charge accumulated in the capacitor C2 is discharged through the transistor Tr4. The

  When the voltage Vc2 at the connection point (c) rises to Vk2 = Vr2-Vbe due to the discharge of the capacitor C2, the transistor Tr4 is turned off, and the voltage Vc2 at the connection point (c) is held at the clamp voltage Vk2 = Vlo + ΔV ( (Refer to voltage waveforms in the period from t1 to t2 in (c)).

  When charging of the capacitor C1 is started at the timing t1, the voltage Vc1 at the connection point (A) drops almost linearly at a speed (waveform slope) corresponding to the charging current J1. The output level of the inverter INV1 is maintained at the low level Vlo while the voltage Vc1 at the connection point (A) is higher than the threshold voltage Vth of the inverter INV1, but the voltage Vc1 at the connection point (A) at the timing of t2. When the voltage reaches the threshold voltage Vth of the inverter INV1, it is inverted to the high level Vhi (refer to the voltage waveform in (b)). When the output level of the inverter INV1 is inverted to the high level Vhi, the voltage Vc2 at the connection point (c) changes to (Vhi + ΔV), and charging of the capacitor C2 by the charging current J2 is started (see voltage waveform in (c)). .

  On the other hand, when the voltage Vc2 at the connection point (c) changes to (Vhi + ΔV) at the timing t2, the output level of the inverter INV2 is inverted to the low level Vlo (see the voltage waveform in (d)). At this time, the voltage Vc1 at the connection point (A) tends to be reduced to Vth− (Vhi−Vlo). As a result, the transistor Tr3 in the current bypass circuit 4 is turned on, and the charge accumulated in the capacitor C1 is reduced. It is discharged via the transistor Tr3.

  When the voltage Vc1 at the connection point (A) rises to Vk1 = Vr1−Vbe by charging the capacitor C1, the transistor Tr3 is turned off, and the voltage Vc1 at the connection point (A) is held at the clamp voltage Vk1 = Vlo−ΔV. (Refer to the voltage waveform during the period from t1 to t2 in (a)).

  When charging of the capacitor C2 is started at the timing t2, the voltage Vc2 at the connection point (c) drops almost linearly at a speed (waveform slope) corresponding to the charging current J2. The output level of the inverter INV2 is maintained at the low level Vlo while the voltage Vc2 at the connection point (c) is higher than the threshold voltage Vth of the inverter INV2, but the voltage Vc2 at the connection point (c) at the timing t3. When the voltage reaches the threshold voltage Vth of the inverter INV2, it is inverted to the high level Vhi (see voltage waveform (d)).

Since the capacitor C2 is charged by the charging current J2 from the voltage (Vhi + ΔV) to the threshold voltage Vth of the inverter INV1, the discharge time T2 is
T2 = (Vhi + ΔV−Vth) × c2 / J2
It becomes.

  When the output level of the inverter INV2 is inverted to the high level Vhi at the timing of t3 (see the voltage waveform in (d)), the voltage Vc1 at the connection point (b) changes to the voltage (Vhi−ΔV), and the capacitor by the charging current J1 Charging of C1 is started (see the voltage waveform in (A)). When charging of the capacitor C1 is started, the voltage Vc1 at the connection point (A) drops almost linearly at a speed (waveform slope) corresponding to the charging current J1, but is lower than the threshold voltage Vth of the inverter INV1. While the voltage is high, the output level of the inverter INV1 is held at the low level Vlo. When the voltage Vc1 at the connection point (A) reaches the threshold voltage Vth of the inverter INV2 at the timing t4, the output level of the inverter INV1 is increased to the high level Vhi. (Refer to the voltage waveform in (b)).

Since the capacitor C1 is charged by the charging current J1 from the voltage (Vhi−ΔV) to the threshold voltage Vth of the inverter INV2, the charging time T1 is
T1 = (Vhi−ΔV−Vth) × c2 / J2
It becomes.

  Thereafter, the charging operation of the capacitor C2 during the period from t2 to t3 and the charging operation of the capacitor C1 during the period from t3 to t4 are alternately repeated, and the charging period T1 of the capacitor C1 is set to the low period from the output terminal of the inverter INV1. PWM signal Spwm with the charging time T2 of the capacitor C2 as the high period is output, and the PWM terminal with the charging period T2 of the capacitor C2 as the low period and the charging time T1 of the capacitor C1 as the high period from the output terminal of the inverter INV2. The signal / Spwm is output.

  As described above, even in the pulse width modulation circuit 1 ′ according to the second embodiment, similarly to the pulse width modulation circuit 1 according to the first embodiment, even when the capacitance values c1 and c2 are different due to individual differences between the capacitors C1 and C2. There is an effect that the modulation degree can be accurately proportional to the amplitude of the audio signal Sin.

  Further, when the audio signal Sin is silent, a DC offset component is not included in the demodulated signals of the PWM signals Spwm and / Spwm.

  In the second embodiment, the circuit configuration using the diode and the voltage follower shown in FIG. 3 as the current bypass circuit 4 can be applied.

  Note that the scope of the present invention is not limited to the above-described embodiment, and the circuit configuration shown in the above-described embodiment is an example, and various circuits can be applied as long as they have equivalent functions. be able to.

1, 1 'Pulse width modulation circuit 2 Voltage-current conversion circuit 21 Constant current source 3 Astable multivibrator circuit 4 Current bypass circuit C1 capacitor (first charge storage circuit)
C2 capacitor (second charge storage circuit)
INV1 inverter (first logic circuit)
INV2 inverter (second logic circuit)
D1 Current bypass diode (first discharge circuit)
D2 Current bypass diode (second discharge circuit)
TR1, TR2 Semi-fixed resistors Tr1-Tr4 Transistors Vth Inverter threshold voltage (first reference level)

Claims (4)

A voltage-current for converting a voltage signal whose level fluctuates in a predetermined level fluctuation range into two current signals having a current value obtained by dividing a predetermined constant current value by a ratio indicating the position of the level in the level fluctuation range. A conversion circuit;
A first logic circuit that operates in an inverse relationship between an input level and an output level;
A second logic circuit having the same configuration as the first logic circuit;
The first current output from the voltage-current conversion circuit is connected between the output terminal of the second logic circuit and the input terminal of the first logic circuit, and is input to the first logic circuit. A first charge storage circuit supplied as a charging current from a connection point between
The second current output from the voltage-current conversion circuit is connected between the output terminal of the first logic circuit and the input terminal of the second logic circuit, and the input terminal of the second logic circuit. A second charge storage circuit supplied as a charging current from a connection point between
When the input level of the first logic circuit reaches a predetermined threshold level in the charging operation of the first charge storage circuit by the first current, connected to the input terminal of the first logic circuit, the first logic circuit A first discharge for connecting the input terminal of one logic circuit to a first variable voltage power supply to stop the charging operation of the first charge storage circuit and discharging the stored charge of the first charge storage circuit Circuit,
The second logic circuit is connected to the input terminal of the second logic circuit, and when the input level of the second logic circuit reaches the threshold level in the charging operation of the second charge storage circuit by the second current, the second logic circuit A second discharge circuit for connecting the input terminal of the logic circuit to a second variable voltage power supply to stop the charging operation of the second charge storage circuit and discharging the stored charge of the second charge storage circuit And a first pulse width modulation signal whose pulse width is modulated by the amplitude of the voltage signal is output from the output terminal of the first logic circuit, and the first logic circuit outputs the first pulse width modulation signal from the output terminal of the second logic circuit. A pulse width modulation circuit that outputs a second pulse width modulation signal whose phase is inverted with respect to one pulse width modulation signal;
The voltage of the first variable voltage power supply and the voltage of the second variable voltage power supply are high when the amplitude of the voltage signal is zero, when the amplitude of the first pulse width modulation signal or the second pulse width modulation signal is high. A pulse width modulation circuit, wherein the level period and the low level period are set to be the same.   When the first and second variable voltage power supplies change the voltage value of the first variable voltage power supply, the voltage value of the second variable voltage power supply is interlocked with and reverse to the first variable voltage power supply. Voltage adjusting means that changes at the same rate in the direction, and by adjusting the voltage of the first variable voltage power supply or the second variable voltage power supply by the voltage adjusting means, the voltages of both variable power supplies The pulse width modulation circuit according to claim 1, wherein the pulse width modulation circuit is adjusted. The first variable voltage power source includes a first semi-fixed resistor that outputs a voltage obtained by dividing a predetermined power source voltage, and the second variable voltage power source is in parallel with the first semi-fixed resistor. A second semi-fixed resistor connected to output a voltage obtained by dividing the power supply voltage;
The movable terminal that outputs the divided voltage of the first semi-fixed resistor and the movable terminal that outputs the divided voltage of the second semi-fixed resistor are interlocked in opposite directions. The voltage of the first variable voltage power supply and the second variable voltage are adjusted by adjusting the fixed position of one of the movable terminals of the first and second semi-fixed resistors. The pulse width modulation circuit according to claim 2, wherein the voltage of the power supply is set.   4. The pulse width modulation circuit according to claim 1, wherein the first logic circuit and the second logic circuit are configured by inverters driven by the same power source. 5.

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