JP5437986B2 - Folding circuit and analog / digital conversion circuit - Google Patents

Description

  The present invention relates to a folding circuit and an analog / digital conversion circuit, and more particularly to a folding circuit and an analog / digital conversion circuit used in an optical communication system.

  In recent years, verification of transmission formats with high spectrum utilization efficiency has been actively conducted toward further increase in capacity of optical communication systems. Examples of such transmission formats include PSK (Phase Shift Keying) that gives information to the phase of light, ASK (Amplotude Shift Keying) that gives information to the amplitude of light, or information to both the phase and amplitude. There are QAM (Quadrature Amplitude Modulation), etc., and DPSK (Differential Phase Shift Keying) and DQPSK (Differential Quadrature Phase Shift Keying), which modulate the phase of differential signals, are already in practical use. QPSK (Quadrature Phase Shift Keying) that is not used is in a state of practical use. Further, techniques for improving spectrum utilization efficiency (16QAM, (D) 8PSK, etc.) more than DQPSK and QPSK are being actively studied.

  DLI (Delay Line Interferometer), which extracts a binary signal directly from the modulated optical signal when demodulating an optical signal modulated by DPSK, which is binary phase modulation, or DQPSK, which is quaternary phase modulation, is known. However, in order to demodulate an optical signal modulated by further multi-level (for example, 8-level) phase modulation such as D8PSK, in addition to DLI, an analog-to-digital conversion circuit having a very high sample rate performance is required. Necessary. For example, when receiving one sample per symbol without polarization multiplexing, the sample rate performance required for the analog-to-digital conversion circuit when demodulating a 200 GHz / 16QAM modulation signal is 54 GS / s (gigasample per second). ) Is a high value.

  In addition, in order to cope with the increase in capacity in recent optical communication systems, when demodulating an optical signal modulated by multi-level phase modulation as described above, an analog / digital conversion circuit of the receiving apparatus has a high sample rate. In addition to the rate (for example, 50 GS / s or more), a performance that can achieve both high resolution (for example, 5 bits or more) is required.

Among various analog-to-digital conversion circuits that have been widely known, a flash-type analog-to-digital conversion circuit is available as an analog-to-digital conversion circuit that can realize a high sample rate (Patent Document 1). .
As an example, as shown in FIG. 16, a flash type analog-digital conversion circuit disclosed in Patent Document 1 includes a clock signal input terminal CLK31-1, an analog signal input terminal VIN35, and a reference voltage (top side) input terminal. VRT32-1, reference voltage (bottom side) input terminal VRB32-2, resistor ladder 32, clock distributor 31, voltage comparator 33 (33-1 to 33-7), encoder 34, digital signal output (D2 to D0) It comprises terminals 36-1 to 36-3.

The resistance ladder 32 has a reference voltage of 2 ⁿ −1 (n represents the number of bits of the digital signal output, and n = 3 in FIG. 16) obtained by dividing the reference voltage VRT and the reference voltage VRB. Generate and send to voltage comparator.
The voltage comparator 33 (33-1 to 33-7) inputs an analog input signal VIN to one input and one of 2 ⁿ −1 reference voltages generated by a resistor ladder to the other input. The comparison result is sent to the encoder 34.
The encoder 34 reads the output from the voltage comparator 33 as a thermometer code that is parallel data, converts the thermometer code into a binary code, and outputs 3-bit digital signals D2 to D0.
The clock distributor 31 distributes the clock signal CLK input from the clock signal input terminal 31-1 in the same phase, and sends the distributed clock signal CLK to the voltage comparator 33 and the encoder 34.
Such a flash type analog / digital conversion circuit has a feature that a relatively high sample rate is possible, while the circuit scale increases as the resolution when converting into a digital signal increases.

On the other hand, a folding type analog / digital conversion circuit is known as an analog / digital conversion circuit capable of making the circuit scale relatively small even when a high-resolution (multi-bit) signal is handled (non-conversion). Patent Document 1).
As an example, the folding type analog-digital conversion circuit disclosed in Non-Patent Document 1 includes a clock signal input terminal CLK41-1, an analog signal input terminal VIN46, and a reference voltage (top side) input as shown in FIG. Terminal VRT 43-1, reference voltage (bottom side) input terminal VRB 43-2, analog data distributor 42, clock distributor 41, upper bit analog-digital conversion circuit 43, folding circuit 44, encoder 45, digital signal output (D3-3) D0) terminals 47-1 to 47-4.

The folding type analog / digital conversion circuit shown in FIG. 17 includes an upper bit conversion analog / digital conversion circuit (upper bit analog / digital conversion circuit 43) and a lower bit conversion analog / digital conversion circuit (folding circuit 44). And the encoder 45) are operated together.
As shown in FIG. 17, the upper bit analog / digital conversion circuit 43 is a flash type analog / digital conversion circuit that converts the upper 3 bits of the digital signal corresponding to the analog signal input from the analog input terminal VIN46 into the above-described manner. Can be derived using.

As shown in FIG. 17, the folding circuit 44 and the encoder 45, which are analog / digital conversion circuits for lower bit conversion, derive a lower two bit signal of the digital signal corresponding to the analog signal input from the analog input terminal VIN46. To do.
The folding circuit 44 is a circuit that generates a folding signal (F2, F1) necessary for conversion of the lower 2 bits of the digital signal corresponding to the analog signal input from the analog input terminal VIN46. The folding signal (F1, F2) output from the folding circuit 44 has an output characteristic that is folded back with a voltage width smaller than the voltage corresponding to the least significant bit D2 output from the upper bit analog / digital conversion circuit 43. A conventional folding circuit that generates a folded signal having such output characteristics is generally an electronic circuit having a configuration in which a plurality of electric signal amplifiers are connected in parallel.

The encoder 45 derives the lower 2 bits (D1, D0) of the digital signal corresponding to the analog signal input from the analog input terminal VIN46 based on the folding signal (F1, F2).
Here, the relationship between the upper bits D3 and D2 of the digital signal output by the folding type analog-digital conversion circuit, the folding signals F1 and F2 output by the folding circuit, and the lower bits D1 and D0 of the digital signal As shown in FIG. As shown in FIG. 18, the lower bits D1 and D0 of the digital signal are output from the encoder based on the folding signals F1 and F2 output from the folding circuit.

  In such a folding type analog / digital conversion circuit, even when a high resolution (multi-bit (for example, 5 bits or more)) digital signal is output, the circuit scale is reduced as compared with a flash type analog / digital conversion circuit. On the other hand, the input load capacity increases due to the configuration characteristics of the folding circuit, so that the operation speed is lower than that of the flash type analog-digital conversion circuit.

JP 2009-267808 A

Michael P. Flynn and Ben Sheahan, “A 400-Msample / s, 6-b CMOS Folding and Interpolating ADC”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 12, DECEMBER 1998

  Therefore, in order to realize a higher sample rate, the flash-type analog-digital conversion circuit as disclosed in Patent Document 1 has a larger circuit scale to achieve higher resolution. In the folding type analog-digital conversion circuit as disclosed in Non-Patent Document 1, the operation speed of the folding circuit for lower-order bit conversion becomes a bottleneck as the high resolution is realized. It was.

Specifically, when dealing with high resolution (multi-bit (for example, 5 bits or more)) signals in conventional flash type and folding type analog / digital conversion circuits, the circuit scale of the flash type analog / digital conversion circuit is: However, there is a problem that the sampling rate is lowered due to an exponential increase, skew (timing shift) generated between signals of a huge circuit scale, and heat generation of circuit elements due to an increase in power consumption. .
On the other hand, in the conventional folding type analog-digital conversion circuit, the number of amplifiers used in the folding circuit increases as the signal after digital conversion becomes higher in resolution, so the input load capacity of the folding circuit increases. There was a problem that the operation of the system became slow and a high sample rate could not be realized.

  As a result, in the conventional analog-digital conversion circuit as described above, since there is a trade-off relationship between the sample rate and the resolution, it is required to cope with the increase in capacity in recent optical communication systems. It has been difficult to achieve both high resolution and higher sample rate.

  Therefore, in order to solve the above-described problem, the present invention relaxes the trade-off relationship between the sample rate and the resolution when demodulating the optical signal, and achieves both a high sample rate and a high resolution.・ The purpose is to realize digital conversion.

  In order to achieve the above-described object, the present invention includes a signal light distribution unit that distributes input signal light input from the outside to N (N is an integer) signal lights having equal light intensities in a folding circuit. A reference light distribution unit that distributes input reference light input from the outside to N reference lights having different light intensities according to a predetermined light intensity distribution ratio, and the N signal lights and N reference lights Each bit of the inverted thermometer code in which the N-bit thermometer code obtained by quantizing the light intensity of the input signal light is derived from the light intensity with the reference light, and the logic of the thermometer code is inverted every other bit. And a folding signal output unit that outputs a folding signal that is folded according to a change in the light intensity of the input signal light.

In addition, the reference light distribution unit according to the present invention has an optical distributor that distributes the input reference light to N light beams having the same light intensity, and has a different transmittance and is distributed by the light distributor. You may provide the N optical attenuator which attenuates the light intensity of N light to the light intensity according to the said distribution ratio, respectively.
In addition, the folding circuit according to the present invention may include a plurality of the reference light distribution units, and the plurality of reference light distribution units may have different distribution ratios.

  In the present invention, the folded signal output unit may calculate the light intensity of one of the N signal lights and the light intensity of one of the N reference lights. A comparison operation unit that compares and outputs the N-bit thermometer code corresponding to N comparison results, and inverts the logic of the thermometer code output by the comparison operation unit every other bit to perform the inversion You may provide the inversion operation part which outputs a thermometer code, and the addition operation part which adds each bit of the said inversion thermometer code output by this inversion operation part, and outputs an addition signal.

  In the present invention, the comparison calculation unit includes a first input terminal to which one of the N signal lights is input, and a second input to which one of the N reference lights is input. A first output terminal that outputs an electrical signal converted from the signal light input from the first input terminal, and a conversion from the reference light input from the second input terminal. N photoelectric converters having a second output terminal for outputting the electrical signal, and the potentials of the electrical signals output from the first and second output terminals of the photoelectric converter are compared. N comparators that output electrical signals according to the results, and the inversion operation unit includes an inverting output unit that inverts every other logic of the electrical signals output from the N comparators. One computing unit is provided by the inverting output device. By adding the N electrical signals that are inverted can be an adder for outputting the sum signal.

  Further, the comparison operation unit according to the present invention includes an optical interferometer that outputs one of N interference optical signals by interfering with one of the N signal lights and one of the N reference lights. The inversion operation unit includes an optical delay unit that generates a delayed interference optical signal by delaying every other phase of the N interference optical signals by 180 °, and the addition operation unit outputs from the optical delay unit An optical multiplexer that combines the N delayed interference optical signals to be output and outputs a combined optical signal, and a photoelectric converter that converts the combined optical signal output from the optical multiplexer into an electrical signal and outputs the electrical signal And may be provided.

  The present invention also provides an input signal light distributor that distributes the input signal light into two signal lights as an analog-digital conversion circuit that converts the input signal light input from the outside into a digital signal with a predetermined resolution. A photoelectric converter for converting one signal light distributed by the input signal light distributor into an electric signal; a clock distributor for distributing a predetermined clock signal to a plurality of predetermined sampling clock signals; and the sampling clock A voltage level of an electric signal output from the photoelectric converter in synchronization with a signal is compared with a reference voltage level input from the outside, and a signal of a predetermined upper bit of the digital signal based on the comparison result A high-order bit signal generation unit for generating the input signal light, the input reference light input from the outside, and the input signal light A folding circuit that generates a folding signal that folds back at a predetermined timing according to a variation in the degree, and a predetermined lower order of the digital signal based on the folding signal that is output from the folding circuit in synchronization with the sampling clock signal A lower bit signal generation unit for generating a bit signal, wherein the folding circuit is a folding circuit according to any one of claims 1 to 6, wherein the folding circuit is related to a resolution of the upper bit of the digital signal. The number of folding signals determined in accordance with the number of folding signals is generated in a number determined in relation to the resolution of the lower bits.

  The present invention also provides a sampling clock generator for outputting a predetermined sampling clock as an analog / digital conversion circuit for converting input signal light input from the outside into a digital signal having a predetermined resolution, and an input input from the outside. A folding circuit that inputs reference light and the input signal light and generates a folding signal that returns at a predetermined timing in accordance with fluctuations in light intensity of the input signal light, and outputs from the folding circuit in synchronization with the sampling clock An encoder for generating the digital signal corresponding to the input signal light based on the folded signal, wherein the folding circuit is the folding circuit according to any one of claims 1 to 6, The number of folding signals generated by the folding circuit Folding number, and wherein the determined connection with the resolution of the digital signal.

Also, the number of folding signals and the number of folding signals output from the folding circuit according to the present invention are expressed by a relational expression: Fs = 2 ^{(m + 1)} +1, Ft = 2 ⁿ / 2 (where Fs is the folding signal of the folding signal). Ft is the number of the folded signals, m is the number of bits of the upper bits of the digital signal, and n is the number of bits of the lower bits of the digital signal.

  According to the present invention, when an optical signal received by a receiving device is demodulated in an optical communication system, a folding circuit mounted on an analog / digital conversion circuit of the receiving device distributes an input optical signal and Even when converting to a digital signal with higher resolution by optically performing arithmetic processing using the light intensity in the optical signal, the folding circuit can be made faster than before without increasing the input load capacity of the folding circuit. It can be operated and a higher sample rate and a higher resolution can be achieved at the same time.

  Therefore, according to the present invention, the folding circuit that optically executes the arithmetic processing using the input optical signal relaxes the trade-off relationship between the sample rate and the resolution, thereby increasing the higher sample rate. It is possible to achieve analog / digital conversion with low power consumption while ensuring high resolution and suppressing an increase in circuit scale.

It is a figure which shows the structure of the folding circuit concerning the 1st Embodiment of this invention. It is a figure explaining an example of the output result of each element of the folding circuit concerning a 1st embodiment. It is a figure which shows an example of the folding signal output from the folding circuit concerning 1st Embodiment. It is a figure explaining the structure of a folding circuit at the time of providing multiple reference light splitters. It is a figure which shows the structure of the folding circuit concerning the 2nd Embodiment of this invention. It is a figure explaining an example of the output result of each element of the folding circuit concerning 2nd Embodiment. It is a figure which shows the structure of the folding circuit concerning the 3rd Embodiment of this invention. It is a figure explaining an example of the output result of each element of the folding circuit concerning 3rd Embodiment. It is a figure which shows the structure of the folding circuit concerning the 4th Embodiment of this invention. It is a figure explaining an example of the output result of each element of the folding circuit concerning 4th Embodiment. It is a figure which shows the structure of the analog / digital conversion circuit concerning the 5th Embodiment of this invention. It is a figure explaining the relationship between the folding | turning number of the folding signal output from the folding circuit in an analog-digital conversion circuit, and the parallel number, and digital signal D2, D1, D0 after A / D conversion. It is a figure which shows an example of an encoder output (truth table). It is a figure which shows the structure of the analog / digital conversion circuit concerning the 6th Embodiment of this invention. It is a figure which shows an example of the encoder output (truth table) based on the folding signal output from the folding circuit of the analog-digital conversion circuit concerning 6th Embodiment. It is a figure which shows the structure of a flash type analog-digital conversion circuit. It is a figure which shows the structure of a folding type | mold analog-digital conversion circuit. The figure explaining the relationship between the high-order bits D3 and D2 of the digital signal output by the folding type analog-digital conversion circuit, the folding signals F1 and F2 output by the folding circuit, and the low-order bits D1 and D0 of the digital signal It is.

Embodiments of the present invention will be described below with reference to the drawings.
[First Embodiment]
The folding circuit according to the first embodiment of the present invention optically executes arithmetic processing using the light intensities of the input signal light and the input reference light, thereby performing analog-to-digital conversion (hereinafter referred to as “A / This is referred to as “D conversion”) to output a folded signal used when the input signal light is converted into a digital signal.
FIG. 1 shows the configuration of the folding circuit according to this embodiment, and FIG. 2 shows an example of the output result of each element of the folding circuit according to this embodiment. Hereinafter, the configuration and function of the folding circuit 100 according to the present embodiment will be described in detail with reference to FIGS.

As shown in FIG. 1, the folding circuit 100 according to the present embodiment includes a signal light distribution unit 110, a reference light distribution unit 120, and a folding signal output unit 130.
The signal light distribution unit 110 distributes the input signal light 1 input from the outside into n signal lights (n is an integer) having the same light intensity.
In the present embodiment, as shown in FIG. 2, the light intensity of the input signal light 1 is represented by “0” to “50” as the light intensity level, and “10” is changed in steps. The signal light distribution unit 110 distributes the signal light into five signal lights having the same light intensity according to the light intensity level of the input signal light 1.
Specifically, as shown in FIG. 2, when the light intensity level of the input signal light 1 is “50”, the signal light distribution unit 110 sets the light intensity levels of the input signal light 1 equal to each other. Since the signal light is distributed to the five signal lights, the five signal lights having the light intensity level “10” are output. Similarly, the signal light distribution unit 110 outputs five signal lights whose light intensity level is “8” when the light intensity level of the input signal light 1 is “40”, and the light intensity level of the input signal light 1 is “30”. Then, five signal lights having a light intensity level of “6” are output.

The reference light distribution unit 120 distributes the input reference light 2 input from the outside to n reference lights having different light intensities according to a predetermined light intensity distribution ratio.
In the present embodiment, as shown in FIG. 2, the light intensity of the input reference light 2 is represented by “25” as the light intensity level, and the light intensity level of the input reference light 2 is constant. The reference light distribution unit 120 sets the light intensity level “25” of the input reference light 2 to the light intensity levels of “9”, “7”, “5”, “3”, “1” with a predetermined distribution ratio. It distributes to the five reference beams that it has.

The return signal output unit 130 is a light of n signal lights distributed from the input signal light 1 by the signal light distribution unit 110 and n reference lights distributed from the input reference light 2 by the reference light distribution unit 120. An n-bit signal obtained by quantizing the input signal light 1 (hereinafter referred to as “thermometer code”) is derived from the intensity, and a signal (hereinafter referred to as “the thermometer code”) in which the logic of each bit of the thermometer code is alternately inverted. A signal representing the sum of each bit of “inverted thermometer code”) is output as a signal that is turned back in response to a change in the light intensity of the input signal light 1 (hereinafter referred to as a “turn-back signal”).
The folding signal output unit 130 in the present embodiment includes a comparison calculation unit 131, an inversion calculation unit 132, and an addition calculation unit 133.

  The comparison operation unit 131 includes a first input terminal to which one of n signal lights is input, a second input terminal to which one of n reference lights is input, and a first input. A first output terminal that outputs an electrical signal converted from the signal light input to the terminal; and a second output terminal that outputs an electrical signal converted from the reference light input to the second input terminal. The potentials of the electric signals output from the first output terminal and the second output terminal of each of the n photoelectric converters 131-11 to 131-1n and the photoelectric converters 131-11 to 131-1n are compared. The n comparators 131-21 to 131-2n each output an electrical signal corresponding to the comparison result.

In the present embodiment, the comparison operation unit 131 uses the potential of the electrical signal converted from the signal light output from the photoelectric converters 131-11 to 131-1n and the electrical signal converted from the reference light as the comparator 131-. 21 to 131-2n, and an n-bit thermometer code corresponding to n comparison results is output.
Specifically, the comparators 131-21 to 131-2 n set “1” when the potential of the electrical signal converted from the signal light is larger than the potential of the electrical signal converted from the reference light, and when the potential is smaller Outputs an n-bit thermometer code by outputting “0”.

  For example, as shown in FIG. 2, when the light intensity level of the input signal light 1 is “50” and the light intensity level of the input reference light 2 is “25”, the five signals output by the signal light distribution unit 110 The light intensity levels of the lights are equal to each other, “10”, and the light intensity levels of the five reference lights output by the reference light distribution unit 120 are “9”, “7”, “5”, “3”, “1”.

The five signal lights and reference lights having such light intensity levels are converted into electric signals having potentials corresponding to the light intensity levels by the photoelectric converters 131-11 to 131-15, respectively, and comparators 131-21 to 131- 25, the electric signal potentials are respectively compared.
That is, the photoelectric converter 131-11 converts the signal light having the light intensity level “10” and the reference light having the light intensity level “9” into an electric signal having a potential corresponding to each light intensity level, 131-11 compares the electric signal converted from the signal light having the light intensity level “10” and the electric signal converted from the reference light having the light intensity level “9”.

  At this time, since the electric signal potential converted from the signal light is higher than the electric signal potential converted from the reference light, the comparator 131-11 outputs “1”. Similarly, the photoelectric converters 131-12 to 131-15 and the comparators 131-22 to 131-25 compare the potentials of the remaining four signal lights and electrical signals converted from the reference light, and output the comparison results. . As a result, as shown in FIG. 2, the comparison operation unit 131 outputs a 5-bit thermometer code “1, 1, 1, 1, 1”.

The inversion operation unit 132 outputs an inverted thermometer code obtained by inverting the logic of the thermometer code output by the comparison operation unit 131 every other bit.
In the present embodiment, the inversion operation unit 132 is configured by an inversion output device that alternately inverts the logic of signals output from the n comparators 131-21 to 131-2 n. For example, as illustrated in FIG. 2, when the light intensity level of the input signal light 1 is “50”, the thermometer codes output from the comparators 131-21 to 131-25 of the comparison calculation unit 131 are “1, 1, The inversion operation unit 132 alternately inverts the logic of each bit of the thermometer code and outputs the inverted thermometer code “1, 0, 1, 0, 1”.

The addition operation unit 133 adds each bit of the inversion thermometer code output by the inversion operation unit 132 and outputs an addition signal.
In the present embodiment, the addition operation unit 133 is configured by an adder that adds the signals of the respective bits of the inverted thermometer code output by the inverting output unit included in the inverting operation unit 132 and outputs the addition result. .

For example, as shown in FIG. 2, when the light intensity level of the input signal light 1 is “50”, the inversion thermometer code output from the inversion operation unit 132 is “1, 0, 1, 0, 1”. The addition operation unit 133 outputs an addition signal representing “3” obtained by adding the values of the respective bits of the inverted thermometer code. Further, when the light intensity level of the input signal light 1 is “40”, the addition operation unit 133 adds “2”, which is obtained by adding the values of the respective bits of the inverted thermometer code “0, 0, 1, 0, 1”. The addition signal representing is output.
Therefore, when the light intensity level of the input signal light 1 varies from “0” to “50”, the addition signal output from the addition operation unit 133 of the folding signal output unit 130 varies in the light intensity level of the input signal light 1. Accordingly, the value changes repeatedly as “2 → 3 → 2 → 3 → 2 → 3”. Here, the relationship between the addition signal output from the addition operation unit 133 and the fluctuation of the light intensity of the input signal light is shown in FIG. As shown in FIG. 3, the added signal has an output characteristic in which the output is folded back (repeated) between 2 and 3 as the light intensity of the input signal varies.

  From the above, the folding signal output unit 130 of the folding circuit 100 according to the present embodiment digitally converts the input signal light by the A / D conversion, that is, the signal whose output changes according to the input characteristics of the input signal light 1. A loopback signal used for conversion to a signal is output.

Further, in the present embodiment, when outputting a plurality of folding signals, the folding circuit 100 includes a plurality of reference light distribution units 120 and outputs the folding signals as many as the number of reference light distribution units 120 mounted. Further, the plurality of reference light distribution units 120 have different light intensity distribution ratios.
FIG. 4 is a diagram for explaining the configuration of the folding circuit when two folding signals are output. With reference to FIG. 4, the configuration of the folding circuit when outputting a plurality of folding signals will be described below.

As shown in FIG. 4, the folding circuit that outputs two folding signals includes two reference light distribution units 120-1 and 120-2. The two reference light distribution units 120-1 and 120- 2 have different light intensity distribution ratios.
Specifically, the light intensity level of the input reference light 2-1 input to the reference light distribution unit 120-1 is “25”, and the reference light 120-1 a to 120-1 distributed by the reference light distribution unit 120-1. The light intensity levels of 120-1e are “9”, “7”, “5”, “3”, and “1” in descending order. On the other hand, the light intensity level of the input reference light 2-2 input to the reference light distribution unit 120-2 is “20”, and the reference lights 120-2a to 120-2e distributed by the reference light distribution unit 120-2. The light intensity levels are “8”, “6”, “4”, “2”, “0” in descending order of level.

  The return signal output unit 130 compares the light intensities of the reference lights 120-1a to 120-1e output from the reference light distributor 120-1 and the signal lights 110a to 110e output from the signal light distributor 110. The first folding signal output unit 130-1 that outputs the folding signal F1 in the above, the reference beams 120-2a to 120-2e that are output from the reference beam distribution unit 120-2, and the signal that is output from the signal beam distribution unit 110 A second folding signal output unit 130-2 that outputs the folding signal F2 by comparing the light intensities of the lights 110a to 110e is provided, and the two folding signals F1 and F2 are output simultaneously.

  In this way, when outputting a plurality of folding signals, the distribution number of the input signal light and the light intensity of the input reference light in the folding circuit are changed, and the configurations of the reference light distribution unit and the folding signal output unit are made plural. Thus, the folding circuit can output a plurality of folding signals simultaneously.

As described above, according to the present embodiment, the input signal light and the input reference light are distributed in the state of an optical signal, and optical calculation processing is performed using the light intensity of the distributed signal light and reference light. By executing this, it is possible to output a folded signal whose output is folded according to the input characteristics of the input signal light.
Therefore, the folding circuit according to the present embodiment for distributing the optical signal can operate at a high speed without increasing the input load capacity as compared with the folding circuit using the conventional electronic circuit.

  Therefore, when demodulating an optical signal received by a receiving device in an optical communication system, the trade-off relationship between the sample rate and the resolution is relaxed, and both a high sample rate and a high resolution can be achieved. It is possible to realize A / D conversion with low power consumption while suppressing an increase.

[Second Embodiment]
The folding circuit according to the second embodiment of the present invention is a light that equally distributes the light intensity of the input reference light to the configuration of the reference light distributor 120 of the folding circuit 100 described in the first embodiment. A distributor and a light attenuator for attenuating the light intensity of the reference light with a predetermined transmittance are provided.

  FIG. 5 shows a configuration of the folding circuit according to the present embodiment, and FIG. 6 shows an example of an output result of each element of the folding circuit according to the present embodiment. Hereinafter, the configuration and function of the folding circuit 200 according to the present embodiment will be described in detail with reference to FIGS. In addition, the same code | symbol is attached | subjected to what has the same structure and function as the component of the folding circuit 100 demonstrated in 1st Embodiment, and the detailed description is abbreviate | omitted.

  As shown in FIG. 5, the folding circuit 200 according to this embodiment includes a signal light distribution unit 110 that distributes the input signal light 1 into n signal lights having the same light intensity, and the input reference light 2. A reference light distribution unit 220 that distributes the light to n reference lights having different light intensities, and outputs according to fluctuations in the light intensity of the input signal light 1 using the light intensities of the distributed signal light and reference light. The loopback signal output unit 130 outputs a loopback signal to be looped back.

Further, the folding signal output unit 130 outputs a comparison result of the light intensity comparison between the n signal lights and the reference light, and an n-bit indicating the light intensity comparison result between the signal light and the reference light. An inversion operation unit 132 that outputs an inverted thermometer code obtained by alternately inverting the logic of each bit of the thermometer code, and an addition operation unit 133 that adds the values of the respective bits of the inverted thermometer code and outputs an addition signal; And outputs a folded signal whose output is folded according to the input characteristics of the input signal light 1.
When outputting a plurality of folding signals, the number of distributions of the input signal light and the light intensity of the input reference light in the folding circuit are changed, and the configurations of the reference light distribution unit and the folding signal output unit are made plural. A plurality of return signals can be obtained simultaneously.

Here, the reference light distribution unit 220 will be described in detail.
As shown in FIG. 5, the reference light distributor 220 includes an optical distributor 221 and optical attenuators 222-1 to 222-n.
The light distributor 221 distributes the input reference light 2 into n pieces of light having the same light intensity.
The optical attenuator 222 attenuates the n lights output from the optical distributor 221 with a transmittance that becomes a light intensity determined by a predetermined light intensity distribution ratio, and outputs n reference lights. To do.

In the present embodiment, as shown in FIG. 6, the light intensity level of the input reference light 2 is “50” and is constant, and the reference light distribution unit 220 outputs five reference lights.
In such a case, the light distributor 221 distributes the input reference light 2 into five lights having the same light intensity level, and thus outputs five lights having a light intensity level of “10”.
The optical attenuator 222 converts the five light beams having the light intensity level “10” output from the optical distributor 221 into attenuation ratios “9/10”, “7/10”, “5/10”, “3/10”. ”And“ 1/10 ”and output as five reference lights having predetermined light intensity levels“ 9 ”,“ 7 ”,“ 5 ”,“ 3 ”, and“ 1 ”.

As described above, according to the present embodiment, the input reference light is distributed to n lights having the same light intensity, and then attenuated to a predetermined light intensity by an optical attenuator having a predetermined attenuation factor. By outputting a single reference light, the distribution ratio of the light intensity of the reference light can be set flexibly.
Therefore, it is possible to flexibly construct a folding circuit that outputs a plurality of folding signals.

[Third Embodiment]
In the folding circuit according to the third embodiment of the present invention, an optical interference device, an optical delay device, and an optical multiplexer are used as the folding signal output unit 130 of the folding circuit 100 described in the first embodiment. The configuration is such that the optical signal is used up to the previous stage of outputting the folding signal.

  FIG. 7 shows the configuration of the folding circuit according to the present embodiment, and FIG. 8 shows an example of the output result of each element of the folding circuit according to the present embodiment. Hereinafter, the configuration and function of the folding circuit 300 according to the present embodiment will be described in detail with reference to FIGS. In addition, the same code | symbol is attached | subjected to what has the same structure and function as the component of the folding circuit 100 demonstrated in 1st Embodiment, and the detailed description is abbreviate | omitted.

  As shown in FIG. 5, the folding circuit 300 according to this embodiment includes a signal light distribution unit 110 that distributes the input signal light 1 into n signal lights having the same light intensity, and the input reference light 2. A reference light distribution unit 120 that distributes the light to n reference lights having different light intensities, and outputs according to fluctuations in the light intensity of the input signal light 1 using the light intensities of the distributed signal light and reference light. The loopback signal output unit 330 outputs a loopback signal to be looped back.

  The return signal output unit 330 is a light of n signal lights distributed from the input signal light 1 by the signal light distribution unit 110 and n reference lights distributed from the input reference light 2 by the reference light distribution unit 120. An addition signal obtained by deriving an n-bit thermometer code obtained by quantizing the input signal light 1 from the intensity, and adding the value of each bit of the inverted thermometer code obtained by alternately inverting the logic of each bit of the thermometer code Is output as a folding signal that is folded according to the change in the light intensity of the input signal light 1.

The folding signal output unit 330 in the present embodiment includes a comparison operation unit 331, an inversion operation unit 332, and an addition operation unit 333.
The comparison calculation unit 331 includes one of the n signal lights distributed from the input signal light 1 by the signal light distribution unit 110 and the n reference lights distributed from the input reference light 2 by the reference light distribution unit 120. Are interfering with one of the optical interferors to output n interference optical signals.

  Here, the interference light signal output from the optical interferometer corresponds to a subtraction result of the light intensity of the signal light and the reference light input to the optical interferometer. Therefore, although the interference optical signal output from the optical interferometer cannot be a binary digital signal, in this embodiment, for convenience, the interference optical signal output from the optical interferometer is input. It is assumed that “1” is represented when the light intensity of the signal light is greater than the light intensity of the input reference light, and “0” is represented when the signal light is small. That is, the following description will be made assuming that n interference light signals are n-bit thermometer codes.

An optical interferometer (hereinafter, referred to as “optical interferometer 331”) that constitutes the comparison operation unit 331 generates n interfering optical signals obtained by causing n signal lights and reference light to interfere with each other by n bits. Is output as a thermometer code.
For example, as shown in FIG. 8, when the light intensity level of the input signal light 1 is “50” and the light intensity level of the input reference light 2 is “25”, five signals output by the signal light distributor 110. The light intensity levels of the lights are equal to each other, “10”, and the light intensity levels of the five reference lights output by the reference light distribution unit 120 are “9”, “7”, “5”, “3”, “1”.
The optical interferometer 331 causes the five signal lights and the reference light having such light intensity levels to interfere with each other, and compares the magnitude relationship between the light intensity level of the signal light and the light intensity level of the reference light. Output the total code.

  Specifically, the interferometer 331 refers to the signal light with the light intensity level “10” and the reference light with the light intensity level “9”, the signal light with the light intensity level “10”, and the reference with the light intensity level “7”. Light, signal light having a light intensity level of “10”, reference light having a light intensity level of “5”, signal light having a light intensity level of “10”, reference light having a light intensity level of “3”, and light intensity level of “10” ”And the reference light having the light intensity level“ 1 ”are interfered with each other to compare the light intensity levels, and five interference light signals as comparison results are output. As a result, as shown in FIG. 2, the comparison operation unit 331 outputs a 5-bit thermometer code “1, 1, 1, 1, 1”.

Inversion operation unit 332 in the present embodiment includes an optical delay device that outputs a delayed interference optical signal obtained by delaying every other phase of n interference optical signals output from optical interferometer 331 by 180 °. .
For example, as shown in FIG. 8, when the light intensity level of the input signal light 1 is “50”, the five interference light signals output from the optical interferometer 331, that is, the thermometer code is “1, 1, 1, 1 ”and the optical delay device constituting the inversion operation unit 332 (hereinafter referred to as“ optical delay device 332 ”) has five interference signal lights corresponding to each bit of the thermometer code. Five delayed interference signals having the phase delayed by 180 ° every other phase are output. That is, the optical delay device 332 outputs the inverted thermometer code “1, 0, 1, 0, 1” obtained by inverting the logic of the thermometer code every other bit by outputting five delayed interference signals. To do.

The addition operation unit 333 in the present embodiment multiplexes the n delayed interference optical signals output from the optical delay 332 and outputs a combined optical signal, and an optical multiplexer 333- and a photoelectric converter 333-b that converts the combined optical signal output from a into an electrical signal and outputs the electrical signal.
For example, as shown in FIG. 8, when the light intensity level of the input signal light 1 is “50”, the optical multiplexer 333-a outputs the inverted thermometer code “1, 0, 1, Five delayed interference optical signals corresponding to each bit of “0, 1” are combined, and a combined optical signal corresponding to “3” obtained by adding the values of the respective bits of the inverted thermometer code is output.
When the light intensity level of the input signal light 1 is “40”, the optical multiplexer 333-a adds the value of each bit of the inverted thermometer code “0, 0, 1, 0, 1”. The combined optical signal corresponding to “2” is output.

The photoelectric converter 333-b converts the combined optical signal output from the optical combiner 333-a into an electrical signal and outputs the electrical signal.
As described above, when the light intensity level of the input signal light 1 varies from “0” to “50”, the electrical signal output from the photoelectric converter 333-b is accompanied by the variation in the light intensity level of the input signal light 1. The value changes repeatedly as “2 → 3 → 2 → 3 → 2 → 3”.
From the above, the folding signal output unit 330 of the folding circuit 300 according to the present embodiment outputs a folding signal whose output changes (repetitively) according to the input characteristics of the input signal light 1.
When outputting a plurality of folding signals, the number of distributions of the input signal light and the light intensity of the input reference light in the folding circuit are changed, and the configurations of the reference light distribution unit and the folding signal output unit are made plural. A plurality of return signals can be obtained simultaneously.

  As described above, according to the present embodiment, a configuration of a folding circuit that eliminates the need for a plurality of electric amplifiers is realized by executing optical arithmetic processing using an optical signal up to a stage before outputting a folding signal. can do. Therefore, it is possible to increase the operation speed as compared with the folding circuit described in the first and second embodiments.

[Fourth Embodiment]
The folding circuit according to the fourth embodiment of the present invention is a light that equally distributes the light intensity of the input reference light to the configuration of the reference light distributor 120 of the folding circuit 300 described in the third embodiment. A distributor and a light attenuator for attenuating the light intensity of the reference light with a predetermined transmittance are provided.

  FIG. 9 shows the configuration of the folding circuit according to the present embodiment, and FIG. 10 shows an example of the output result of each element of the folding circuit according to the present embodiment. Hereinafter, the configuration and function of the folding circuit 400 according to the present embodiment will be described in detail with reference to FIGS. In addition, the same code | symbol is attached | subjected to what has the same structure and function as the component of the folding circuit 300 demonstrated in 3rd Embodiment, and the detailed description is abbreviate | omitted.

  As shown in FIG. 9, the folding circuit 400 according to the present embodiment includes a signal light distribution unit 110 that distributes the input signal light 1 into n signal lights having the same light intensity, and the input reference light 2 to each other. A reference light distribution unit 420 that distributes to n reference lights having different light intensities, and an output according to a change in the light intensity of the input signal light 1 using the light intensities of the distributed signal light and reference light. The loopback signal output unit 330 outputs a loopback signal that is looped back and forth.

The aliasing signal output unit 330 includes a comparison operation unit (optical interferometer) 331 that outputs n interference light signals by causing n signal lights and reference light to interfere with each other, and a phase of the n interference light signals. And an inversion operation unit (optical delay unit) 332 that outputs an inverted interference optical signal that is delayed by 180 ° every other, and a combined optical signal obtained by combining n inverted interference optical signals is converted into an electrical signal and output. The addition operation unit 333 is configured to output a return signal whose output changes back according to the input characteristics of the input signal light 1.
When outputting a plurality of folding signals, the number of distributions of the input signal light and the light intensity of the input reference light in the folding circuit are changed, and the configurations of the reference light distribution unit and the folding signal output unit are made plural. Two or more return signals can be obtained simultaneously.

Here, the reference light distribution unit 420 will be described in detail.
As shown in FIG. 9, the reference light distribution unit 420 includes an optical distributor 421 and optical attenuators 422-1 to 422-n.
The light distributor 421 distributes the input reference light 2 into n light beams having the same light intensity.
The optical attenuator 422 attenuates the n lights output from the optical distributor 421 with a transmittance that becomes a light intensity determined by a predetermined light intensity distribution ratio, and outputs n reference lights. To do.

In the present embodiment, as shown in FIG. 10, the light intensity level of the input reference light 2 is represented by “50”, and the level is constant.
In such a case, the light distributor 421 distributes the light intensity level of the input reference light 2 to five lights having the same light intensity level, and thus outputs five lights having a light intensity level of “10”. To do.
The optical attenuator 422 converts the five light beams having the light intensity level “10” output from the optical distributor 421 into attenuation ratios “9/10”, “7/10”, “5/10”, “3/10”. ”And“ 1/10 ”, and five reference lights having predetermined light intensity levels“ 9 ”,“ 7 ”,“ 5 ”,“ 3 ”, and“ 1 ”are output.

As described above, according to the present embodiment, the input reference light is distributed to n lights having the same light intensity, and then attenuated to a predetermined light intensity by an optical attenuator having a predetermined attenuation factor. Since one reference light is used, the distribution ratio of the light intensity of the reference light can be set flexibly.
Therefore, compared to the folding circuit described in the third embodiment, the configuration of the folding circuit that outputs a plurality of folding signals can be flexibly constructed.

[Fifth Embodiment]
An analog / digital conversion circuit according to a fifth embodiment of the present invention converts an optical signal input from the outside into a digital signal having a predetermined resolution, and converts the optical signal to a predetermined higher order of the digital signal. Folding analog / digital that operates together with an analog / digital conversion circuit for high-order bit conversion that converts to a bit, and a folding circuit and encoder for low-order bit conversion that converts an optical signal into a predetermined low-order bit of a digital signal It is a conversion circuit.

FIG. 11 is a diagram showing a configuration of the analog / digital conversion circuit according to the present embodiment.
As shown in FIG. 11, the analog / digital conversion circuit 10 according to the present exemplary embodiment includes a clock distributor 11, an optical distributor 12, a photoelectric converter 13, an upper bit analog / digital conversion circuit 14, and a folding. The circuit 15 and the encoder 16 are included.

The clock distributor 11 distributes a predetermined clock signal (CLK) 11-1 to a plurality of predetermined sampling clocks.
In this embodiment, as shown in FIG. 11, the clock distributor 11 distributes the input CLK 11-1 to two sampling clocks CLKa and CLKb having the same frequency and the same phase, and CLKa will be described later. CLKb is output to the higher-order bit analog / digital conversion circuit 14 and the encoder 16 described later.

The optical distributor 12 distributes the input signal light 1 to the two input signal lights 1-a and 1-b, and distributes the distributed one input signal light 1-a to the photoelectric converter 13 described later and the other input signal. The light 1-b is output to a folding circuit 15 described later.
The photoelectric converter 13 converts one input signal light 1-a distributed by the optical distributor 12 into an electric signal VINa, and outputs the electric signal VINa to an upper bit analog / digital conversion circuit 14 to be described later.

The upper bit analog / digital conversion circuit 14 compares the voltage level of VINa output from the photoelectric converter 13 in synchronization with CLKa with the voltage levels of the reference voltages VRT14-1 and VRB14-2 input from the outside. The high order bits of the digital signal based on the comparison result are generated and output.
In the present embodiment, as shown in FIG. 11, it is assumed that the input signal light is converted into a 5-bit digital signal (D4, D3, D2, D1, D0) by A / D conversion. The circuit 14 generates and outputs the upper 3 bits digital signal (D4, D3, D2) of the 5 bits digital signal.
As such an upper bit analog-digital conversion circuit 14, for example, a flash type analog-digital conversion circuit which is a conventional technique can be used.

The holding circuit 15 receives the input reference light 2 input from the outside and the other input signal light 1-b distributed by the optical distributor 12 as input, and changes the light intensity of the input truth light 1-b. In response, a return signal is generated that returns the output at a predetermined timing.
The encoder 16 generates and outputs lower bits of the digital signal based on the folding signal output from the folding circuit 15 in synchronization with CLKb.
In the present embodiment, as described above, since the input signal light is converted into a 5-bit digital signal by A / D conversion, the folding circuit 15 and the encoder 16 have the lower two of the 5-bit digital signals. Bit digital signals (D1, D0) are generated and output.

Here, the folding circuit 15 of the analog / digital conversion circuit 10 according to the present embodiment will be described in detail with reference to FIGS.
The folding circuit 15 in the present embodiment has the same configuration as that of any of the folding circuits 100 to 400 described in the first to fourth embodiments. Further, the folding circuit 15 folds the output a number of times determined in relation to the resolution (number of bits) of the upper bits of the digital signal output by the upper bit analog-digital conversion circuit 14 (hereinafter, the number of times of folding is expressed as “ The number of folding signals is referred to as a number that is determined in relation to the resolution (number of bits) of the lower bits of the digital signal generated by the encoder 16 (hereinafter referred to as “parallel number”).

<About the “number of loops” and “number of parallels” of the loopback signal>
The folding signal generated by the folding circuit provided in the folding type analog-to-digital converter circuit is the number of foldings corresponding to the upper bit resolution of the digital signal output by the upper-bit analog-to-digital converter circuit. A “parallel number” corresponding to the resolution of the lower bits of the digital signal output by the bit analog / digital conversion circuit (folding circuit and encoder) is required.
Specifically, the folding number and the parallel number of the folding signal generated by the folding circuit can be expressed by the following relational expressions (Equation 1) and (Equation 2).

  Here, when the upper bit resolution of the digital signal generated by the upper bit analog-digital conversion circuit is 1 bit, the lower bit resolution of the digital signal generated by the lower bit analog-digital conversion circuit is 2 bits. FIG. 12 shows the relationship between the number of folded back signals and the number of parallel signals.

When the upper bit resolution is 1 bit and the lower bit resolution is 2 bits, the parallel number and the folding number required for the folding signal generated by the folding circuit to generate a digital signal having such a resolution are: From (Expression 1) and (Expression 2), it can be seen that “the number of parallels = 2” and “the number of turns = 5”.
As shown in FIG. 12, on the basis of the folding signal with “parallel number = 2” and “folding number = 5” generated by the folding circuit, the encoder uses the lower bit (D2) corresponding to the upper bit (D2) of the digital signal. D1, D0) are generated. Here, FIG. 13 shows a truth table of the lower bits (D1, D0) of the digital signal generated by the encoder based on the folding signal with “parallel number = 2” and “folding number = 5”.

Further, although the case where the upper bit is 1 and the lower bit is 2 has been described as an example, the folding signal output from the folding circuit is not limited to the above example (parallel number = 2, folding number = 5). Depending on the resolution of the digital signal after D conversion (the resolution of the upper bits and the resolution of the lower bits), the number of parallels and the number of turns determined by (Expression 1) and (Expression 2) are obtained.
Further, when generating a plurality of folding signals, that is, when the number of parallels required for the folding signals is two or more, the distribution number of the input signal light in the folding circuit and the light intensity of the input reference light are changed and referenced. By using a plurality of configurations of the optical distribution unit and the folding signal output unit, a plurality of folding signals can be obtained simultaneously.

As described above, according to the present embodiment, a digital signal with multiple bits (for example, 5 bits or more) is output by providing a folding circuit that optically executes arithmetic processing using an input optical signal. Even in this case, it is possible to realize a high-speed operation as compared with the conventional folding type analog / digital conversion circuit, and it is possible to reduce the circuit scale and suppress the power consumption.
Therefore, the analog-to-digital converter circuit reduces the trade-off relationship between sample rate and resolution, achieves both high sample rate and high resolution, and suppresses the increase in circuit scale while reducing analog power consumption. Conversion can be realized.

[Sixth Embodiment]
The analog / digital conversion circuit according to the sixth embodiment of the present invention includes an upper bit analog / digital conversion circuit 14 and peripheral elements from the components of the analog / digital conversion circuit 10 described in the fifth embodiment. Except for this, the optical signals input by the folding circuit 15 and the encoder 16 are A / D converted. In addition, the same code | symbol is attached | subjected to what has the same structure and function as the component of the analog / digital conversion circuit 10 demonstrated in 5th Embodiment, and the detailed description is abbreviate | omitted.

FIG. 14 is a diagram showing a configuration of an analog / digital conversion circuit according to the present embodiment.
As shown in FIG. 14, the analog / digital conversion circuit 20 according to the present embodiment has an encoder 16 that receives an input signal light based on a folding signal output from the folding circuit 15 in synchronization with a predetermined clock CLK11-1. 1 is converted into a digital signal having a predetermined resolution and output.

The folding circuit 15 in the present embodiment has the same configuration as that of any of the folding circuits 100 to 400 described in the first to fourth embodiments, and the folding signal generated by the folding circuit 15 Has “folding number” and “parallel number” determined by the relational expressions shown in (Expression 1) and (Expression 2) described above.
Here, based on the folding signal output from the folding circuit 15 of the analog / digital conversion circuit 20 according to the present embodiment when the input signal light is A / D converted into a digital signal having a resolution (number of bits) of 3 bits. An example of the encoder output (truth table) is shown in FIG.

In the case as shown in FIG. 15, the “folding number” and “parallel number” of the folding signal output from the folding circuit 15 are “upper resolution = 0, lower resolution = 3” (formula 1) and (formula 2). Therefore, “folding number = 3” and “parallel number = 4”, and the folding circuit 15 generates such a folding signal and outputs it to the encoder 16.
The encoder 16 outputs a 3-bit digital signal based on the folding signal input in synchronization with the sampling clock.

  When a plurality of folding signals are generated, that is, when the number of parallels required for the folding signals is two or more, the distribution number of the input signal light and the light intensity of the input reference light in the folding circuit are changed to distribute the reference light. A plurality of folding signals can be obtained at the same time by using a plurality of configurations of the unit and the folding signal output unit.

  As described above, according to the present embodiment, high-speed operation is realized by A / D converting the input signal light by the folding circuit and the encoder that optically executes arithmetic processing using the input optical signal. In addition, the circuit scale can be made smaller than that of the analog / digital conversion circuit described in the fifth embodiment, and the power consumption can be kept low.

  The present invention can be used for an A / D conversion circuit in a receiving device of an optical communication system that requires a high sampling rate and high resolution A / D conversion performance, and an A / D conversion circuit inside a measuring instrument.

  DESCRIPTION OF SYMBOLS 1 ... Input signal light, 2 ... Input reference light 10, 20, 40 ... Folding type | mold analog / digital conversion circuit, 30 ... Flash type | mold analog / digital conversion circuit, 11, 31, 41 ... Clock distributor, 12 ... Optical distribution 13, photoelectric converter 14, 43, upper bit analog / digital conversion circuit 15, 44, 100 to 400, folding circuit 16, 34, 45, encoder, 17-1 to 17 -m, 36-1 To 36-3, 47-1 to 47-4, digital signal output terminals, 31-1, 41-1 ... clock signal input terminals CLK, 32 ... resistor ladder, 42 ... analog data distributor, 32-1, 42- DESCRIPTION OF SYMBOLS 1 ... Reference voltage (top side) input terminal VRT32-2, 42-2 ... Reference voltage (bottom side) input terminal VRB, 33 ... Voltage comparator, 110 ... Signal light Distributing section, 120, 220, 420... Reference light distributing section, 221, 421... Optical distributor, 222-1 to 222-n, 422-1 to 422-n ... Optical attenuator, 130, 330. 131 ... Comparison operation unit 133-11 to 131-1n, 333b ... Photoelectric converter, 131-21 to 131-2n ... Comparator, 331 ... Comparison operation unit (optical interferometer), 132 ... Inversion operation unit ( Inversion output unit), 332... Inversion operation unit (optical delay unit) 133... Addition operation unit (adder), 333... Addition operation unit, 333-a.

Claims (9)

A signal light distribution unit that distributes input signal light input from the outside into N (N is an integer) signal lights having the same light intensity;
A reference light distribution unit that distributes input reference light input from the outside to N reference lights having different light intensities according to a predetermined light intensity distribution ratio;
An N-bit thermometer code obtained by quantizing the light intensity of the input signal light is derived from the light intensities of the N signal lights and the N reference lights, and the logic of the thermometer code is set every other bit. A folding circuit comprising: a folded signal output unit that outputs a summed output of each bit of the inverted inverted thermometer code as a folded signal that is folded according to a change in light intensity of the input signal light. The folding circuit according to claim 1,
The reference light distributor is
A light distributor that distributes the input reference light into N light beams of equal light intensity;
And N optical attenuators having different transmittances and attenuating the light intensities of the N lights distributed by the optical distributor to light intensities corresponding to the distribution ratios, respectively. Folding circuit. The folding circuit according to claim 1 or 2,
A folding circuit comprising a plurality of the reference light distribution units, wherein the plurality of reference light distribution units have different distribution ratios. The folding circuit according to any one of claims 1 to 3,
The folding signal output unit is
The light intensity of one of the N signal lights is compared with the light intensity of one of the N reference lights, and N corresponding to the N comparison results is compared. A comparison operation unit for outputting the thermometer code of the bit;
An inversion operation unit that inverts the logic of the thermometer code output by the comparison operation unit every other bit and outputs the inversion thermometer code;
A folding circuit comprising: an addition operation unit that adds each bit of the inversion thermometer code output by the inversion operation unit and outputs an addition signal. The folding circuit according to claim 4,
The comparison operation unit
A first input terminal to which one of the N signal lights is input; and a second input terminal to which one of the N reference lights is input, and the first input A first output terminal that outputs an electrical signal converted from the signal light input to the terminal; and a second output that outputs an electrical signal converted from the reference light input to the second input terminal. N photoelectric converters having terminals,
N comparators that compare the electric potentials of the electric signals output from the first and second output terminals of the photoelectric converter and output electric signals according to the comparison results;
The inversion operation unit includes an inversion output device that inverts every other logic of the electric signals output from the N comparators,
The folding circuit includes an adder that adds N electrical signals inverted every other time by the inversion output unit and outputs the addition signal. The folding circuit according to claim 4,
The comparison operation unit includes an optical interferometer that outputs N interference optical signals by causing interference among one of the N signal lights and one of the N reference lights.
The inversion operation unit includes an optical delay device that delays every other phase of the N interference optical signals by 180 ° to generate a delayed interference optical signal,
The addition operation unit
An optical multiplexer that combines the N delayed interference optical signals output from the optical delay device and outputs a combined optical signal;
A folding circuit comprising: a photoelectric converter that converts the combined optical signal output from the optical multiplexer into an electrical signal and outputs the electrical signal. An analog-digital conversion circuit that converts input signal light input from the outside into a digital signal with a predetermined resolution,
An input signal light distributor for distributing the input signal light into two signal lights;
A photoelectric converter that converts one signal light distributed by the input signal light distributor into an electrical signal;
A clock distributor for distributing a predetermined clock signal to a plurality of predetermined sampling clock signals;
A voltage level of an electrical signal output from the photoelectric converter in synchronization with the sampling clock signal is compared with a reference voltage level input from the outside, and a predetermined higher order of the digital signal based on the comparison result An upper bit signal generation unit for generating a bit signal;
A folding circuit that inputs an input reference light input from the outside and the input signal light and generates a return signal that returns at a predetermined timing according to a change in light intensity of the input signal light; and
A lower bit signal generation unit that generates a predetermined lower bit signal of the digital signal based on the folded signal output from the folding circuit in synchronization with the sampling clock signal, and
The folding circuit according to any one of claims 1 to 6, wherein the folding signal having a folding number determined in relation to the resolution of the upper bit of the digital signal is converted into a resolution of the lower bit. An analog-to-digital conversion circuit characterized by generating a number determined in relation to An analog-digital conversion circuit that converts input signal light input from the outside into a digital signal with a predetermined resolution,
A sampling clock generator for outputting a predetermined sampling clock;
A folding circuit that inputs an input reference light input from the outside and the input signal light and generates a return signal that returns at a predetermined timing according to a change in light intensity of the input signal light; and
An encoder that generates the digital signal corresponding to the input signal light based on the folded signal output from the folding circuit in synchronization with the sampling clock;
7. The folding circuit according to claim 1, wherein the number of folded signals generated by the folding circuit and the number of folded signals are determined in relation to the resolution of the digital signal. An analog-digital conversion circuit characterized by The analog-digital conversion circuit according to claim 7 or 8,
The number of folding signals and the number of folding signals output from the folding circuit are expressed by the following relational expression: Fs = 2 ^{(m + 1)} +1, Ft = 2 ⁿ / 2 (where Fs is the number of folding signals and Ft is the number of folding signals) The number of folded signals, m is the number of bits of the upper bits of the digital signal, and n is the number of bits of the lower bits of the digital signal.

Images