JP5439983B2 - Multiprocessor system, interrupt control method, and interrupt control program - Google Patents

Description

  The present invention relates to a multiprocessor system, an interrupt control method, and an interrupt control program.

  Conventionally, a multiprocessor system is known in which interrupt processing is assigned to a plurality of processors and operates in cooperation. In a conventional multiprocessor system, each processor transmits a permission signal permitting an interrupt to the interrupt controller, and interrupt processing is assigned to the processor that transmitted the permission signal earliest.

  Here, processing for assigning interrupt processing will be specifically described with reference to FIG. FIG. 11 is a diagram for explaining the prior art. First, as shown in FIG. 11A, the interrupt controller transmits an interrupt request to each processor. Then, as shown in FIG. 11B, each processor transmits an interrupt permission signal to the interrupt controller when the processor is in an idle state (or a state where its own operation rate is a certain value or less).

  Then, as shown in FIG. 11C, the interrupt controller assigns an interrupt to the processor that has transmitted the permission signal earliest. In the example of FIG. 11, an interrupt is assigned to the processor C that has transmitted the permission signal earliest.

JP 2002-334066 A

  By the way, in the above-described conventional technique for allocating interrupt processing, an interrupt is allocated to the processor that has transmitted the permission signal earliest, so that the interrupt processing is allocated without considering the processor operating rate due to the interrupt.

  For this reason, when interrupt processing is uniformly assigned to each processor, all the processors are operating, and there is a problem that the power consumption of the processors cannot be suppressed.

  Accordingly, the present invention has been made to solve the above-described problems of the prior art, and an object thereof is to increase the number of sleeping processors and suppress the power consumption of the processors.

  In order to solve the above-described problems and achieve the object, this apparatus predicts the operation rate of each processor when interrupt processing is assigned when assigning interrupt processing to any of a plurality of processors executing interrupt processing. Then, control is performed so that interrupt processing is assigned to a processor having an operation rate that does not exceed the upper limit operation rate and is closest to the upper limit operation rate among the predicted operation rates of the respective processors.

  The disclosed system has an effect of increasing the number of sleeping processors and reducing the power consumption of the processors.

FIG. 1 is a diagram for explaining the configuration of the multiprocessor system according to the first embodiment. FIG. 2 is a block diagram illustrating the configuration of the multiprocessor system according to the second embodiment. FIG. 3 is a diagram for explaining an example of the operation rate table. FIG. 4 is a diagram for explaining an assumed operation rate calculation process. FIG. 5 is a diagram for explaining the change in the operation rate when the interrupt is dynamically assigned. FIG. 6 is a diagram for explaining processing in which the interrupt controller determines the operation rate. FIG. 7 is a flowchart for explaining the processing procedure of the interrupt controller according to the second embodiment. FIG. 8 is a block diagram illustrating the configuration of the multiprocessor system according to the third embodiment. FIG. 9 is a diagram for explaining processing in which each processor determines an operation rate. FIG. 10 is a diagram illustrating a computer that executes an interrupt control program. FIG. 11 is a diagram for explaining the prior art.

  Exemplary embodiments of a multiprocessor system, an interrupt control method, and an interrupt control program according to the present invention will be described below in detail with reference to the accompanying drawings.

  In the following embodiment, the configuration and processing of the multiprocessor system according to the first embodiment will be described, and finally the effects of the first embodiment will be described.

  First, the configuration of the multiprocessor system according to the first embodiment will be described with reference to FIG. FIG. 1 is a block diagram illustrating the configuration of the multiprocessor system according to the first embodiment. The multiprocessor system 1 includes an interrupt controller 2 and a plurality of processors 3.

  The interrupt controller 2 according to the first embodiment includes an operation rate prediction unit 2a and an interrupt destination control unit 2b.

  The operation rate prediction unit 2a predicts the operation rate of each of the processors A to C when the interrupt processing is allocated when the interrupt processing is allocated to any of the plurality of processors A to C that execute the interrupt processing.

  The interrupt destination control unit 2b assigns an interrupt process to a processor having an operation rate that does not exceed the upper limit operation rate and is closest to the upper limit operation rate among the operation rates of the processors predicted by the operation rate prediction unit 2a. To control.

  As described above, the multiprocessor system 1 is a processor having an operation rate that does not exceed the upper limit operation rate (for example, the operation rate “100%”) and that has the operation rate closest to the upper limit operation rate. Assign intensively.

  For this reason, the interrupt controller 2 can increase the number of processors to which sleep processing is performed by increasing the number of processors to which interrupt processing is not assigned. As a result, it is possible to suppress the power consumption of the processors by increasing the number of processors that sleep.

  In the following embodiments, the configuration and processing flow of the multiprocessor system according to the second embodiment will be described in order, and finally the effects of the second embodiment will be described.

[Configuration of multiprocessor system]
Next, the configuration of the multiprocessor system shown in FIG. 1 will be described with reference to FIG. FIG. 2 is a block diagram illustrating the configuration of the multiprocessor system according to the second embodiment. As shown in the figure, the multiprocessor system 1A includes an interrupt controller 10, a plurality of processors 20, an IO interface 30, and a memory 40, which are connected via a bus 50. The processing of each of these units will be described below.

  The interrupt controller 10 grasps the operation rate from the interrupt transmitted to each processor 20. The interrupt controller 10 calculates an operation rate of a process to be interrupted by the processor. Based on the operation rate of each processor and the operation rate of interrupt processing, an interrupt signal is transmitted to the processor 20 whose operation rate is close to 100%.

  Here, the configuration of the split interrupt controller 10 will be specifically described. The interrupt controller 10 includes a register 11, an operation rate prediction unit 12 for each processor (an operation rate table 12a for each process, an initial state operation rate calculation unit 12b, an assumed operation rate calculation unit 12c), an interrupt destination determination unit 13, and a cross connect 14 Have

  The operation rate prediction unit 12 of each processor predicts the operation rate of each of the processors A to C when the interrupt processing is allocated when the interrupt processing is allocated to any of the plurality of processors A to C that execute the interrupt processing. . The operation rate prediction unit 12 of each processor has an operation rate table 12a for each process, an initial state operation rate calculation unit 12b, and an assumed operation rate calculation unit 12c.

  The operation rate table 12a of each process stores the operation rate of each interrupt process. Specifically, as shown in FIG. 3, the operation rate table 12a for each process includes a type of interrupt process, a “request time” indicating when the process must be performed, and a load of 100% on the processor. The “minimum processing time”, which is the processing time when operating in, and the “operation rate” when interrupt processing is processed are stored in association with each other. FIG. 3 is a diagram for explaining an example of the operation rate table.

  Here, the operation rate is a value obtained by dividing the minimum processing time by the required time. That is, “operation rate” = “minimum processing time” / “request time” can also be obtained. For example, the operation rate of the process “A” is “20 ms” / “100 ms” = “20%”.

  The initial state operation rate calculation unit 12b calculates the operation rate of the current processor using the operation rate table 12a of each process. For example, referring to the example of FIG. 3, when the interrupt processing A is assigned to the processor A, the initial state operation rate calculation unit 12b has the current operation rate of the processor A of “20%”. Calculate that there is. Note that the processor operating rate is “0%” immediately after start-up, because no interrupt processing is assigned to the processor.

  The assumed operation rate calculation unit 12c calculates an assumed operation rate that is an operation rate of each processor when interrupt processing is assigned. Further, the assumed operation rate calculation unit 12c gives priority to an interrupt process with a short request processing time. That is, when the request processing time of the interrupt processing newly assigned is shorter than the request processing time of the processing currently being performed by the processor, the interrupt processing is assigned.

  Here, a method for calculating the assumed operation rate will be specifically described. The assumed operation rate calculation unit 12c uses the operation rate table 12a of each process, and the interrupt controller uses the current processing request processing time, the current processing minimum processing time, the interrupt processing request processing time, and the interrupt processing minimum processing. Know the time.

  Then, the assumed operation rate calculation unit 12c uses the current request processing time as the denominator and the sum of the minimum processing time of the current processing and the minimum processing time of the interrupt processing as the numerator. The expected operation rate when interrupt processing is performed from the above denominator and numerator is obtained. That is, “operation rate” = (“minimum processing time of current processing” + “minimum processing time of interrupt processing”) / “requested time of current processing” is also obtained.

  Here, the calculation method of the assumed operation rate will be specifically described with reference to the example of FIG. FIG. 4 is a diagram for explaining an assumed operation rate calculation process. In FIG. 4, the request processing time of the current processing is “request processing time 1”, the minimum processing time of the current processing is “minimum processing time 1”, the request processing time of interrupt processing is “request processing time 2”, and interrupt processing The minimum processing time is “minimum processing time 2”.

  As shown in FIG. 4, for the processor A, the assumed operation rate calculation unit 12c has a required processing time 1 of “100 ms”, a minimum processing time 1 of “20 ms”, and a required processing time 2 of “20 ms”. Yes, the minimum processing time 2 is “10 ms”. For this reason, the assumed operation rate calculation unit 12c calculates (20 ms + 10 ms) / 100 ms, and the assumed operation rate becomes “30%”.

  Further, for the processor B, the assumed operation rate calculation unit 12c has a required processing time 1 of “100 ms”, a minimum processing time 1 of “80 ms”, a required processing time 2 of “20 ms”, and a minimum processing time. 2 is “10 ms”. For this reason, the assumed operation rate calculation unit 12c calculates (80 ms + 10 ms) / 100 ms, and the assumed operation rate becomes “90%”.

  Further, the assumed operating rate calculation unit 12c has a required processing time 1 of “100 ms”, a minimum processing time 1 of “95 ms”, a required processing time 2 of “20 ms” and a minimum processing time of the processor C. 2 is “10 ms”. For this reason, the assumed operation rate calculation unit 12c calculates (95 ms + 10 ms) / 100 ms, and the assumed operation rate becomes “105%”.

  The interrupt destination determination unit 13 assigns an interrupt process to a processor having an operation rate that does not exceed the upper limit operation rate “100%” and is closest to “100%” among the predicted operation rates of the respective processors. To control.

  For example, in the example of FIG. 4, the interrupt destination determination unit 13 has an assumed operation rate of “30%” for the processor A, “90%” for the assumed operation rate of the processor B, and “105%” for the assumed operation rate of the processor C. It is. For this reason, control is performed so that interrupt processing is assigned to the processor B that does not exceed the upper limit operation rate “100%” and has the operation rate closest to “100%”.

  Here, the change in the operation rate when the interrupt is dynamically assigned will be described with reference to FIG. FIG. 5 is a diagram for explaining the change in the operation rate when the interrupt is dynamically assigned. As illustrated in FIG. 5, in the initial state, the processor A performs the process A and the operation rate is 20%, the processor B performs the process B and the operation rate is 80%, and the processor C Processing C is performed and the operating rate is 95%.

  Here, when the interrupt controller 10 receives the interrupt factor D, the interrupt controller 10 calculates an assumed operation rate for each processor when the process D is performed in addition to the current process. That is, as shown in FIG. 5, the assumed operation rate of the processor A is 30%, the assumed operation rate of the processor B is 90%, and the assumed operation rate of the processor C is 105%.

  Then, the interrupt destination determination unit 13 determines to allocate an interrupt process to the processor B having an operation rate that does not exceed the upper limit operation rate “100%” and is closest to “100%”. Specifically, the interrupt controller 10 cross connects the interrupt factor D to the processor B through the cross connect 14. The processor B receives the interrupt of the interrupt factor D and starts the process D.

  Thereafter, when the interrupt controller 10 further receives the interrupt factor D, the interrupt controller 10 calculates the assumed operation rate for each processor when the process D is performed in addition to the current process, as described above. That is, as shown in FIG. 5, the assumed operation rate of the processor A is 30%, the assumed operation rate of the processor B is 100%, and the assumed operation rate of the processor C is 105%.

  Then, the interrupt destination determination unit 13 determines to allocate an interrupt process to the processor B that has an estimated operation rate that does not exceed the upper limit operation rate “100%” and is closest to “100%”. Specifically, the interrupt controller 10 cross-connects the interrupt factor D to the processor B through the cross-connect unit 14. The processor B receives the interrupt of the interrupt factor D and starts the process D.

  Thereafter, it is assumed that the processing in the initial state (processor A is processing A, processor B is processing B, and processor C is processing C) is completed. As for the operation rate of each processor, the processor A can sleep at 0%, the processor B can sleep at 20%, and the processor C can sleep at 0%. In other words, as a result of intensively assigning to the processor B having the operation rate closest to “100%” and not assigning to the processor A and the processor C, the processor A and the processor C enter the sleep state, and power saving can be achieved. it can.

  Thus, as illustrated in FIG. 6, the interrupt controller 10 determines the assumed operation rate, does not exceed the upper limit operation rate “100%”, and is the assumed operation rate closest to “100%”. It is decided to assign an interrupt process to the processor B. For this reason, it is possible to increase the number of processors to sleep and suppress the power consumption of the processors.

  The register 11 stores an interrupt factor assigned to each processor. The cross connect 14 cross connects interrupt factors to the processor.

  The processor 20 receives an interrupt cause interrupt from the interrupt controller 10 and executes interrupt processing. The IO interface 30 controls input / output of information. The memory 40 stores data necessary for various processes.

[Processing by interrupt controller]
Next, processing performed by the interrupt controller 10 according to the second embodiment will be described with reference to FIG. FIG. 7 is a flowchart illustrating the processing operation of the interrupt controller 10 according to the second embodiment.

  As shown in the figure, the interrupt controller 10 initializes the operation rate of each processor to 0% as an initialization process (step S101). Then, the interrupt controller 10 enters an idle state (step S102). When an interrupt factor is accepted, the interrupt controller 10 calculates an assumed operation rate that is an operation rate of each processor when interrupt processing is assigned (step S103).

  Then, the interrupt controller 10 selects a processor that does not exceed the upper limit operation rate “100%” and has an assumed operation rate that is closest to “100%” (step S104), and performs interrupt processing on the selected processor. Allocate and generate an interrupt (step S105). Thereafter, the interrupt controller 10 returns to the idle state, and repeats the processing of steps S102 to S106 each time an interrupt factor is accepted.

[Effect of Example 2]
As described above, the interrupt controller 10 predicts the operation rate of each processor 20 when the interrupt process is assigned when the interrupt process is assigned to any of the plurality of processors 20. Then, the interrupt controller 10 performs control so that interrupt processing is allocated to the processor 20 having an operation rate that does not exceed the upper limit operation rate and is closest to the upper limit operation rate among the predicted operation rates of the respective processors 20.

  For this reason, the interrupt controller 10 concentrates the allocation on the processors 20 whose operation rate is closest to “100%”, increases the number of processors 20 to which no interrupt processing is allocated, and increases the number of processors 20 that sleep. be able to. As a result, the number of processors 20 that sleep can be increased to reduce the power consumption of the processors 20. Further, since the interrupt controller 10 predicts the operation rate, the processing load can be centrally managed.

  Further, according to the second embodiment, the interrupt controller 10 is a minimum time indicating a request time indicating how long the interrupt processing should be processed and a processing time required when the processor 20 is operated at the load of the upper limit operation rate. The operation rate of each processor 20 is predicted using the processing time. For this reason, it is possible to predict the operation rate of each processor 20 appropriately.

  Further, according to the second embodiment, the interrupt controller 10 stores the interrupt processing type, the request time, the minimum processing time, and the operation rate when the interrupt processing is processed in association with each other for the interrupt processing. Therefore, the interrupt controller 10 can reduce the burden of calculating the operation rate for each interrupt process.

  In the second embodiment, the case where the interrupt controller predicts the operation rate of each processor has been described. However, the present embodiment is not limited to this, and each processor predicts the operation rate of its own processor. You may do it.

  Therefore, in the following third embodiment, the configuration and processing of the multiprocessor system in the third embodiment will be described using FIGS. 8 and 9 as a case where each processor predicts the operation rate of its own processor. FIG. 8 is a block diagram illustrating the configuration of the multiprocessor system according to the third embodiment. FIG. 9 is a diagram for explaining processing in which each processor determines an operation rate. Note that the description of the same configuration and the same processing as in the second embodiment is omitted.

  As illustrated in FIG. 8, the interrupt controller 10a includes a register 11a, an interrupt destination determination unit 13a, a cross connect 14, and an interrupt request signal transmission unit 15. Each processor 20 a includes an initial state operation rate calculation unit 21, an assumed operation rate calculation unit 22, and a permission signal transmission unit 23. In addition, the memory 40a stores an operation rate table 41 that stores the operation rate of each process.

  The operation rate table 41 stores the operation rate of each interrupt process. Specifically, the operation rate table 41 is similar to the second embodiment in that the type of interrupt processing, “request time” indicating how long it must be processed, and when the processor is operated with a load of 100% Is stored in association with the “minimum processing time” that is the processing time of the above and the “operation rate” when the interrupt processing is processed. A different table may be stored for each processor.

  The register 11a of the interrupt controller 10a includes an “interrupt factor” that is an interrupt factor currently being executed by each processor, an “transmission request factor” that is an interrupt factor requested by an interrupt request signal transmitted to each processor 20a, and each processor. The “permission signal” indicating that the interrupt written in 20a is possible is stored.

  When receiving an interrupt factor, the interrupt request signal transmission unit 15 of the interrupt controller 10a transmits an interrupt request signal for requesting interrupt processing to each processor 20a.

  When receiving the interrupt request signal from the interrupt request signal transmission unit 15, the initial state operation rate calculation unit 21 of each processor 20a uses the operation rate table 41 stored in the memory 40a as in the second embodiment. Calculate the current operating rate of.

  Here, since the register 11a of the interrupt controller stores the interrupt factor of the currently executing process as the initial state operating rate, the interrupt factor of the currently executing process is stored in the interrupt controller register 11a. Is read, and the current operation rate of the processor is calculated.

  Further, as in the second embodiment, the assumed operation rate calculation unit 22 calculates an assumed operation rate that is the operation rate of the own processor when interrupt processing is assigned. Here, the assumed operation rate calculation unit 22 reads the interrupt request signal of which interrupt factor is received from the register 11a, and then calculates the assumed operation rate that is the operation rate of the own processor when the interrupt process is assigned. To do.

  When the predicted operation rate of the processor does not exceed the upper limit operation rate “100%”, the permission signal transmission unit 23 permits an interrupt at an earlier timing as the operation rate increases. In other words, the permission signal transmission unit 23 determines whether or not an interrupt is possible after calculating the assumed operation rate of the processor, and if interrupt is possible, the interrupt is permitted at an earlier timing as the assumed operation rate is larger. The permission signal to be transmitted is transmitted to the interrupt controller 10a.

  Specifically, the permission signal transmission unit 23 determines whether or not the assumed operation rate of the own processor exceeds “100%”, and determines that the interruption is possible when it does not exceed. Then, when the interrupt is possible, the permission signal transmission unit 23 transmits the permission signal permitting the interrupt at an earlier timing as the assumed operation rate is larger, and at a later timing as the assumed operation rate is smaller. A permission signal for permitting an interrupt is transmitted to the interrupt controller 10a.

  Moreover, the permission signal transmission part 23 does not transmit a permission signal, when an interruption is possible. Note that the processor 20a writes the permission signal to the register 11a with an offset in time.

  The interrupt destination determination unit 13a of the interrupt controller 10a identifies the processor that has transmitted the permission signal earliest and determines the interrupt destination. Then, the interrupt destination determination unit 13a of the interrupt controller 10a performs control so that interrupt processing is assigned to the processor.

  Here, it demonstrates concretely using the example of FIG. As shown in FIG. 9A, when an interrupt request is received from the interrupt controller 10a, each processor 20a determines an assumed operation rate of the own device. Here, it is assumed that the assumed operation rate of the processor A is 30%, the assumed operation rate of the processor B is 90%, and the assumed operation rate of the processor C is 105%.

  In such a case, as shown in FIG. 9B, for example, the processor A transmits a permission signal to the interrupt controller 10a after 70 μsec. Further, for example, the processor B transmits a permission signal to the interrupt controller 10a after 10 μs, and the processor C does not transmit a permission signal. As a result, as shown in FIG. 9C, the interrupt controller 10a assigns an interrupt process to the processor B that has transmitted the permission signal earliest.

  In this way, the plurality of processors 20a predict the operation rate of the own processor when the interrupt processing is assigned, and when the predicted operation rate of the own processor does not exceed the upper limit operation rate, the operation rate is A permission signal permitting an interrupt is transmitted to the interrupt controller 10a at an earlier timing as the value increases. Then, the interrupt controller 10a performs control so that interrupt processing is assigned to the processor 20a that has transmitted the permission signal earliest among the transmitted permission signals of each processor 20a.

  For this reason, the interrupt controller 10a can increase the number of processors to sleep by intensively assigning to processors whose operation rate is the closest to “100%”, increasing the number of processors not assigned interrupt processing. . As a result, it is possible to suppress the power consumption of the processors by increasing the number of processors that sleep. In addition, since each processor 20a predicts the operation rate, the processing load can be distributed.

  Although the present embodiment has been described so far, the present invention may be implemented in various different forms other than the embodiment described above. Accordingly, another embodiment included in the present invention will be described below as a fourth embodiment.

(1) System Configuration, etc. Further, each component of each illustrated apparatus is functionally conceptual and does not necessarily need to be physically configured as illustrated. In other words, the specific form of distribution / integration of each device is not limited to that shown in the figure, and all or a part thereof may be functionally or physically distributed or arbitrarily distributed in arbitrary units according to various loads or usage conditions. Can be integrated and configured. For example, the initial state operation rate calculation unit 12b and the assumed operation rate calculation unit 12c may be integrated. Further, all or any part of each processing function performed in each device may be realized by a CPU and a program analyzed and executed by the CPU, or may be realized as hardware by wired logic.

  In addition, among the processes described in this embodiment, all or part of the processes described as being performed automatically can be performed manually, or the processes described as being performed manually can be performed. All or a part can be automatically performed by a known method. In addition, the processing procedure, control procedure, specific name, and information including various data and parameters shown in the above-described document and drawings can be arbitrarily changed unless otherwise specified.

(2) Program Various processes of the interrupt controller 2 described in the first embodiment can be realized by executing a program prepared in advance on a computer system such as a personal computer or a workstation. In the following, an example of a computer that executes an interrupt control program having the same function as that of the first embodiment will be described with reference to FIG. FIG. 10 is a diagram illustrating a computer that executes an interrupt control program.

  As shown in the figure, a computer 900 as an interrupt controller is configured by connecting a RAM 910, a CPU 920, an HDD 930, and a cross-connect 940 via a bus.

  Here, the cross connect 940 controls communication related to various types of information exchanged with the processor. The HDD 930 stores information necessary for the CPU 920 to execute various processes. The RAM 910 temporarily stores various information. The CPU 920 executes various arithmetic processes.

  As shown in FIG. 10, the HDD 930 stores in advance an interrupt control program 911 that exhibits the same function as each processing unit of the interrupt controller shown in the first embodiment. Note that the interrupt control program 911 may be appropriately distributed and stored in a storage unit of another computer that is communicably connected via a network.

  Then, the CPU 920 reads this interrupt control program 911 from the HDD 930 and expands it in the RAM 910. The interrupt control program 911 reads various data from the HDD 930, expands the data in an area allocated to itself in the RAM 910, and executes various processes based on the expanded data.

  The interrupt control program 911 described above does not necessarily need to be stored in the HDD 930 from the beginning. For example, a flexible disk (FD), a CD-ROM, a DVD disk, a magneto-optical disk, an IC inserted into the computer 900 can be used. Each program is stored in a “portable physical medium” such as a card, and “another computer (or server)” connected to the computer 900 via a public line, the Internet, a LAN, a WAN, or the like. The computer 900 may read and execute each program from these.

1, 1A, 1B Multiprocessor system 2, 10, 10a Interrupt controller 11 Register 12 Operation rate prediction unit of each processor 12a Operation rate table 12b Initial state operation rate calculation unit 12c Assumed operation rate calculation unit 13 Interrupt destination determination unit 14 Cross connect 15 Interrupt request signal transmission unit 3, 20, 20a Processor 30 IO interface 40 Memory

Claims (6)

A multiprocessor system having a plurality of processors that execute interrupt processing and an interrupt controller that assigns interrupt processing to the processors,
The interrupt controller is
When assigning interrupt processing to any of the plurality of processors, an operation rate prediction unit that predicts the operation rate of each processor when the interrupt processing is assigned;
An interrupt destination control unit that performs control so that interrupt processing is allocated to a processor having an operation rate that does not exceed the upper limit operation rate and that is closest to the upper limit operation rate among the operation rates of each processor predicted by the operation rate prediction unit When,
A multiprocessor system comprising:   The operating rate predicting unit uses a request time indicating how long the interrupt processing must be processed and a minimum processing time indicating a processing time required when the processor is operated with a load of an upper limit operating rate. The multiprocessor system according to claim 1, wherein an operation rate of each processor is predicted.   The interrupt controller further includes an operation rate storage unit that stores, in association with the interrupt processing, the type of the interrupt processing, the request time, the minimum processing time, and the operation rate when the interrupt processing is processed in association with each other. The multiprocessor system according to claim 2, further comprising: A multiprocessor system having a plurality of processors that execute interrupt processing and an interrupt controller that assigns interrupt processing to the processors,
The plurality of processors are
When an interrupt request signal is received from the interrupt controller, an operation rate prediction unit that predicts an operation rate of the own processor when the interrupt processing is assigned;
When the operation rate of the own processor predicted by the operation rate prediction unit does not exceed the upper limit operation rate, the larger the operation rate, the higher the permission that allows an interrupt at an earlier timing from the reception of the interrupt request signal A permission signal transmitter for transmitting a signal to the interrupt controller;
With
The interrupt controller is
Among the permission signals of each processor transmitted by the permission signal transmission unit, an interrupt destination control unit that controls to assign an interrupt process to the processor that transmitted the permission signal earliest;
A multiprocessor system comprising: An interrupt control method performed in a multiprocessor system having a plurality of processors that execute interrupt processing and an interrupt controller that assigns interrupt processing to the processor,
Said interrupt controller, when assigning interrupt processing in any of said plurality of processors to execute the interrupt processing, the operation rate prediction step of predicting the behavior of each processor when assigned the interrupt processing,
It said interrupt controller, among the operation rate of each processor which is predicted by the operation ratio prediction step, does not exceed the upper limit operation rate, and the interrupt process controller to allocate to the nearest operating ratio of the processor to the upper limit operation rate Interrupt destination control step to
An interrupt control method comprising: An interrupt control program to be executed by a computer having a plurality of processors for executing interrupt processing,
When assigning an interrupt process interrupt processing in any of said plurality of processors executing, operating rate and the prediction procedure for predicting the behavior of each processor when assigned the interrupt processing,
Interrupt destination control procedure for controlling to assign an interrupt process to a processor having an operation rate closest to the upper limit operation rate among the operation rates of each processor predicted by the operation rate prediction procedure When,
An interrupt control program characterized by causing a computer to execute.

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