JP5453345B2 - Memory control unit - Google Patents

Description

  The present invention relates to a memory control device for controlling a DRAM such as a DDR3-SDRAM.

  2. Description of the Related Art Conventionally, an image forming apparatus or the like is equipped with a memory module (RAM) that temporarily stores programs, control data, and image data. For example, a memory chip such as a DDR-SDRAM (Double Data Rate Synchronous Random Random Access Memory) that can read and write data at both rising and falling timings of the data strobe signal is mounted on the memory module. DDR-SDRAM has a plurality of standards such as DDR, DDR2, and DDR3. A device equipped with a memory module (memory chip) such as an image forming device is equipped with a memory control device for controlling reading and writing.

  For example, Patent Document 1 describes an example of a memory control device. Specifically, Patent Document 1 includes delay adjustment means for delay adjustment of a data strobe signal for a memory system that reads / writes data from / to a DDR-SDRAM, and sets a specific value to a specific address. Memory control means for reading and writing to the same address as the address while changing the delay value of the write and delay adjusting means, comparing and recognizing both values, and setting the intermediate value of the recognized readable range in the delay adjusting means A memory control device is described. With this configuration, by reading while changing the value of the delay adjustment means, the optimum delay time set in the delay adjustment means is recognized depending on whether or not the correct value has been read, and an attempt is made to latch the read data within the effective area. (See Patent Document 1: Claim 1, paragraph [0008], etc.).

JP 2003-099321 A

  As described above, various devices including a memory module such as an image forming apparatus may be provided with a memory control device that controls the operation of the memory module and the memory chip included in the memory module.

  Here, for example, in the DIMM (Dual Inline Memory Module) of DDR3-SDRAM, the presence or absence of an address mirror can be selected as an option. The address mirror is defined in the DDR3 standard (for example, refer to Page 14 of JEDEC Standard JEDEC Standard No. 21C Page 4.20.19-1. This standard can be found at www.jedec.org/sites/default/ files / docs / 4_20_19R20.pdf etc.)

  To match the trace length (line length) of the memory chip such as each SDRAM mounted on the memory module and improve the quality of the signal on the memory module, the address mirror replaces and connects the memory signal lines. It is recognized that In other words, there is an option to connect a signal line to a pin different from a predetermined pin of the memory chip when connected to the pin of the memory socket (replacement of signal line). For example, normally (when there is no address mirror), the A3 pin on the connector side of the memory module is connected to the A3 pin of the SDRAM, but when there is an address mirror, the A3 pin on the connector side of the memory module is Connect to A4 pin of SDRAM.

  In normal memory access, even if the address lines (signal lines) are misconnected by the address mirror inside the memory module, the addresses correspond one-to-one with read and write. For this reason, there is no need to perform address conversion or the like even if there is a misplaced address in each process of read and write, and there is no need to be aware of it. On the other hand, setting commands (for example, MRS command, JEDEC standard JESD79-3D, page 24, etc.) for setting memory chip initialization and operation (behavior). This standard can be found at www.jedec.org/ standards-documents / docs / jesd-79-3d). Then, a setting command may be given to each memory chip using a signal line that is switched and connected by an address mirror.

  In such a command that gives special meaning to the address itself (using a signal line to be exchanged by the address mirror), the memory control device needs to generate the command while considering the address misplacement by the address mirror. is there. However, in the conventional memory control device, when generating a command that gives a special meaning to the address itself for a memory module that has both a memory chip with an address mirror and a memory chip without an address mirror, It corresponds. Specifically, the software performs processing to confirm the presence / absence of an address mirror, temporarily generates a command for a memory chip without an address mirror, and further performs processing such as changing the address of a setting command. A command is generated for a memory chip with a mirror.

  In this way, in the command that makes the address itself meaningful, conventionally, the presence / absence of the address mirror is determined by software, and the command is generated separately according to the presence / absence of the address mirror (repeat command issuance). There is a problem in that initialization and operation settings are complicated, and unnecessary time is generated until command issue is completed.

  In the invention described in Patent Document 1, there is no description about a command that gives a special meaning to the address mirror or the address itself, and the above problem cannot be solved.

  In view of the above problems, the present invention eliminates complicated command issuance (command generation) by special control by software when the presence or absence of address mirror is mixed, and issues commands that give special meaning to the address itself. It is an object to generate and simplify initialization and operation setting of a memory chip.

  In order to solve the above-described problem, a memory control device according to claim 1 includes a queuing unit for queuing a command for a memory module mounted with a plurality of memory chips including a configuration setting register for setting an operation, and a memory. An address mirror setting unit that holds address mirror information indicating the presence / absence of an address mirror in the chip, and a command generation request from the queuing unit and a command generation for the memory chip according to target information indicating a memory chip to be commanded A command issuing unit that issues a request, and a signal line that generates a command for the memory chip based on the command generation request issued by the command issuing unit, gives the command to the memory chip, and is a target of wiring replacement by an address mirror The setting configuration using A command generation unit that provides a setting command for setting a register to a memory chip, and the command generation unit provides a similar setting command to a memory chip without an address mirror and a memory chip with an address mirror. Based on the address mirror information and the target information, a process of giving the setting command generated toward a memory chip without an address mirror is performed, and for a memory chip with an address mirror, a signal exchanged by the address mirror According to the line, an address conversion unit that converts the address of the setting command to generate the setting command for the memory chip having the address mirror is included.

  According to this configuration, when the command generation unit gives the same setting command to the memory chip without the address mirror and the memory chip with the address mirror, the command generation unit applies the setting to the memory chip without the address mirror based on the address mirror information and the target information. For the memory chip with the address mirror, the address of the setting command is converted for the memory chip with the address mirror, and the address of the setting command is converted for the memory chip with the address mirror. An address conversion unit that generates a setting command is included. As a result, the address conversion unit as hardware automatically converts the address of the setting command for the memory chip having the address mirror. In other words, if the command issuing unit issues target information indicating the memory chip that is the target of the setting command and a setting command generation request, the command generating unit automatically generates a setting command according to the presence or absence of an address mirror. Give to the memory chip.

  In this way, the command issuing unit and queuing unit determine the presence / absence of an address mirror by software, and issue a request for a setting command according to the presence / absence of an address mirror separately (divided into multiple times). It is not necessary to perform conversion or the like, and setting commands can be continuously given to a memory chip having an address mirror and a memory chip having no address mirror. In other words, since software processing such as address conversion is not required, it is possible to automatically divide and process setting command issuance for a memory chip with an address mirror and a memory chip without an address mirror. Therefore, it is possible to simplify the initialization of the memory chip and the operation setting process. Further, even if a memory chip having an address mirror and a memory chip having no address mirror are mixed in the memory module, the control flow such as initialization can be made common.

  According to a second aspect of the present invention, in the first aspect of the present invention, the address mirror setting unit holds address mirror rank information indicating the presence / absence of a rank address mirror in the memory module, and from the memory chip having the address mirror. When the same setting command is generated for each rank of a memory module including a rank and a rank including a memory chip without an address mirror, the queuing unit matches the request for issuing the setting command as the target information. First rank information indicating a rank without an address mirror and second rank information indicating a rank with an address mirror are transmitted to the command issuing unit, and the command issuing unit transmits the first command together with the setting command generation request. The rank information and the second rank information are sent to the command generator. The address conversion unit, based on the information held by the address mirror setting unit, the first rank information, and the second rank information, according to the replaced signal line, for the rank without an address mirror The setting command address is converted to generate the setting command for a memory chip having an address mirror.

  According to this configuration, the address conversion unit, based on the information held by the address mirror setting unit, the first rank information, and the second rank information, sets the setting command for the rank without the address mirror according to the replaced signal line. Converts the address and generates a setting command for the memory chip having the address mirror. Thus, command issue (generation) for each rank is automatically divided according to the presence or absence of an address mirror. Therefore, even if the rank with address mirror and the rank without address mirror are mixed in the memory module, the presence / absence of the address mirror is determined by the software separately (divided into multiple times) according to the presence / absence of the address mirror. Therefore, it is not necessary to issue a setting command, and it is possible to initialize memory chips at the same rank and simplify operation settings.

  According to a third aspect of the present invention, in the second aspect of the present invention, the queuing unit continuously transmits the first rank information and the second rank information together with the setting command issuance request. The command issuing unit issues the setting command generation request to the command generation unit and the second rank information following the first rank information in accordance with the setting command generation request. The command is transmitted to the command generation unit.

  According to this configuration, the queuing unit continuously transmits the first rank information and the second rank information to the command generating unit together with the setting command issuance request, and the command issuing unit generates the setting command as a command. The second rank information is issued to the command generation unit following the first rank information. As a result, when a setting command is issued for a plurality of ranks, the setting command is continuously issued for each of the rank having no address mirror and the rank having the address mirror. As a result, even if a rank with an address mirror and a rank without an address mirror are mixed, a setting command can be issued promptly and a command can be generated.

  According to the configuration of the present invention, it is possible to eliminate complicated command issuance by special control by software due to the presence or absence of an address mirror. Therefore, a command for giving a special meaning to the address itself can be issued smoothly, and initialization and memory chip operation setting can be simplified.

1 is a block diagram illustrating an example of a multifunction machine. It is a block diagram which shows an example of the memory system containing a memory control apparatus. It is a block diagram which shows an example of an internal structure of a memory control apparatus. It is explanatory drawing for demonstrating an address mirror. It is explanatory drawing which shows an example of the operation setting command of each memory chip. It is a timing chart which shows an example of command issue when the presence or absence of an address mirror is not mixed. It is a timing chart which shows an example of the conventional command issue when the presence or absence of an address mirror is mixed. It is a timing chart which shows an example of command issue in the memory control device of this embodiment when the presence or absence of an address mirror is mixed.

  Hereinafter, embodiments of the present invention will be described with reference to FIGS. However, each element such as the configuration described in this embodiment does not limit the scope of the invention and is merely an illustrative example.

(An example of a device equipped with the memory control device 1)
First, based on FIG. 1, an example of a device in which the memory control device 1 according to the embodiment is mounted will be described. As an example of a device on which the memory control device 1 is mounted, the multifunction device 100 is given as an example. FIG. 1 is a block diagram illustrating an example of a multifunction peripheral 100.

  The multi-function device 100 is provided with an image reading unit 101 as a part for scanning. For example, the image reading unit 101 includes a contact glass on the upper surface, and reads a document placed on the contact glass. In the image reading unit 101, for example, an exposure lamp, a mirror, a lens, an image sensor (for example, a CCD), etc. (all not shown) are arranged, and the reflected light to the document is guided to the image sensor. Is A / D converted to obtain document image data.

  Further, the multifunction peripheral 100 is provided with a paper feeding unit 102, a conveyance path 103, an image forming unit 104, a fixing unit 105, and the like as a part for performing printing (print engine part). The paper supply unit 102 accommodates various sizes of paper such as copy paper. The paper feed unit 102 then feeds the paper to the transport path 103 one by one during printing. The transport path 103 is a path for transporting the paper supplied from the paper supply unit 102. The conveyance path 103 is provided with, for example, a guide plate for paper guidance, a conveyance roller pair that is connected to a drive mechanism (not shown) including a motor and the like and is rotated and conveyed.

  The image forming unit 104 forms a toner image based on the image data, and transfers the toner image onto the conveyed paper. The image forming unit 104 includes, for example, a photosensitive drum, a charging unit, a developing unit, a cleaning unit, and the like (not shown). The image forming unit 104 forms a toner image based on image data acquired by the image reading unit 101, image data received from the computer 200, or the like. Specifically, in the toner image formation, the charging unit charges the surface of the photosensitive drum to a predetermined potential. The exposure unit turns on and off a semiconductor laser device (not shown) according to the image data, and scans and exposes the charged photosensitive drum. The developing unit stores toner and charges the toner to a predetermined potential. Further, the developing unit causes the toner to fly and supplies the toner to the electrostatic latent image. As a result, the electrostatic latent image is developed as a toner image. The cleaning unit is in contact with the photosensitive drum and collects and removes residual toner and the like.

  The fixing unit 105 includes, for example, a heating roller that incorporates a heating element and a pressure roller that presses the heating roller. The fixing unit 105 passes the sheet on which the toner image is transferred between both rollers, and fixes the toner image on the sheet. When the fixing is completed, printing of one sheet is completed, and the printed sheet is discharged outside the apparatus.

  In addition, the multifunction device 100 is provided with a communication unit 106 that communicates with the external computer 200. The communication unit 106 receives image data to be printed and setting data for printing from the computer 200.

  The MFP 100 includes a control unit 10 for controlling operations of the image reading unit 101, the paper feeding unit 102, the conveyance path 103, the image forming unit 104, the fixing unit 105, the communication unit 106, and the like of the MFP 100. Is provided.

  For example, the control unit 10 is provided with a CPU 10a and a ROM 10b as a storage device. In the multifunction device 100, the HDD 10 c is connected to the control unit 10 so as to be communicable. The CPU 10a is a central processing unit of the multifunction peripheral 100, and performs various computations based on control programs and data read from the ROM 10b and the HDD 10c to control each part of the multifunction peripheral 100. The ROM 10b and the HDD 10c store various data such as a control program, control data, and image data of the multifunction peripheral 100.

  The control unit 10 is provided with a memory module 2 as a RAM. The memory module 2 can store control programs and various data read from the ROM 10b and the HDD 10c, data received by the communication unit 106 from the computer 200, and image data generated by reading by the image reading unit 101. . Further, the control unit 10 is provided with a memory control device 1 that controls reading and writing of data in the memory module 2. The CPU 10a performs various processes based on data and programs developed in the memory module 2.

  The control unit 10 is connected to each unit such as the image reading unit 101, the paper feeding unit 102, the conveyance path 103, the image forming unit 104, the fixing unit 105, and the communication unit 106 of the multifunction peripheral 100, and printing is performed appropriately. Thus, the operation of each unit is controlled.

(Outline of memory control device 1)
Next, the outline of the memory control device 1 according to the present embodiment will be described with reference to FIG. FIG. 2 is a block diagram illustrating an example of a memory system 300 including the memory control device 1.

  The memory system 300 includes, for example, a memory control device 1, an SDRAM I / F 3, a memory module 2, and the like.

  The memory control device 1 is connected to the CPU 10a, the ROM 10b, and the HDD 10c via a bus. For example, the memory control device 1 controls data exchange between the memory module 2 and the CPU 10a. The memory control device 1 controls reading and writing of data and programs between the memory module 2 and the ROM 10b and HDD 10c.

  As shown in FIG. 2, the SDRAM I / F 3 is connected to the memory control device 1. For example, the SDRAM I / F 3 includes a data buffer and a socket for the memory module 2. The memory module 2 is connected to the SDRAM I / F 3. Although FIG. 2 shows an example in which one memory module 2 is provided, two or more memory modules 2 may be provided.

  The SDRAM I / F 3 is an interface between the memory control device 1 and the memory module 2. The SDRAM I / F 3 buffers data to be written under the control of the memory control device 1. The SDRAM I / F 3 writes data or the like in the memory module 2. The SDRAM I / F 3 reads data to be read from the memory module 2, buffers it, and outputs it to the memory control device 1.

  The memory module 2 includes a plurality of memory chips 4. The memory module 2 is attached to a memory module 2 socket (not shown) on a substrate on which the control unit 10 is provided. The memory chip 4 in the memory module 2 is, for example, a DDR3 SDRAM. For example, the memory module 2 is a substrate on which a plurality of DDR3 SDRAM memory chips 4 are mounted while being wired.

  In the memory module 2, a plurality of ranks 5 are provided with a plurality of memory chips 4 as one unit. Rank 5 is a unit in which the memory control device 1 inputs and outputs data. For example, the number of rank 5 is 2, 4 or the like. For example, all the memory chips 4 arranged on the front side of the memory module 2 can be set as one rank 5, and all the memory chips 4 arranged on the back side of the memory module 2 can be set as the other rank 5.

  Each memory chip 4 in the memory module 2 includes a configuration setting register 6. The memory control device 1 issues a command for setting the operation of each memory chip 4 (details will be described later). The configuration setting register 6 stores a command for setting the operation of each memory chip 4 issued by the memory control device 1. Each memory chip 4 operates based on the setting stored in the configuration setting register 6. As a result, the memory chip 4 can be programmed according to various functions, functions, and modes, and each memory chip 4 can be operated according to an application.

(Configuration of memory control device 1)
Next, the internal configuration of the memory control device 1 according to the embodiment will be described with reference to FIG. FIG. 3 is a block diagram illustrating an example of the internal configuration of the memory control device 1.

  The memory control device 1 includes a device manager 11, an arbiter (arbitration unit) 12, a refresh unit 13, a host I / F 14, an OPBI / F 15, a queuing unit 16 (queue buffer), a command issuing unit 17 (command dispatcher), and a command generator. Unit 18, strobe generation unit 19, and clock generation unit 191.

  The device manager 11 performs processing related to management of the memory module 2 and each memory chip 4. For example, the device manager 11 outputs a power down request command for setting any one of the memory modules 2 to the power saving mode to the arbiter 12. In addition, the device manager 11 receives a state transition command from the command issuing unit 17. In addition, the device manager 11 outputs various requests for changing the state of each memory bank to the command issuing unit 17.

  The arbiter 12 accepts a refresh request from the refresh unit 13, a memory access request from the host I / F 14, and a direct command request from the OPBI / F 15. The refresh unit 13 transmits a refresh request to the arbiter 12. The host I / F 14 receives a memory access request from the CPU 10 a and transmits it to the arbiter 12. In addition, the host I / F 14 outputs the data read from the memory module 2 by the strobe generation unit 19 to the CPU 10a, the HDD 10c, and the like. In addition, the host I / F 14 receives data to be written to the memory module 2 from the CPU 10 a, ROM 10 b, HDD 10 c, and the like, and transmits the data to the strobe generation unit 19.

  An OPBI / F 15 (On-chip Peripheral Bus I / F) receives a direct command request from the CPU 10 a or the like and transmits it to the arbiter 12. The OPBI / F 15 is provided with an address mirror setting unit 151 for storing and holding information (address mirror information) indicating the presence / absence of an address mirror in each memory chip 4 (details of the address mirror will be described later).

  The address mirror setting unit 151 receives information indicating the presence or absence of the address mirror of each rank 5 or each memory chip 4 from the CPU 10a or the ROM 10b, for example, and holds the information so that each unit in the memory control device 1 can refer to it. For example, the queuing unit 16, the command issuing unit 17, and the command generating unit 18 refer to information indicating the presence / absence of an address mirror in each memory chip 4 held in the address mirror setting unit 151.

  The arbiter 12 registers these requests as transactions in the queuing unit 16. The queuing unit 16 stores the transaction from the arbiter 12.

  The command issuing unit 17 accepts various requests output from the device manager 11 and dispatches these requests. Then, the command issuing unit 17 transmits (issues) a command generation request corresponding to the dispatched request to the command generation unit 18 and causes the command generation unit 18 to generate a command for each rank 5 and each memory chip 4. The command issuing unit 17 reads a ROW command request, a ROW address designation request, a COL command request, a COL address designation request, and the like output from the queuing unit 16. The command issuing unit 17 transmits these requests to the command generating unit 18.

  The command generation unit 18 receives a command generation request, a ROW command request, a ROW address designation request, a COL command request, a COL address designation request, and the like transmitted from the command issuing unit 17. Then, the command generator 18 generates a control command or the like for controlling the memory module 2.

  The command generation unit 18 outputs the generated command to the SDRAM I / F 3. For example, the command generation unit 18 includes MCS (Memory Chip Select) _b, RAS (Row Address Strobe) _b, CAS (Column Address Strobe) _b, MWE (Memory Write Enable) _b, BA (Bank Address), MA (Memory Address). ) And CKE (Clock Enable) signals are transmitted as commands to the SDRAM I / F 3. The command generator 18 outputs the generated command to the strobe generator 19. The command generator 18 outputs a control command to the SDRAM I / F 3 and simultaneously outputs a data transfer trigger to the strobe generator 19.

  The strobe generation unit 19 writes data to the memory module 2 (memory chip 4) to which data is to be written in accordance with the data transfer trigger from the command generation unit 18. The strobe generation unit 19 reads data from the memory module 2 (memory chip 4) that is a data reading target. The strobe generation unit 19 outputs signals such as DQOUT (data signal output), DQIN (data signal input), DQSOUT (output data strobe signal), DQSIN (input data strobe signal), DM (Data Mask), and the like to SDRAMI. Send / receive to / from F3.

(Address mirror)
Next, based on FIG. 4, the presence / absence of an address mirror in each memory chip 4 according to the present embodiment will be described. FIG. 4 is an explanatory diagram for explaining the address mirror.

  In the DDR3-SDRAM, in order to match the chip trace length (line length) and improve the signal quality on the memory module 2, the memory signal lines (addresses) can be switched and connected. In the DDR3 standard, signal lines to be exchanged are signal lines having pin names A3 to A8, BA0, and BA1, as shown in FIG.

  Specifically, rank 0 in FIG. 4 indicates a pin connection relationship with the memory chip 4 when there is no exchange of wiring and no address mirror. In other words, rank 0 in FIG. 4 is a normal wiring. On the other hand, rank 1 in FIG. 4 indicates the relationship of pin connection to the memory chip 4 when the wiring is replaced and the address mirror is provided. For example, the A3 signal line is connected to the A4 signal line in the memory chip 4, and the A4 signal line is connected to the A3 signal line in the memory chip 4. Thus, for example, in the memory chip 4 of the DDR3, an address mirror for exchanging signal lines can be performed.

(Operation setting command for memory chip 4)
Next, an example of the operation setting command of each memory chip 4 according to the present embodiment will be described with reference to FIG. FIG. 5 is an explanatory diagram showing an example of the operation setting command of each memory chip 4.

  In the DDR3-SDRAM, in addition to data read and write, commands for setting the mode and parameters of the memory chip 4 are prepared. With this command, the behavior of the memory chip 4 (SDRAM chip) can be defined. This command is called an MRS command (corresponding to a setting command).

  In the DDR3-SDRAM, four types of mode register sets MR0 to MR3 are prepared. For example, when initializing each memory chip 4 when the main power is turned on or changing the operation setting of the memory chip 4, an MRS command is generated and applied to the memory chip 4 that is the target of the MRS command. For example, the MRS command is given in units of rank 5 in the memory module 2. The MRS command is stored in the configuration setting register 6 in each memory chip 4, and each memory chip 4 operates according to the instruction (contents) of the MRS command.

  Upon receiving an instruction from the CPU 10a, the queuing unit 16 registers the transaction of rank 5, the memory chip 4, and the MRS command that are targets of the MRS command. The command issuing unit 17 in the memory control device 1 receives information (target information) indicating the rank 5 and the memory chip 4 that are targets of the MRS command from the queuing unit 16 and also receives a setting command issue request. Then, the command issuing unit 17 issues an MRS command generation request to rank 5 that is the target of the setting command. Upon receiving this MRS command issuance instruction, the command generator 18 generates an MRS command for rank 5 that is the target of the setting command. Then, the command generation unit 18 transmits the MRS command to rank 5 (memory chip 4) that is the target of the MRS command.

  Therefore, an example of operation setting for each rank 5 (memory chip 4) will be described with reference to FIG. 5 by taking the MRS command of MR0 out of the four types of mode register sets prepared.

  As shown in FIG. 5, in the MRS command, signal lines A0 to A15 and BA0 to BA2 connected to the command generation unit 18 are used. With the MR0 MRS command, the burst length (BL) can be set using the signal lines A0 and A1 shown in FIG. 5 (the burst length can be set to 8 or 4). The burst type (BT) can be set using the A3 signal line. Further, CAS latency (the number of delay cycles from when the read command becomes valid until data is actually output, CL) can be set using the signal lines A2, A4 to A6. Further, a test mode (a test mode for producers, TM) can be set using the A7 signal line. Further, the DLL reset (reset of the DLL circuit in the memory chip 4, DLL) can be set using the A8 signal line. Also, write recovery (WR) can be set using the signal lines A9 to A11. Also, precharge power down (PPD) can be set using the A12 signal line. The signal lines BA0 to BA2 are used to indicate which mode register set the MRS command is.

  In addition, with the MRS commands MR1 to MR3, various settings such as the output impedance, write latency, and termination resistance value of the memory chip 4 can be made (for details, refer to the above-mentioned JEDEC standard JEDEC Standard JESD79-3D).

  Here, among signals A0 to A15 and BA0 to BA2 of signal lines (addresses) used for setting the operation (behavior) of the memory chip 4 included in each rank 5, signals A3 to A8, BA0 and BA1. Lines may be replaced by address mirrors. In normal read and write, even if the wiring is switched (incorrect), the addresses correspond one-to-one, so there is no need to be aware of the switching of the wiring.

  However, commands such as the MRS command are commands that give special meaning to the address itself. For example, when the operation of the memory chip 4 with the address mirror and the operation of the memory chip 4 without the address mirror are set in the same manner (when the same MRS command is given), the MRS command to the memory chip 4 without the address mirror is used as it is in the address mirror. If it is given to a certain memory chip 4, the setting contents are completely different between the memory chip 4 without an address mirror and the memory chip 4 with an address mirror by changing the wiring.

  Therefore, when the MRS command is given to the memory chip 4 having the address mirror, the MRS command must be generated in consideration of the replacement of the wiring.

(Automatic command split issue)
Next, an example of automatic command division issue in the memory control device 1 of the present embodiment will be described with reference to FIGS. 3 and 6 to 8. FIG. 6 is a timing chart showing an example of command issuance when the presence or absence of address mirrors is not mixed. FIG. 7 is a timing chart showing an example of conventional command issuance when the presence or absence of address mirrors is mixed. FIG. 8 is a timing chart showing an example of command issuance in the memory control device 1 of the present embodiment when the presence or absence of address mirrors is mixed.

  First, in FIG. 6 to FIG. 8, “tfRCommand” indicates a command issue request transmitted from the queuing unit 16 to the command issuing unit 17. In this example, this command issue request corresponds to an MRS command, and an MRS command is generated based on this command issue request. “800” in FIGS. 6 to 8 means the MRS command (contents). “TfRDDevice” indicates a list of rank 5 (memory chip 4) that is a target of command issuance. In this description, each bit of “tfRDDevice” corresponds to rank 5 in the memory module 2.

  Here, rank 5 is a unit for inputting and outputting data from the SDRAM of the memory module 2. As described with reference to FIG. 2, the memory module 2 of the present embodiment has a plurality of ranks 5. Even if the memory module 2 physically occupies only one memory slot, if it has a plurality of ranks 5, the memory control device 1 treats the memory modules 2 as many as five ranks. “TfRBunk” is a decode signal output from the queuing unit 16 to the command issuing unit 17 and is finally re-encoded and supplied to the memory module 2.

  6 to 8, “cdCommand” indicates a command generation request transmitted from the command issuing unit 17 to the command generating unit 18. In this example, this command generation request corresponds to an MRS command, and an MRS command is generated based on this command generation request. Specifically, “800” in FIGS. 6 to 8 means an MRS command (contents). “CdDevice” is a signal that the command issuing unit 17 gives to the command generating unit 18 and indicates a list of rank 5 (memory chip 4) that is a target of the command. In this description, “cdDevice” also corresponds to rank 5 in the memory module 2 in the same manner as “tfRDDevice”. Further, “cdBank” is a signal that the command issuing unit 17 gives to the command generating unit 18 and, like “tfRBunk”, is a decode signal that the command issuing unit 17 gives to the command generating unit 18 and is finally reproduced. It is encoded and supplied to the memory module 2.

[When there are no mixed address mirrors in each rank 5]
First, with reference to FIG. 6, the issue of the MRS command when the presence or absence of address mirrors is not mixed in each memory chip 4 included in rank 5 will be described. In the following description, an example in which a similar MRS command is issued to each memory chip 4 included in rank 5 will be described. Further, for example, when the presence or absence of address mirrors is not mixed in each rank 5, each rank 5 is only rank 5 (memory chip 4) having no address mirror.

  For example, the queuing unit 16 queues the MRS command based on an instruction from the CPU 10a or the like. Then, the queuing unit 16 issues a command issuance request for the MRS command to the command issuing unit 17 (for example, “800” of tfRCommand in FIG. 6; time point T1 in FIG. 6). In addition, the queuing unit 16 responds to a command issuance request of the MRS command with tfRDDevice (“f” in FIG. 6, target information) or tfRBunk (in FIG. 6) as information indicating the rank 5 targeted by the MRS command. "4") is transmitted (at time T1 in FIG. 6).

  If the presence or absence of the address mirror is not mixed in each memory chip 4 included in the rank 5, it is not necessary to consider the replacement of the wiring. Therefore, in response to a command issue request from the queuing unit 16, the command issue unit 17 issues a command generation request for the MRS command to the command generation unit 18 (for example, “800” of cdCommand in FIG. 6). 6 from T2 to T3). Also, the command issuing unit 17 sends cdDevice (“f” in FIG. 6, target information) or cdBank (in FIG. 6) as information indicating the rank 5 that is the target of the MRS command in accordance with the command generation request of the MRS command. “4” is transmitted to the command generation unit 18 (section from T2 to T3 in FIG. 6) As described above, if the presence or absence of the address mirror is not mixed, the queuing unit 16 and the command issuing unit 17 It is sufficient to issue a command request once for all ranks 5 (all memory chips 4).

  Then, in response to the MRS command issued from the command issuing unit 17, the command generating unit 18 generates a command (signal) to be given to the memory module 2. Then, the command generation unit 18 transmits (gives) the generated command (signal) to the SDRAM I / F 3 (memory module 2). As a result, the memory module 2 sequentially receives MRS commands after time T0 in FIG.

[When the presence or absence of address mirror is mixed in each rank 5 (conventional reference example)]
Next, with reference to FIG. 7, the conventional issuance of MRS commands when the presence / absence of address mirrors is mixed in each memory chip 4 included in rank 5 will be described. In the following description, an example in which a similar MRS command is issued to each memory chip 4 included in rank 5 will be described.

  First, the queuing unit 16 queues an MRS command based on an instruction from the CPU 10a or the like. Then, the queuing unit 16 issues a command issuance request for the MRS command to the command issuance unit 17 (for example, “800” of tfRCommand in FIG. 7; time point T3 in FIG. 7). Further, the queuing unit 16 sends tfRDDevice (“f” in FIG. 7) and tfRBunk (“4” in FIG. 7) as information indicating the rank 5 that is the target of the MRS command in response to the MRS command issuance request. ) Is transmitted (at time T4 in FIG. 7).

  If the presence or absence of an address mirror is mixed in each memory chip 4 included in the rank 5, in order to reliably set the operation of the memory chip 4, it is necessary to consider the replacement of wiring. Therefore, conventionally, when issuing a request regarding the MRS command, the command issuing unit 17 and the queuing unit 16 confirm the contents of the address mirror setting unit 151 (address mirror information), and the rank 5 targeted by the MRS command is the address. A process is performed to check whether or not there is a mirror. When they are mixed, the command issuing unit 17 and the queuing unit 16 perform processing for distinguishing between rank 5 (memory chip 4) without an address mirror and rank 5 (memory chip 4) with an address mirror.

  Then, for example, the command issuing unit 17 only applies to rank 5 (memory chip 4) having no address mirror among a plurality of ranks 5 (memory chips 4) that are subject to command issue requests from the queuing unit 16. Alternatively, an MRS command generation request is issued to the command generation unit 18 only for rank 5 (memory chip 4) having an address mirror.

  For example, the command issuing unit 17 issues a command generation request for the MRS command to the command generating unit 18 (for example, “800” of cdCommand in FIG. 7; a section from T5 to T6 in FIG. 7). In addition, the command issuing unit 17 sets cdDevice (“d” in FIG. 7, which is either “d” in FIG. 7 or no rank in the address mirror) as information indicating the rank 5 targeted by the MRS command in accordance with the command generation request of the MRS command. One is shown) and cdBank ("4" in FIG. 7) is transmitted to the command issuing unit 17 (T5 to T6 in FIG. 7).

  Then, for example, the command issuing unit 17 causes the queuing unit 16 to prepare an MRS command issue request for rank 5 that has not been issued an MRS command among ranks 5 that are subject to the command issue request of the MRS command. In other words, the command issuing unit 17 causes the queuing unit 16 to newly register a transaction of an MRS command for rank 5 for which no MRS command has been issued. For example, if the command issuing unit 17 removes rank 5 with an address mirror in the previous command generation request from ranks 5 that are subject to the MRS command (rank 5 with no MRS command issued is an address mirror). If there is a rank 5), the queuing unit 16 replaces the address of the command issuance request of the previously issued MRS command (an MRS command for rank 5 without an address mirror) in consideration of the wiring replacement by the address mirror. Processing for newly preparing a transaction of the MRS command is performed.

  After these processes are completed, the queuing unit 16 makes a command issuance request to the command issuing unit 17 for rank 5 where the MRS command has not been issued. Specifically, the queuing unit 16 issues a command issuance request for a new MRS command in consideration of the replacement of the address of the MRS command to the command issuing unit 17 (for example, “800 ′” of tfRCommand in FIG. 7). “800 ′” is an MRS command (after address conversion) in consideration of replacement of a signal line by a command mirror (at time T7 in FIG. 7). Further, the queuing unit 16 responds to an MRS command issue request by using tfRDDevice (“2” in FIG. 7) or tfRBunk (“4” in FIG. 7) as information indicating the unissued rank 5 that is the target of the MRS command. ]) Is transmitted (at time T7 in FIG. 7).

  Upon receiving this command issuance request, for example, the command issuance unit 17 issues a command generation request for the MRS command to the command generation unit 18 (cd command “800 ′” in FIG. 7; T8 to T9 in FIG. 7). ). Further, the command issuing unit 17 transmits cdDevice (“2” in FIG. 7) and cdBank (“4” in FIG. 7) to the command generating unit 18 as information indicating the unissued rank 5 in accordance with the MRS command. (Interval from T8 to T9 in FIG. 7).

  As described above, when rank 5 having no address mirror and rank 5 having an address mirror are mixed among ranks 5 included in the memory module 2, the queuing unit 16 and the command issuing unit 17 determine whether there is an address mirror. The software performs special processing such as confirmation of the MRS command and generation of a request for a new MRS command in which the address is exchanged, issuance of an MRS command request for rank 5 without an address mirror, and MRS for rank 5 with an address mirror. A command request was issued. In other words, the operations of the queuing unit 16 and the command issuing unit 17 are operations that repeat the MRS command waveform when there is no address mirror twice.

  Since the queuing unit 16 and the command issuing unit 17 perform processing in software, a time point of starting issuing a command for rank 5 without an address mirror (T5) and a time point of starting issuing commands for rank 5 having an address mirror (T8) ) Is required at certain intervals. Therefore, conventionally, it has not been possible to continuously issue requests for MRS commands to rank 5 without an address mirror and rank 5 with an address mirror. Therefore, the generation of the MRS command in the command generation unit 18 is also separated in time.

[When the presence or absence of address mirrors is mixed in each rank 5 (this embodiment)]
Next, issuance of an MRS command when the presence or absence of an address mirror is mixed in a plurality of ranks 5 included in the memory module 2 according to the present invention will be described with reference to FIG. In the following description, an example in which a similar MRS command is issued to each rank 5 in the memory module 2 will be described.

  First, in the present invention, the command generation unit 18 includes an address conversion unit 181 that converts the address of the MRS command for rank 5 having no address mirror into the address of the MRS command for rank 5 having an address mirror. The address conversion unit 181 may alternatively convert the address of the MRS command for rank 5 having an address mirror into the address of the MRS command for rank 5 having no address mirror.

  By the automatic conversion processing of the address of the MRS command by the address conversion unit 181, even if the presence / absence of address mirrors is mixed in a plurality of ranks 5 included in the memory module 2, consideration is given to incorrect wiring in the address mirrors. Then, the queuing unit 16 and the command generation unit 18 perform software processing for converting the address for rank 5 having the address mirror of the MRS command, or processing for creating a separate command transaction for rank 5 having the address mirror. You don't have to.

  Therefore, in the present invention, first, the queuing unit 16 queues the MRS command based on an instruction from the CPU 10a or the like. For example, the queuing unit 16 issues a command issuance request for the MRS command to the command issuing unit 17 (for example, “800” of tfRCommand in FIG. 8; time point T10 in FIG. 8). Further, the queuing unit 16 confirms the address mirror information in the address mirror setting unit 151, and in accordance with the MRS command issuance request, the queuing unit 16 has two types of tfRDDevice as information indicating the rank 5 targeted by the MRS command. The signal is continuously transmitted to the command issuing unit 17. The information indicating the rank 5 that is the target of these two types of MRS commands corresponds to the first rank information and the second rank information, and “f” in FIG. 8 is issued at time T10, and “2” is displayed at T11. It is emitted at the time (in the past, two types of tfRDDevice signals are transmitted at a time interval).

  Since software processing such as address translation is unnecessary, the queuing unit 16 automatically divides the MRS command issuance request of rank 5 without address mirror and rank 5 with address mirror, and these two types of tfRDDevice signals. (First rank information and second rank information) can be issued continuously. In addition, the queuing unit 16 transmits tfRBunk (“4” in FIG. 8) (at time T10 in FIG. 8).

  Upon receiving a command issuance request from the queuing unit 16, the command issuance unit 17 confirms the address mirror setting unit 151 and issues a command generation request for the MRS command for rank 5 having no address mirror to the command generation unit 18. (For example, “800” of cdCommand in FIG. 8. T12 to T13). Further, the command issuing unit 17 sends cdDevice (“d” in FIG. 8) or cdBank (in FIG. 8) as information indicating rank 5 without an address mirror that is the target of the MRS command in response to the command generation request of the MRS command. "4") is transmitted to the command generator 18 (T12 to T13).

  The command issuing unit 17 then issues a command generation request for the MRS command for rank 5 having an address mirror to the command generation unit 18 (cd command “800” in FIG. 8, period T14 to T15). In addition, in response to the MRS command generation request, the command issuing unit 17 uses cdDevice (“2” in FIG. 8) or cdBank (in FIG. 8) as information indicating the rank 5 having the address mirror targeted by the MRS command. "4") is transmitted to the command generator 18 (T14 to T15).

  Note that the section in which the signals T13 to T14 are not issued is the minimum waiting time until cdCommand, cdDevice, and cdBank are issued in response to switching of the tfRDDevice signal at the time T11. Therefore, the command issuing unit 17 issues a command generation request for the MRS command to rank 5 with no address mirror and rank 5 with an address mirror in the shortest possible time.

  Here, the values in the MRS command request generated by the queuing unit 16 and the command generation unit are address conversion processing performed by the address conversion unit 18, so that the rank 5 with no address mirror and the rank 5 with an address mirror are included. In either case, the same may be applied.

  Then, in response to the MRS command generation request issued from the command issuing unit 17, the command generation unit 18 generates an MRS command (signal) to be given to the memory module 2. Then, the command generation unit 18 transmits the generated command (signal) to the SDRAM I / F 3 (memory module 2). As a result, the memory module 2 sequentially receives MRS commands after time T01 in FIG.

  Specifically, the command generation unit 18 confirms the address mirror information of the address mirror setting unit 151, and confirms rank 5 with no address mirror and rank 5 with an address mirror. In response to a command generation request for rank 5 without an address mirror, the command generation unit 18 generates an MRS command (ordinary command) that does not perform address conversion for rank 5 without an address mirror. The command generation unit 18 transmits the MRS command generated toward rank 5 (memory chip 4) without an address mirror to the SDRAM I / F 3.

  On the other hand, the address conversion unit 181 confirms the address mirror information of the address mirror setting unit 151. If rank 5 targeted by the MRS command generation request is rank 5 with an address mirror, the address conversion unit 181 converts the address of the MRS command for rank 5 without an address mirror, and rank with an address mirror. MRS command for 5 is generated. Then, the command generation unit 18 transmits the MRS command generated toward the rank 5 (memory chip 4) having the address mirror generated by the address conversion unit 181 to the SDRAM I / F 3. As a result, the intended MRS command is smoothly applied to each rank 5 (each memory chip 4) regardless of the presence or absence of the address mirror, and the operation of each memory chip 4 of each rank 5 is set.

  In this manner, the memory control device 1 according to the present embodiment includes the queuing unit 16 that queues commands for the memory module 2 that includes the plurality of memory chips 4 including the configuration setting register 6 for setting the operation. The address mirror setting unit 151 that holds address mirror information indicating the presence / absence of an address mirror in the memory chip 4 and the command issue request from the queuing unit 16 and the target information indicating the memory chip 4 to be commanded Based on the command issued by the command issuing unit 17 that issues a command to the memory chip 4 and the command issuing unit 17, the command for the memory chip 4 is generated and given to the memory chip 4, and the wiring is switched by the address mirror. Setting using the target signal line And a command generation unit 18 for giving a setting command for setting the configuration register to the memory chip 4. The command generation unit 18 performs the same setting for the memory chip 4 without the address mirror and the memory chip 4 with the address mirror. When giving a command, a process for giving a setting command generated for the memory chip 4 without the address mirror is performed based on the address mirror information and the target information, and the memory chip 4 with the address mirror is replaced by the address mirror. An address conversion unit 181 that converts an address of a setting command (for example, a setting command for a memory chip 4 without an address mirror) in accordance with the received signal line and generates a setting command for the memory chip 4 with an address mirror. .

  As a result, the address conversion unit 181 as hardware automatically converts the address of the setting command for the memory chip 4 having the address mirror. In other words, if the command issuing unit 17 issues target information indicating the memory chip 4 that is the target of the setting command and a setting command generation request, the command generating unit 18 automatically issues a setting command according to the presence or absence of the address mirror. To the memory chip 4.

  In this way, the command issuing unit 17 and the queuing unit determine the presence / absence of an address mirror by software, and issue a request for a setting command separately (divided into multiple times) according to the presence / absence of an address mirror, It is not necessary to perform address conversion or the like, and setting commands can be continuously given to the memory chip 4 with the address mirror and the memory chip 4 without the address mirror. In other words, since software processing such as address conversion is not required, it is possible to automatically divide and process setting command issuance for the memory chip 4 with an address mirror and the memory chip 4 without an address mirror. Therefore, the initialization of the memory chip 4 and the operation setting process can be simplified. Further, even if the memory chip 4 with the address mirror and the memory chip 4 without the address mirror are mixed in the memory module 2, the control flow such as initialization can be shared.

  The address mirror setting unit 151 holds address mirror rank information indicating the presence or absence of the rank 5 address mirror in the memory module 2, and the rank 5 including the memory chip 4 with the address mirror and the memory chip 4 without the address mirror. When a similar setting command is generated for each rank 5 of the memory module 2 including the rank 5, the queuing unit 16 indicates the rank 5 having no address mirror in accordance with the setting command issuance request as target information. The first rank information and the second rank information indicating the rank 5 with the address mirror are transmitted to the command issuing unit 17, and the command issuing unit 17 sends the first rank information and the second rank information to the command generating unit 18 together with the setting command. The address conversion unit 181 sends the address mirror setting unit 15 For the memory chip 4 having the address mirror, the address of the setting command for the rank 5 without the address mirror is converted according to the replaced signal line based on the information held by the first rank information and the second rank information. Generate configuration commands.

  Thereby, the command issuance for each rank 5 is automatically divided according to the presence or absence of the address mirror. Therefore, even if rank 5 with an address mirror and rank 5 without an address mirror are mixed in the memory module 2, the presence / absence of the address mirror is determined by software separately (divided into multiple times). It is not necessary to issue a setting command according to the presence or absence, and initialization of the memory chip 4 in the same rank 5 and simplification of operation setting can be achieved.

  The queuing unit 16 continuously transmits the first rank information and the second rank information to the command generation unit 18 together with the setting command issue request, and the command issue unit 17 transmits the setting command to the command generation unit. 18 and the second rank information is issued to the command generator 18 following the first rank information.

  As a result, when the setting command is issued to a plurality of ranks 5, the setting command is continuously issued to each of rank 5 having no address mirror and rank 5 having an address mirror. As a result, even if rank 5 with address mirror and rank 5 without address mirror are mixed, a setting command can be issued promptly and a command can be generated.

  The embodiment of the present invention has been described above, but the scope of the present invention is not limited to this, and various modifications can be made without departing from the spirit of the invention.

  The present invention is applicable to a memory control device.

DESCRIPTION OF SYMBOLS 1 Memory control apparatus 151 Address mirror setting part 16 Queuing part 17 Command issuing part 18 Command generation part 181 Address conversion part 2 Memory module 4 Memory chip 5 Rank 6 Configuration setting register

Claims (3)

A queuing unit for queuing a command for a memory module including a plurality of memory chips including a configuration setting register for setting an operation;
An address mirror setting unit for holding address mirror information indicating the presence or absence of an address mirror in the memory chip;
A command issuing unit that issues a command generation request for the memory chip according to the command issuing request from the queuing unit and target information indicating the memory chip to be commanded;
Based on a command generation request issued by the command issuing unit, a command for a memory chip is generated and a command is given to the memory chip, and the setting configuration register is set by using a signal line whose wiring is to be replaced by an address mirror. A command generation unit for giving a setting command to the memory chip,
When the command generation unit gives the same setting command to a memory chip without an address mirror and a memory chip with an address mirror, based on the address mirror information and the target information, the command generation unit is directed toward the memory chip without an address mirror. For the memory chip having the address mirror, the address of the setting command is converted to the memory chip having the address mirror by converting the address of the setting command according to the signal line exchanged by the address mirror. A memory control device comprising an address conversion unit for generating the setting command. The address mirror setting unit holds address mirror rank information indicating the presence or absence of a rank address mirror in the memory module;
When generating the same setting command for each rank of a memory module including a rank consisting of a memory chip with an address mirror and a rank consisting of a memory chip without an address mirror,
The queuing unit transmits, as the target information, first rank information indicating a rank without an address mirror and second rank information indicating a rank with an address mirror to the command issuing unit in accordance with a request for issuing the setting command. ,
The command issuing unit transmits the first rank information and the second rank information to the command generation unit together with the generation request for the setting command,
The address conversion unit, based on the information held by the address mirror setting unit, the first rank information, and the second rank information, the address of the setting command for a rank without an address mirror according to the replaced signal line 2. The memory control device according to claim 1, wherein the setting command is generated for a memory chip having an address mirror by converting the above. The queuing unit continuously transmits the first rank information and the second rank information to the command issuing unit together with the setting command issue request,
The command issuing unit issues the setting command generation request to the command generation unit, and sends the second rank information to the command generation unit following the first rank information in accordance with the setting command generation request. The memory control device according to claim 2, wherein the memory control device transmits.

Images