JP5453687B2 - Extremely low voltage oscillation circuit and extremely low voltage DCDC converter using the same - Google Patents

Description

  The present invention relates to a DCDC converter using energy harvesting energy such as single-cell or parallel-cell solar cells and fuel cells, and an oscillation circuit that operates reliably at an extremely low voltage.

  Promoting the use of non-carbon energy is a very important issue. Energy harvesting that generates electricity from renewable non-carbon energy sources such as solar power generation, thermal power generation, radio power generation, vibration power generation, wind power generation, etc. has been taken up as a major development theme. The generated energy is distributed as electric power or charged and stored in a secondary battery such as a lithium battery.

When charging, the charging current and charging voltage need to be managed accurately. Secondary batteries cause failures such as ignition or destruction due to abnormal charging current or charging voltage.

Most of the environmental power sources do not output at a very low voltage.
For example, it is known that the energy generated by a single cell solar cell has a maximum power point that outputs maximum power.

The maximum power point voltage is very low, about 0.25V to 0.45V, and it has not been provided in an ordinary manufacturing process to realize a circuit that operates normally in an ordinary manufacturing process in an integrated circuit. Therefore, it was necessary to increase the generated voltage by connecting solar cells in series.

For this reason, a processing step of cutting the solar cell with a laser and connecting it with wiring is necessary, which increases the cost of the solar cell panel.

In addition, solar cells connected in series do not generate power if they are hidden behind one of the series cells. It is necessary to take measures against partial shadows.

An additional control circuit for avoiding this partial shadow problem is required, which also causes an increase in cost. In view of cost and convenience, the necessity of a circuit that operates from an extremely low voltage of a single cell has become important.

The present invention is intended to contribute to energy saving of the earth by generating electricity from energy that does not generate CO ₂ in chargers and power supply devices used in all electronic devices.

Various proposals have been made for use with single-cell solar cells. However, no proposal has been found for starting up and operating completely in a single cell, requiring a separate high voltage source for starting up, requiring an expensive manufacturing process, or starting up.

  The present invention can be manufactured in a normal manufacturing process, and starts to oscillate reliably from a very low voltage power source to extract energy from a single cell solar cell without any increase in solar panel manufacturing costs. To achieve a DCDC converter.

  Examples of the prior art for realizing extremely low voltage operation include the following. These have achieved a certain degree of operation and are effective. However, in the case of an analog circuit, if the operation is performed below the threshold value VTH, a large temperature fluctuation of the operating point and output is inevitable, and it has not been widely used.

  US Publication No. US2009 / 0146749 related to Patent Document 1 introduces an oscillation circuit that generates a trigger signal at an extremely low voltage. However, since there is no mention of a method of stabilizing fluctuations with respect to temperature, Large characteristic variations are foreseen.

  US Patent Publication US4542330 related to Patent Document 2 proposes a blocking transmitter that generates a trigger signal at a low voltage, but the voltage is 0.9 V or more and cannot be applied to a single cell solar cell or the like.

In Japanese Patent Publication No. 2006-020491 related to Patent Document 3, a trigger circuit that oscillates at a first extremely low voltage is generated by boosting a voltage from an extremely low voltage by a charge pump circuit and operating a second main booster circuit. It doesn't touch on the measures.

According to Japanese Patent Publication No. 4223041 related to Patent Document 4, a solar cell panel that outputs a high voltage using two types of solar cells is connected to a start signal generation and is switched between a very low voltage solar cell and a diode, but by a diode. It is clear that the voltage drop as large as the generation voltage is not mentioned and that it is not a single cell is a hindrance to practical use.

In Patent Publication No. 2007-135352 related to Patent Document 5, the start-up starts with the remaining power of the rechargeable battery and the power is generated by the solar battery after the start-up, but once the rechargeable battery is discharged, the start-up will start again. There is no problem.

US Publication US2009 / 0146749 US Patent Publication US4542330 Patent Publication 2006-020491 Patent Publication 4223041 Patent Publication No. 2007-135352

  When an energy harvesting element such as a solar cell or a fuel cell has a very low output voltage of 0.2 V to 0.6 V in a single cell and boosts the voltage to store energy in the secondary battery, the booster circuit is set to 0. It is necessary to start the boosting operation from an extremely low voltage region from about 2V. In order to boost the voltage, a pulse signal that starts operation is essential at start-up. The present invention uses the FET subthreshold region to start oscillation from an extremely low voltage and is stable against changes in ambient temperature. Incorporating a correction mechanism that generates a high frequency ensures reliable startup and accurate DCDC conversion.

In order to solve the above problem, an extremely low voltage oscillation circuit that generates a boost trigger signal having a small temperature coefficient and oscillating from an extremely low voltage, and an extremely low voltage that generates a signal for stopping the oscillation circuit at a predetermined extremely low voltage or less. A DCDC converter that supplies power from an extremely low voltage is realized by using a low voltage detection circuit and two types of switching FETs having a normal threshold and a threshold lower than the normal threshold.

(A) a first power supply terminal (VSS) to which a renewable energy source such as a solar cell is connected, a second power supply terminal (VSB), and an output terminal (VCG); (B) an ultra-low voltage detector U17 for detecting an ultra-low power supply voltage, and (c) an ultra-low voltage generator U16 connected to the ultra-low voltage detector, connected between the two power terminals. (D) a signal level converter U15 connected to the very low voltage generator; (e) a first NMOS enhancement FET (N1) controlled by the output of the signal level converter; and (f) an output voltage. An output voltage detector U11 that detects the state of the output and outputs an operation mode control signal; and (g) a power switch U12 that selects a power supply voltage for operating a pulse width controller described later when the output voltage exceeds a predetermined value; Consists of
(H) a pulse width controller U14 connected between the first power supply terminal VSS and the output terminal VCG; and (i) a second NMOS enhancement FET (N2) controlled by the pulse width controller output. And (j) a DCDC converter comprising a first reference voltage generator U13,
The ultra-low voltage generator U16 includes at least a first resistor R3, a capacitor C4, an NMOSFET (N6), an inverter UH1, and an inverter UL1, and the inverter UH1 has an inverting threshold higher than that of the inverter UL1. The inversion threshold of UH1 has a positive temperature coefficient of 0.3 mV or more per degree, and the inverter UL1 has a temperature coefficient of −0.03 mV to +0.03 mV per degree, and the first NMOS enhancement FET (N1 ) Is in the range of 0.1V to 0.35V, and the second NMOS enhancement FET (N2) has a threshold VTH that is 1.2 times higher than the threshold VTH of the NMOS enhancement FET (N1). And the channel width of the first NMOS enhancement FET (N1) is the first NMOS enhancement FET (N1). Ultra-low voltage oscillation circuit that is stable and stable to temperature fluctuations by reliably starting to boost from an extremely low voltage by being less than one-tenth of the channel width of the NMOS enhancement FET (N2), and an ultra-low voltage DCDC converter using the same Is realized.

  Hereinafter, the present invention will be described in detail with reference to the drawings. Throughout the drawings, like elements are given like reference numerals.

  For convenience of explanation, a specific example of a conventional boosting device will be described in the DCDC converter to which the present invention is applied.

FIG. 1 shows a specific example of a conventional booster, which is an example according to Patent Document 3.
In FIG. 1, the booster according to the conventional example has power supply terminals VSB and VSS. A power supply voltage and a reference ground are connected between VSB and VSS to which the solar cell output is connected. When the power supply terminal VSS is the reference ground, VSB is supplied with a positive potential, and when VSB is the reference ground, VSS is supplied with a negative potential.

  In the conventional single cell booster in FIG. 1, the single cell solar cell V1, the first booster U3, and the inductance L1 operate on the extremely low voltage side. The portion operating with the boosted voltage is constituted by a second booster composed of voltage dividing resistors R1 and R2, a reference voltage device U5, an error amplifier U1, and a PWM circuit U2. Compared with the voltage FB divided by the voltage dividing resistors R1 and R2 and the output VR from the reference voltage generator U5, the switch FET N3 is opened and closed to increase the voltage.

Although the first booster U3 is a charge pump system, in the conventional example in FIG. 1, an oscillator different from the oscillator U4 operating at an extremely low voltage is indispensable, but is not specified in the literature. And for double boosting, at least two large capacitors are required. A FET with a large current capability for switching two capacitors is also essential. It is well known that when integrated with a semiconductor, it occupies a large area, and an increase in cost cannot be avoided.

FIG. 2 shows a specific example of a conventional booster, which is an example according to Patent Document 4.
In FIG. 2, V2 indicates a solar cell panel that generates a higher voltage, and power for starting up the booster circuit U5 is supplied via the diode D2. Once the voltage is increased to a certain voltage, the control unit U6 switches the power supply source to a main power generation source such as a solar cell or a fuel cell indicated by V3. However, in this method, the output voltage of the starting solar cell V2 drops in the forward direction of the diode D2, and if a sufficient voltage can be output, it is clear that a better effect can be obtained if it is connected to V3 as it is. Yes, the convenience and cost increase of a single cell cannot be avoided.

FIG. 3 shows a specific example of a conventional booster, which is an example according to Patent Document 5.
In FIG. 3, V4 is a solar cell panel. V5 indicates a secondary battery.
When the solar cell output voltage VSB is sufficient, charging and load current are supplied in the direction of → 1 with the electric power boosted from the solar cell V4. When the voltage detector U9 detects a low voltage, it starts by supplying power to the booster circuit in the direction of → 2 with the remaining voltage of the lithium battery V5.
However, in this method, when the secondary battery reaches the overdischarge prohibition voltage, all the operations are stopped, and the solar cell does not work at all and cannot be used even when there is sunlight.

According to the first aspect of the present invention, there is provided an ultra-low voltage booster capable of reliably guaranteeing a boost operation at an extremely low voltage and setting a clock frequency variation due to temperature flat. This will be described with reference to FIGS.

FIG. 4 is a block diagram of the DCDC converter according to the first embodiment of the present invention. A DCDC converter that reliably starts boosting even at an extremely low voltage output from a single-cell solar cell or fuel cell is realized.

In FIG. 4, the DCDC converter according to the present invention has input terminals VSS and VSB. A voltage from the solar cell is applied between the input terminals VSS and VSB. In the example of FIG. 4, the input terminal VSS serves as one of output terminals as a common terminal or a ground terminal.

That is, the DCDC converter includes output terminals VCG and VSS, and a secondary battery V6 charged between the output terminals VCG and VSS is connected to the load LD1. Note that the load LD1 does not represent a part of the DCDC converter, but represents an electronic device (for example, a mobile phone) that uses the DCDC converter as a power source. In this way, the voltage (output voltage) from the output terminals VCG and VSS is applied to the secondary battery V6 and the load LD1.

In addition to the input terminals VSB and VSS and the output terminals VCG and VSS, the DCDC converter of the present invention includes a very low voltage detector U17, a very low voltage oscillator U16, a signal level converter U15, and a first NMOS functioning as a start switch. An enhancement FET (N1), a second NMOS enhancement FET (N2) functioning as a main boost switch, an output voltage detector U11, a power supply switch U12, and a first power supply terminal VSS and an output terminal VCG are connected. A pulse width controller U14 and a first reference voltage generator U13.

The extremely low voltage detector U17 is shown in a circuit diagram in FIG. 5 and an operation waveform in FIG. The ultra-low voltage detector U17 outputs a low level and inhibits the operation of the ultra-low voltage oscillator U16 when it is below a predetermined power supply voltage as shown by the waveforms 24, 25 and 26 in FIG. When the voltage is higher than a predetermined power supply voltage, a high level is output to enable the operation of the ultra-low voltage oscillator U16.

As shown in the circuit diagram of FIG. 5, the ultra-low voltage detector U17 detects the power supply voltage by NMOSFETs (N1 and ND1), and is shown as detection signals by curves 21, 22, and 23 in FIG. The comparison circuit including N2, N3, P2, and P3 in FIG. 5 performs comparison and detection, and outputs as VDO including N4, N5, P4, and P5.
Reference numerals 21 and 24 represent 90 degrees, 22 and 25 represent 30 degrees, and 23 and 26 represent −20 degrees, respectively.

In FIG. 13, the detection output has a negative coefficient with respect to the temperature, and has a characteristic that the detection voltage decreases as the temperature increases. Since the output voltage of the solar cell has a negative temperature coefficient with respect to temperature, it corresponds to the characteristic. Although the detection output can be a very low voltage detector having a flat coefficient with respect to temperature, details are not shown here.

The extremely low voltage oscillator U16 is shown in a circuit diagram in FIG. 7 and an operation waveform in FIG. In FIG. 7, a resistor R3, a capacitor C4, and an enhancement NMOSFET N6 form a charge / discharge circuit to generate a triangular wave. When the input of the inverter UH1 exceeds the inversion threshold, the inverter UD2 changes to high and N6 is made conductive, and the triangular wave shifts to a downward slope. When the triangular wave falls to the inversion potential of the inverter UL1, the inverter UD2 changes to low, the triangular wave shifts to a rising slope and repeats the triangular wave. The NMOSFET N7 is used for prohibiting the operation, and the NMOSFET N7 is fixed to the energized state during the operation for generating the triangular wave. The ultra-low voltage oscillator U16 in FIG. 7 is a circuit that can oscillate and generate a pulse signal whenever a power supply voltage higher than a certain level is supplied. In this embodiment, the threshold value VTH is set to 0.1 V to 0.35 V, which is lower than the threshold value VTH in the standard manufacturing process, and a power supply voltage of about 0.1 V for starting oscillation is realized.

Since the MOSFET N6 operates in the subthreshold region when generating a triangular wave, the conduction frequency changes greatly with temperature, so the oscillation frequency changes greatly. If the operating frequency of the DC / DC converter fluctuates, spurious noise is generated in a wide frequency band, and therefore undesirable undesirable effects are required.

FIG. 12 shows the temperature variation observed in the subthreshold region.
In the FET characteristics of FIG. 12, the left side of the intersection of the drain current ID1 at a temperature of 90 degrees and the drain current ID2 at a temperature of −20 degrees with respect to a predetermined gate input voltage is a positive temperature coefficient at which the drain current increases as the temperature rises. Has a negative temperature coefficient because the drain current decreases as the temperature rises. In the subthreshold region, a current change with a relatively large temperature coefficient cannot be avoided. Therefore, in order to use this region, it can be said that practical use is difficult without a temperature correction function. FIG. 12 is an example of an N-type enhancement FET with L = 1u, W = 20u, and threshold value VTH = 0.2V, but the same tendency is shown for both depletion and P-type. It should be noted that the drain current ID1 is not zero when VGS = 0V.

According to the operation waveform of the ultra-low voltage oscillator U16 shown in FIG. 15, the change is within about 2% from −20 degrees to 90 degrees. In order to operate the oscillation circuit in FIG. 7 at an extremely low voltage, a necessary pulse waveform can be obtained by operating the MOSFET in the subthreshold region by reducing the threshold value VTH of the MOSFET to about 0.2V. However, since it operates in the subthreshold region, the ON current of the NMOSFET N6 varies greatly with temperature, and the delay time of the inverter U5 and the two-input NANDs U3 and U4 also varies greatly. It has been reported that at low temperatures, the NOSFET N6 on-current becomes smaller and the period of the triangular wave becomes larger than that at high temperatures, almost twice as long. In the present invention, a method of keeping the period of the triangular wave constant is realized by utilizing the characteristic that the inversion threshold values of the inverter UL1 and the inverter UH1 change with temperature.

FIG. 14 shows input / output characteristics with the temperature of the inversion threshold of UH1 and UL1 as a variable. Curves 41 and 42 are UL1 characteristics, 43 and 44 are UH1 characteristics, 41 and 43 are -20 degrees, and 42 and 43 are 90 degrees. The circuit of inverters UL1 and UH1 is shown in FIG. The temperature coefficient of the inversion threshold is adjusted by changing the channel lengths of the NMOSFET NE2 and the PMOS FET PE5. In one embodiment of the present invention, the temperature coefficient of the input / output characteristics of UL1 is substantially zero, and the temperature coefficient of UH1 has a coefficient of +45 mV per degree. As described above, the extremely low voltage oscillation circuit according to the present invention is a circuit that always oscillates, and the temperature coefficient of the oscillation frequency is made substantially zero by adjusting the ratio of the channel lengths of the MOS FETs constituting the inverters UL1 and UH1. It becomes possible. In other words, the ON-current change of the NMOSFET N6 accompanying the temperature change and the delay time change by the inverter U5 and the like are absorbed by the temperature change of the inversion threshold value of the inverter UH1, thereby realizing a highly accurate oscillation cycle.

Since the DCDC converter according to the present invention boosts the voltage 15 times from an extremely low voltage of 0.3V or less to about 4.5V, the NMOS switch at the time of startup needs to have a large on / off ratio. The on-time is about 6 uS, the off-time is 200 nS, and a large on-off ratio is realized so as to be able to respond to a large step-up ratio, thereby guaranteeing startup.
The very low voltage oscillator U16 generates a pulse width by inverters UD1 to UD5 and a two-input NAND U6 in the circuit diagram of FIG.

FIG. 8 shows a circuit diagram of the signal level converter U15. N21 to N23 denote NMOS FETs, and P21 to P25 denote PMOSFETs, which constitute a level shift unit. The input terminal OSC is supplied with the output of the extremely low voltage oscillator U16, and the pulse signal level-converted to VDD is output to the drains of the MOSFETs P23 and N23. Inverters U21 and U22 are added as buffer circuits to drive the start switch N1. Since the start switch N1 operates at an extremely low voltage, it is configured with a threshold value VTH lower than that of the main boost switch N2. Since the control voltage is switched to a high voltage when the voltage reaches a predetermined voltage after activation, the activation switch N1 does not need to be a switch having a large current capability.

FIG. 6 shows the output voltage detector U11 and the power switch U12 together. U21 is a comparator, U22 is a signal level converter VREF is a reference voltage generator for generating a reference voltage from an extremely low voltage VSB, and PE1 to PE4 are PMOSFET switches. FB2 is a voltage divided from the boosted output voltage VCG, and when FB2 is lower than the reference voltage VREF, PE3 becomes conductive and outputs VSB to VP. When the boosted voltage rises and FB2 becomes higher than the reference voltage VREF, the boosted output VCG = VH is output to VP and a high voltage is supplied to the PMW control unit U14. A circuit example of the reference voltage generator VREF is shown in FIG.

FIG. 9 shows a configuration diagram of the pulse width controller U14. In the figure, the inductance L3, the Schottky diode D1, and the output smoothing capacitor C6 are shown overlapping with the embodiment of FIG. U32 is an integrator that amplifies and smoothes the difference between the reference voltage VR and the feedback signal FB, U33 is a sawtooth wave generator that generates a sawtooth wave from the level converter output CLK, U31 is a FET switch from the sawtooth wave and the integrator output. A PWM pulse signal to be opened and closed is supplied to the main boost switch N2. Since this block operates with a boosted voltage VP, the main boost switch N2 uses a standard threshold VTH, unlike the start switch N1 in FIG. 4 which operates with a very low voltage.

The reference voltage generator U13 that generates the reference voltage VR can be configured by a circuit similar to that shown in FIG. 10, but a very low voltage operation is not required since a sufficient voltage is supplied.

FIG. 16 shows operation waveforms of the present invention.
An example in which the start switch N1 has a channel length L = 0.8u, a channel width 1000u, a threshold VTH = 0.2V, a main boost switch N2 has L = 0.5u, W = 80000u, and VTH = 0.55V. A waveform 61 indicates the output voltage of the output terminal VCG, 62 indicates a current waveform flowing through the load LD1, 63 indicates an applied extremely low voltage power supply waveform VSB, and 64 indicates a switching signal of the voltage switch U12. Since VSB and 63 simulate a case where 300 mV is applied in a direct current manner, a step waveform is observed. It can be seen that at the first 500 uS, the step-up speed is smooth, and when the switch N2 is opened and closed with a high voltage boosted from an output voltage of 0.9 V or higher, the step-up is realized quickly.

As described above, according to the present invention, a pulse signal that triggers boosting can be reliably generated by an extremely low voltage oscillator that always oscillates, and the boost switching operation can be started without failing. With an extremely low voltage of 0.25 V or less with the extremely low voltage detector U17, it is possible to prohibit a malfunction and guarantee a safe operation. Moreover, by using the sub-threshold region and incorporating the temperature compensation function, it becomes possible to supply a DCDC converter that can be mass-produced in a normal manufacturing process without increasing the cost.

Further, according to the embodiment of the present invention, there is no need to provide a separate charge pump circuit for boosting start-up, and there is no need to add a second solar cell that outputs a high voltage. It is possible to realize a DCDC conversion system and a DCDC converter that always start from an extremely low power supply voltage in a cell.

Although the embodiment of the present invention is shown by the booster, it is easily inferred that the same action can be realized by the buck. It is also clear that the parameters of each element shown in the embodiments of the present invention are not limited to this, and can be easily changed according to the required specifications.

The block diagram of the low voltage booster circuit of the prior art example 1 is shown. The block diagram of the low voltage booster circuit of the prior art example 2 is shown. The block diagram of the low voltage booster circuit of the prior art example 3 is shown. The block diagram of the DCDC converter of this invention is shown. The circuit diagram of the very low voltage detector in this invention is shown. The circuit diagram of the output voltage detector and power supply switching device in this invention is shown. The circuit diagram of the very low voltage oscillator in this invention is shown. The circuit diagram of the level converter in this invention is shown. The circuit diagram of the PWM DCDC converter in this invention is shown. 1 shows a circuit diagram of a reference voltage generator according to the present invention. The circuit diagram of the inverter concerning this invention is shown. The current-gate voltage characteristic diagram of an NMOS FET element is shown. The operation | movement waveform diagram of the very low voltage detector in this invention is shown. The input-output characteristic figure of the inverter concerning this invention is shown. The operation | movement waveform diagram of the very low voltage oscillator in this invention is shown. The operation | movement waveform diagram of the DCDC converter in this invention is shown.

VSB, VSS: Input terminal VOUT: Output terminal VCG: Charge output terminal VR: Reference voltage FB: Detection voltage U1: Error amplifier U2: PWM controller U3: Charge pump booster U4: Oscillator U5, U13, VREF: Reference voltage generation U6: Controller U7: Booster U8, U14: Pulse width controller U9: Voltage detector U11: Output voltage detector U12: Current switching unit U13: Reference voltage generator U15: Signal level converter U16: Extremely low voltage Oscillator U17: Extremely low voltage detector U21, U22: Inverter U31: Comparator U32: Integrator U33: Sawtooth wave generator N1: Low threshold NMOS enhancement FET
N2: Standard threshold NMOS enhancement FET
N1 to N23: NMOS enhancement FET
P1 to P25: PMOS enhancement FET
NE1, NE2: NMOS enhancement FET
PE1 to PE2: PMOS enhancement FET
ND1 to ND2: NMOS depletion FET
R1 to R3: Resistors L1 to L3: Inductances C1 to C6: Capacitances V1 to V4, PV: Solar cells or fuel cells V5, V6: Lithium batteries D1 to D5: Schottky diodes

Claims (1)

(A) a first power supply terminal (VSS) to which a renewable energy source such as a solar cell is connected, a second power supply terminal (VSB), and an output terminal (VCG); (B) an ultra-low voltage detector U17 connected between two power supply terminals, (c) an ultra-low voltage generator U16 connected to the ultra-low voltage detector, and (d) the ultra-low voltage. A signal level converter U15 connected to the generator, (e) a first NMOS enhancement FET (N1) controlled by the output of the signal level converter, (f) an output voltage detector U11, (g ) Power switch U12,
(H) a pulse width controller U14 connected between the first power supply terminal VSS and the output terminal VCG; and (i) a second NMOS enhancement FET (N2) controlled by the pulse width controller output. And (j) a DCDC converter comprising a first reference voltage generator U13,
The ultra-low voltage generator U16 includes at least a first resistor R3, a capacitor C4, an NMOSFET (N6), an inverter UH1, and an inverter UL1, and the inverter UH1 has an inverting threshold higher than that of the inverter UL1. The inversion threshold of UH1 has a positive temperature coefficient of 0.3 mV or more per degree, and the inverter UL1 has a temperature coefficient of −0.03 mV to +0.03 mV per degree, and the first NMOS enhancement FET (N1 ) Is 0.1V to 0.35V, and the second NMOS enhancement FET (N2) has a threshold VTH that is 1.2 times higher than the threshold VTH of the NMOS enhancement FET (N1). The channel width of the first NMOS enhancement FET (N1) is equal to the second N Extremely low voltage DCDC converter using very low voltage oscillator circuit and a characterized in that not more than one tenth of the channel width of the OS enhancement FET (N2).

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