JP5454411B2 - Method for dry etching of a film containing silicon - Google Patents

Description

The present invention relates to a dry etching method for a film containing silicon .

  For example, a conventional thin film transistor includes an inverted staggered type (see, for example, Patent Document 1). In this thin film transistor, a gate electrode is provided on the upper surface of the substrate. A gate insulating film is provided on the upper surface of the substrate including the gate electrode. A semiconductor thin film made of intrinsic amorphous silicon is provided on the upper surface of the gate insulating film on the gate electrode. Ohmic contact layers made of n-type amorphous silicon are provided on both sides of the upper surface of the semiconductor thin film. A source electrode and a drain electrode are provided on the upper surface of each ohmic contact layer.

  By the way, in the conventional method for forming an ohmic contact layer and a semiconductor thin film in a thin film transistor, an intrinsic amorphous silicon film (film for forming a semiconductor thin film) and an n-type amorphous silicon film (formation of an ohmic contact layer) formed on the upper surface of the gate insulating film. The film is continuously dry-etched. In this case, SF6 (sulfur hexafluoride) gas is used as the etching gas (see paragraph 130 of Patent Document 1).

Japanese Patent Laying-Open No. 2007-79342 (FIG. 5)

  However, SF6 as an etching gas used in the above conventional dry etching method has a very large warming coefficient of several thousands to several tens of thousands, so that it has recently been regarded as a problem as a cause of global warming. It has become to. Therefore, selection of alternative gas to replace this is an important issue.

Therefore, the present invention includes silicon that can satisfactorily dry-etch materials constituting thin film transistors such as an amorphous silicon film and a silicon nitride film without using a gas that causes global warming such as SF _6. It is an object to provide a dry etching method for a film .

According to a first aspect of the present invention, there is provided a silicon nitride film formed on an amorphous silicon film by parallel plate dry etching using an etching gas containing COF ₂ and oxygen gas. The film is dry-etched using the amorphous silicon film as a stopper, and the flow rate ratio of the oxygen gas to the COF ₂ gas is 0.5-4 .
According to a second aspect of the present invention, there is provided a dry etching method for a silicon-containing film according to the first aspect of the present invention, wherein the amorphous silicon film is a genuine amorphous film when an inverted staggered type channel protective film type thin film transistor is manufactured. It is a silicon film, and the silicon nitride film is dry-etched on the genuine amorphous silicon film to form a channel protective film .
According to a third aspect of the present invention, there is provided a dry etching method for a film containing silicon according to the first or second aspect of the present invention, wherein the flow rate ratio of the oxygen gas to the COF ₂ gas is 1.5 to 2. It is what.
The dry etching method of the film containing silicon according to the invention of claim 4 is the invention according to any one of claims 1 to 3, characterized in that it comprises a said etching gas further inert gas Is.
The dry etching method of the film containing silicon according to the invention of claim 5 is the invention according to any one of claims 1 to 4, wherein the dry etching to be carried out in a vacuum atmosphere of 1~100Pa It is a feature.
According to a sixth aspect of the present invention, there is provided a dry etching method for a silicon-containing film, comprising : amorphous silicon formed on a silicon nitride film by parallel plate type dry etching using an etching gas containing COF ₂ and chlorine gas. The film is dry-etched using the silicon nitride film as a stopper, and the flow rate ratio of COF ₂ gas to chlorine gas is 0.1 to 1.
According to a seventh aspect of the present invention, there is provided a dry etching method for a silicon-containing film according to the sixth aspect of the present invention , wherein the amorphous silicon film is dry-etched when an inverted stagger type channel protective film type thin film transistor is manufactured. Then, a semiconductor thin film is formed on the gate insulating film made of the silicon nitride film .
A dry etching method for a film containing silicon according to an eighth aspect of the present invention is the method according to the sixth or seventh aspect , wherein the amorphous silicon film is a genuine amorphous silicon film formed on the silicon nitride film. And an n-type amorphous silicon film formed on the genuine amorphous silicon film.
According to a ninth aspect of the present invention, there is provided a dry etching method for a silicon-containing film according to the eighth aspect of the present invention, wherein the n-type amorphous silicon film The genuine amorphous silicon film is continuously dry-etched to form a semiconductor thin film on the gate insulating film made of the silicon nitride film, and an ohmic contact layer is formed on both sides of the upper surface of the semiconductor thin film. Is .
According to a tenth aspect of the present invention, there is provided a dry etching method for a silicon-containing film according to the sixth aspect, wherein the flow rate ratio of the COF ₂ gas to the chlorine gas is 0.25 to 0. .5.
The silicon-containing film dry etching method according to claim 11 is the invention according to any one of claims 6 to 10 , wherein the dry etching is dry etching by cathode coupling. It is what.
A dry etching method for a film containing silicon according to a twelfth aspect of the present invention is the dry etching method according to any one of the sixth to tenth aspects, wherein the dry etching is dry etching by anode coupling. It is what.
A dry etching method for a film containing silicon according to a thirteenth aspect of the present invention is the method according to any one of the sixth to twelfth aspects, wherein the etching gas further includes an inert gas. Is.
A dry etching method for a film containing silicon according to a fourteenth aspect of the present invention is the method according to any one of the sixth to thirteenth aspects, wherein the dry etching is performed in a vacuum atmosphere of 1 to 100 Pa. It is a feature.
The dry etching method of the film containing silicon according to the invention of claim 15, the parallel plate type dry etching using an etching gas containing at least COF _2, the silicon nitride film underlying the consisting of ITO film or chromium The silicon nitride film thus formed is dry-etched using the ITO film or chromium as a stopper.
According to a sixteenth aspect of the present invention, there is provided a dry etching method for a silicon-containing film according to the fifteenth aspect of the present invention, wherein an inversely staggered channel protective film type or channel etch type thin film transistor is manufactured. An opening is formed in the corresponding portion of the overcoat film made of the silicon nitride film by dry etching.
According to a seventeenth aspect of the present invention, there is provided a dry etching method for a film containing silicon according to the sixteenth aspect of the present invention, wherein the etching gas is a single COF ₂ gas.
The dry etching method for a film containing silicon according to the invention of claim 18 is characterized in that, in the invention of claim 16 , the etching gas is a mixed gas containing COF ₂ gas and oxygen gas. It is.
According to a nineteenth aspect of the present invention, there is provided a dry etching method for a silicon-containing film according to the eighteenth aspect , wherein the flow rate ratio of the oxygen gas to the COF ₂ gas is 2 or less. .
The dry etching method of the film containing silicon according to the invention of claim 20 is the invention according to claim 18, wherein the flow ratio of oxygen gas to COF ₂ gas is 0.2 to 0.3 It is what.
The dry etching method of the film containing silicon according to the invention of claim 21 is the invention according to any one of claims 15 to 20, characterized in that it comprises a said etching gas further inert gas Is.
The dry etching method of the film containing silicon according to the invention of claim 22 is the invention according to any one of claims 15 to 21, wherein the dry etching and characterized in that in a vacuum atmosphere of 1~100Pa To do.

According to the present invention, a film containing silicon is dry-etched by parallel plate type dry etching using a gas containing at least COF _{2, so} that a gas that causes global warming such as SF ₆ is not used. The film containing silicon can be satisfactorily dry etched.

Sectional drawing of an example of the thin-film transistor panel manufactured by the manufacturing method including the dry etching method of this invention. Sectional drawing of the initial process in an example of the manufacturing method of the thin-film transistor panel shown in FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. FIG. 9 is a cross-sectional view of the process following FIG. 8. The schematic block diagram of an example of a 1st dry etching apparatus. The schematic block diagram of the other example of the 2nd dry etching apparatus. FIG. 10 is a diagram for illustrating a third transistor characteristic. FIG. 5 is a diagram for illustrating a fourth transistor characteristic. Sectional drawing of the other example of the thin-film transistor panel manufactured by the manufacturing method including the dry etching method of this invention. FIG. 15 is a cross-sectional view of an initial process in the example of the method for manufacturing the thin film transistor panel illustrated in FIG. 14. FIG. 16 is a cross-sectional view of the process following FIG. 15. FIG. 17 is a cross-sectional view of the process following FIG. 16. FIG. 18 is a cross-sectional view of the process following FIG. 17. FIG. 19 is a cross-sectional view of the process following FIG. 18. FIG. 20 is a cross-sectional view of the process following FIG. 19.

  FIG. 1 shows a sectional view of an example of a thin film transistor panel manufactured by a manufacturing method including a dry etching method of the present invention. The thin film transistor panel includes a glass substrate 1. A gate electrode 2 made of a metal such as chromium is provided at a predetermined location on the upper surface of the glass substrate 1. A gate insulating film 3 made of silicon nitride is provided on the upper surface of the glass substrate 1 including the gate electrode 2.

  A semiconductor thin film 4 made of intrinsic amorphous silicon is provided at a predetermined position on the upper surface of the gate insulating film 3 on the gate electrode 2. A channel protective film 5 made of silicon nitride is provided at a predetermined position on the upper surface of the semiconductor thin film 4. Ohmic contact layers 6 and 7 made of n-type amorphous silicon are provided on both sides of the upper surface of the channel protective film 5 and on the upper surface of the semiconductor thin film 4 on both sides thereof. A source electrode 8 and a drain electrode 9 made of a metal such as chromium are provided on the upper surfaces of the ohmic contact layers 6 and 7.

  Here, the gate electrode 2, the gate insulating film 3, the semiconductor thin film 4, the channel protective film 5, the ohmic contact layers 6 and 7, the source electrode 8 and the drain electrode 9 constitute an inversely staggered channel protective film type thin film transistor 10. Has been.

  A pixel electrode 11 made of ITO is provided at a predetermined position on the upper surface of the gate insulating film 3 and a part of the upper surface of the source electrode 8. An overcoat film 12 made of silicon nitride is provided on the upper surface of the gate insulating film 3 including the thin film transistor 10 and the pixel electrode 11. In this case, an opening 13 is provided in the overcoat film 12 in a portion corresponding to a region other than the peripheral portion of the pixel electrode 11.

  Next, an example of a method for manufacturing the thin film transistor panel will be described. First, as shown in FIG. 2, a gate electrode 2 is formed by patterning a metal film made of chromium or the like formed by sputtering at a predetermined location on the upper surface of the glass substrate 1 by photolithography.

  Next, a gate insulating film 3 made of silicon nitride, an intrinsic amorphous silicon film (film for forming a semiconductor thin film 4) 21 and a silicon nitride film (channel protective film) are formed on the upper surface of the glass substrate 1 including the gate electrode 2 by plasma CVD. 5 forming film) 22 is continuously formed. Next, a resist film 23 is formed by patterning a resist film applied by a screen printing method, a spin coating method, or the like on the channel protection film 5 formation region on the upper surface of the silicon nitride film 22 by a photolithography method.

  Next, when the silicon nitride film 22 is dry-etched using the resist film 23 as a mask, the silicon nitride film 22 in a region other than under the resist film 23 is removed, and the channel protective film 5 is formed under the resist film 23 as shown in FIG. Is formed. Next, the resist film 23 is peeled off.

  Next, as shown in FIG. 4, an n-type amorphous silicon film (film for forming ohmic contact layers 6 and 7) 24 is formed on the upper surface of the intrinsic amorphous silicon film 21 including the channel protective film 5 by plasma CVD. To do. Next, a source / drain electrode forming film 25 made of a metal such as chromium is formed on the upper surface of the n-type amorphous silicon film 24 by sputtering.

  Next, by patterning a resist film applied to the source electrode 8 formation region and the drain electrode 9 formation region on the upper surface of the source / drain electrode formation film 25 by a screen printing method, a spin coating method, or the like by a photolithography method. Then, resist films 26 and 27 are formed.

  Next, when the source / drain electrode forming film 25 is wet-etched using the resist films 26 and 27 as a mask, the source / drain electrode forming film 25 in the regions other than the regions under the resist films 26 and 27 is removed, as shown in FIG. As described above, the source electrode 8 and the drain electrode 9 are formed under the resist films 26 and 27.

  Next, when the n-type amorphous silicon film 24 and the intrinsic amorphous silicon film 21 are continuously dry-etched using the resist films 26 and 27 and the channel protective film 5 as a mask, the n-type amorphous silicon in regions other than the regions under the resist films 26 and 27 is obtained. The film 24 is removed, and the intrinsic amorphous silicon film 21 in a region other than the resist films 26 and 27 and the channel protective film 5 is removed, and an ohmic contact is provided under the source electrode 8 and the drain electrode 9 as shown in FIG. The layers 6 and 7 are formed, and the semiconductor thin film 4 is formed under the ohmic contact layers 6 and 7 and the channel protective film 5.

  In this state, the gate electrode 2, the gate insulating film 3, the semiconductor thin film 4, the channel protective film 5, the ohmic contact layers 6 and 7, the source electrode 8, and the drain electrode 9 constitute an inverted stagger type channel protective film type thin film transistor 10. Is formed. Next, the resist films 26 and 27 are peeled off.

  Next, as shown in FIG. 7, by patterning an ITO film formed by sputtering at a predetermined location on the upper surface of the gate insulating film 3 and part of the upper surface of the source electrode 8, by photolithography. Pixel electrode 11 is formed.

  Next, as shown in FIG. 8, an overcoat film 12 made of silicon nitride is formed on the upper surface of the gate insulating film 3 including the thin film transistor 10 and the pixel electrode 11 by plasma CVD. Next, a resist film 28 is formed on the upper surface of the overcoat film 12 by patterning a resist film applied by a screen printing method, a spin coating method, or the like by a photolithography method. In this case, an opening 29 is formed in the resist film 28 in a portion corresponding to a region other than the peripheral portion of the pixel electrode 11.

  Next, when the overcoat film 12 is dry-etched using the resist film 28 as a mask, as shown in FIG. 9, the overcoat film in a portion corresponding to the region other than the opening 29 of the resist film 28, that is, the peripheral portion of the pixel electrode 11. 12, an opening 13 is formed. Next, the resist film 28 is peeled off. Thus, the thin film transistor panel shown in FIG. 1 is obtained.

(First dry etching equipment)
Next, in the case shown in FIGS. 2 and 3, an example of a first dry etching apparatus for dry etching the silicon nitride film (channel protective film 5 forming film) 22 to form the channel protective film 5 will be described. This will be described with reference to the schematic configuration diagram shown in FIG. This dry etching apparatus is a parallel plate type and includes a reaction vessel 31.

  A lower electrode 32 is provided in the lower part of the reaction vessel 31, and an upper electrode 33 is provided in the upper part. In this case, the lower electrode 32 is connected to a high frequency power supply 34, and the upper electrode 33 is grounded. A workpiece 35 is placed on the upper surface of the lower electrode 32. A predetermined portion below the reaction vessel 31 is connected to a vacuum pump 37 via a pipe 36.

A gas introduction pipe 38 is provided in the upper central portion of the reaction vessel 31 so as to penetrate the central portion of the upper electrode 33. The gas introduction pipe 38 is connected to a common pipe 39. First and second pipes 40 and 41 are connected to the common pipe 39. First and second solenoid valves 42 and 43 and first and second mass flow controllers 44 and 45 are interposed in the first and second pipes 40 and 41, respectively. A COF ₂ (carbonyl fluoride) gas supply source 46 and an oxygen gas supply source 47 made up of cylinders or the like are connected to the respective leading ends of the first and second pipes 40 and 41.

  Next, the workpiece 35 placed on the upper surface of the lower electrode 32 is in the state shown in FIG. 2 using this first dry etching apparatus, and the intrinsic amorphous silicon film (film for forming the semiconductor thin film 4) 21 is obtained. The case where the upper silicon nitride film (channel protective film 5 forming film) 22 is dry-etched will be described. First, the gas in the reaction vessel 31 was discharged by driving the vacuum pump 37, and the inside of the reaction vessel 31 was set to a vacuum atmosphere at a pressure of 1 to 100 Pa.

Next, the first and second electromagnetic valves 42 and 43 are opened, and a mixed gas of COF ₂ gas and oxygen gas supplied from the COF ₂ gas supply source 46 and the oxygen gas supply source 47 is supplied from the gas introduction pipe 38. Introduce into the reaction vessel 31. In this case, the flow rates of COF ₂ gas and oxygen gas were adjusted by the first and second mass flow controllers 44 and 45, the flow rate of COF ₂ gas was 100 sccm, and the flow rate of oxygen gas was 100 to 400 sccm. A high frequency power of 700 W at 13.56 MHz was applied from the high frequency power supply 34.

Then, the silicon nitride 22 in the region other than under the resist film 23 was removed by dry etching, and the etching rate was about 1500 Å / min. In this case, when the silicon nitride film 22 in the region other than under the resist film 23 is completely removed, the underlying intrinsic amorphous silicon film 21 is exposed as shown in FIG. 3, and the exposed intrinsic amorphous silicon film 21 is exposed. Is removed to some extent by dry etching, but the etching rate was about 210 liters / min. Therefore, the selection ratio in this case is about 7 times, which is practical. Moreover, the COF ₂ gas has a warming coefficient of 1, which can greatly contribute to the suppression of greenhouse gas emissions.

By the way, when the inverted stagger type channel protective film type thin film transistor 10 is manufactured, as an example, the thickness of the silicon nitride film 22 is about 1200 mm and the thickness of the genuine amorphous silicon film 21 is about 250 mm. On the other hand, with the COF ₂ gas alone, the etching rate of the silicon nitride film 22 is relatively high at about 4000 kg / min.

Therefore, in the dry etching with COF ₂ gas alone, there is a possibility that most of the intrinsic amorphous silicon film 21 is etched away. On the other hand, in the dry etching method, since an etching gas composed of a mixed gas of COF ₂ gas and oxygen gas is used, the etching rate of the silicon nitride film 22 is relatively small, about 1500 Å / min, and a genuine amorphous state. Also for the silicon film 21, a practical etching rate of about 210 Å / min can be achieved.

That is, as the flow ratio of oxygen gas to COF ₂ gas increases, the selectivity increases, but the etching rate decreases. On the side where the oxygen gas flow rate ratio is large, processing can be performed even if the flow rate ratio of the oxygen gas to the COF ₂ gas is increased to about 4 as long as a reduction in throughput is allowed. On the other hand, on the side where the oxygen gas flow rate ratio is small, the etching rate of the underlying genuine amorphous silicon film 21 increases, so the limit of the flow rate of oxygen gas to COF ₂ gas is about 0.5. Therefore, in the dry etching method, the flow rate ratio of oxygen gas to COF ₂ gas is set to 0.5-4.

By the way, when manufacturing the inverted stagger type thin film transistor 10 of the channel protective film type, as described above, the thickness of the silicon nitride film 22 is about 1200 mm while the thickness of the genuine amorphous silicon film 21 is only about 250 mm. Therefore, a high selection ratio is required. Therefore, if the flow rate ratio of the oxygen gas to the COF ₂ gas is 1.5 to 2, the etching rate of the silicon nitride film 22 is about 1200 Å / min, which is slightly smaller than the above case (about 1500 Å / min). The selectivity can be further increased. Therefore, the flow rate ratio of oxygen gas to COF ₂ gas is more preferably 1.5 to 2.

The COF ₂ gas supply source 46 may supply a diluted COF ₂ gas diluted with one or more kinds of inert gases such as nitrogen, helium, neon, and argon. For example, the flow rate of diluted COF ₂ gas diluted to 20 vol% with nitrogen gas may be 500 sccm (the flow rate of only COF ₂ gas is 100 sccm), and the flow rate of oxygen gas may be 100 to 400 sccm. When an inert gas is added, the plasma state is stabilized and the etching uniformity can be improved.

In addition to the COF ₂ gas supply source 46, an inert gas supply source such as a cylinder may be provided. In this case, it goes without saying that piping, an electromagnetic valve and a mass flow controller associated with the inert gas supply source are provided. As described above, even when an inert gas is added, the flow rate ratio of the oxygen gas to the COF ₂ gas is preferably 0.5 to 4, and more preferably 1.5 to 2.

(Second dry etching equipment)
Next, in the case shown in FIGS. 5 and 6, the n-type amorphous silicon film (film for forming the ohmic contact layers 6 and 7) 24 and the intrinsic amorphous silicon film (film for forming the semiconductor thin film 4) 21 are continuously dry-etched. An example of the second dry etching apparatus for forming the ohmic contact layers 6 and 7 and the semiconductor thin film 4 will be described with reference to a schematic configuration diagram shown in FIG. The second dry etching apparatus is different from the first dry etching apparatus shown in FIG. 10 in that a chlorine gas supply source 48 is used instead of the oxygen gas supply source 47.

  Next, using this second dry etching apparatus, the workpiece 35 placed on the upper surface of the lower electrode 32 is in the state shown in FIG. 5, and the n-type amorphous on the gate insulating film 3 made of silicon nitride. A case where the silicon film 24 and the intrinsic amorphous silicon film 21 are continuously dry-etched will be described. First, the gas in the reaction vessel 31 was discharged by driving the vacuum pump 37, and the inside of the reaction vessel 31 was set to a vacuum atmosphere at a pressure of 1 to 100 Pa.

Next, the first and second electromagnetic valves 42 and 43 are opened, and the mixed gas of COF ₂ gas and chlorine gas supplied from the COF ₂ gas supply source 46 and the chlorine gas supply source 48 is supplied from the gas introduction pipe 38. Introduce into the reaction vessel 31. In this case, the flow rates of COF ₂ gas and chlorine gas were adjusted by the first and second mass flow controllers 44 and 45, the flow rate of COF ₂ gas was 20 to 200 sccm, and the flow rate of chlorine gas was 200 sccm. A high frequency power of 700 W at 13.56 MHz was applied from the high frequency power supply 34.

Then, the n-type amorphous silicon film 24 and the intrinsic amorphous silicon film 21 in the regions other than the regions under the resist films 26 and 27 and the channel protective film 5 are continuously removed by dry etching, and the etching rate is about 1200 Å / min. It was. In this case, when the n-type amorphous silicon film 24 and the intrinsic amorphous silicon film 21 in regions other than those under the resist films 26 and 27 and the channel protective film 5 are completely removed, as shown in FIG. The gate insulating film 3 is exposed, and the exposed gate insulating film 3 is removed by dry etching to some extent, but the etching rate is about 400 Å / min. Therefore, the selection ratio in this case is about 3 times, which is practical. Moreover, the COF ₂ gas has a warming coefficient of 1, which can greatly contribute to the suppression of greenhouse gas emissions.

By the way, in the dry etching with chlorine gas alone, the etching rate of the amorphous silicon films 21 and 24 can be obtained only about 100 Å / min. However, when 10% (20 sccm) of COF ₂ gas is added to the chlorine gas (200 sccm), it is practical. The lowest possible etching rate is obtained. On the other hand, when gradually increasing the flow rate of the COF ₂ gas, the etching rate of the amorphous silicon film 21 and 24 is reduced, since the etching rate of the gate insulating film 3 made of silicon nitride of the base is increased, COF to chlorine gas ₂ The upper limit of the gas flow ratio is preferably about 1. Therefore, in the dry etching method described above, the flow rate ratio of COF ₂ gas to chlorine gas is set to 0.1 to 1.

By the way, when the flow rate of COF ₂ gas is 75 sccm with respect to the flow rate of chlorine gas of 200 sccm, the etching rate becomes maximum, and the etching rate gradually decreases at most, but the flow rate of chlorine gas decreases to 200 sccm. If the flow rate of the COF ₂ gas is 50 to 100 sccm, a sufficient etching rate and selectivity can be obtained. Therefore, the flow rate ratio of COF ₂ gas to chlorine gas is more preferably 0.25 to 0.5.

The COF ₂ gas supply source 46 may supply a diluted COF ₂ gas diluted with one or more kinds of inert gases such as nitrogen, helium, neon, and argon. For example, the flow rate of diluted COF ₂ gas diluted to 20 vol% with nitrogen gas may be 100 to 1000 sccm (the flow rate of COF ₂ gas alone is 20 to 200 sccm), and the flow rate of chlorine gas may be 200 sccm. When an inert gas is added, the plasma state is stabilized and the etching uniformity can be improved.

In addition to the COF ₂ gas supply source 46, an inert gas supply source such as a cylinder may be provided. In this case as well, it goes without saying that piping, a solenoid valve and a mass flow controller associated with the inert gas supply source are provided. As described above, even when an inert gas is added, the flow rate ratio of COF ₂ gas to chlorine gas is preferably 0.1 to 1, more preferably 0.25 to 0.5. .

  By the way, in the dry etching apparatus shown in FIG. 11, a high frequency is applied to the lower electrode 32 on which the workpiece 35 is placed to facilitate generation of a cathode fall voltage on the grounded upper electrode 33 side, that is, the cathode side, Ions generated by discharge are used for the reaction, which is called reactive ion etching (RIE), and is dry etching by cathode coupling.

  In this dry etching by cathode coupling, anisotropic etching with less side etching is possible. However, in dry etching by cathode coupling, ion bombardment due to cathode fall voltage on the cathode side may damage transistor characteristics. Then, next, the case where ion damage can be reduced is demonstrated.

(Third dry etching equipment)
FIG. 12 shows a schematic configuration diagram of an example of a third dry etching apparatus. The third dry etching apparatus is different from the second dry etching apparatus shown in FIG. 11 in that the lower electrode 32 is grounded and the upper electrode 33 is connected to a high frequency power supply 34. Therefore, in this dry etching apparatus, dry etching by anode coupling is performed, and ion damage can be reduced and transistor characteristics are improved as compared with dry etching by cathode coupling.

(Fourth dry etching equipment)
Next, in the case shown in FIG. 8 and FIG. 9, an example of a fourth dry etching apparatus for dry etching the overcoat film 12 made of silicon nitride to form the opening 13 is schematically shown in FIG. This will be described with reference to the drawings. This fourth dry etching apparatus is different from the first dry etching apparatus shown in FIG. 10 in that the oxygen gas supply source 47 and the accompanying piping 41, the electromagnetic valve 43, and the mass flow controller 45 are omitted.

  Next, by using the fourth dry etching apparatus, the workpiece 35 placed on the upper surface of the lower electrode 32 is in the state shown in FIG. 8, and the silicon electrode overlying the pixel electrode 11 made of ITO is overcoated. A case where the coat film 12 is dry-etched will be described. First, the gas in the reaction vessel 31 was discharged by driving the vacuum pump 37, and the inside of the reaction vessel 31 was set to a vacuum atmosphere at a pressure of 1 to 100 Pa.

Next, opened the first electromagnetic valve 42, the COF ₂ gas supplied from the COF ₂ gas supply source 46 is introduced from the gas introducing pipe 38 into the reaction vessel 31. In this case, the flow rate of the COF ₂ gas was adjusted by the first mass flow controller 44, and the flow rate of the COF ₂ gas was set to 200 sccm. Further, a high frequency power of 600 W of 13.56 MHz was applied from the high frequency power source.

Then, the overcoat film 12 in the portion corresponding to the opening 29 of the resist film 28 was removed by dry etching, and the etching rate was about 4000 kg / min. In this case, when the overcoat film 12 in the portion corresponding to the opening 29 of the resist film 28 is completely removed, as shown in FIG. 9, the underlying pixel electrode 11 made of ITO is exposed. The processed pixel electrode 11 is hardly etched and is practical. Moreover, the COF ₂ gas has a warming coefficient of 1, which can greatly contribute to the suppression of greenhouse gas emissions.

Note that the dry etching of the overcoat film 12 made of silicon nitride on the pixel electrode 11 made of ITO may be performed using the first dry etching apparatus shown in FIG. In this case, the flow rate ratio of the oxygen gas to the COF ₂ gas may be 2 or less, but is more preferably 0.2 to 0.3.

That is, the thickness of the overcoat film 12 made of silicon nitride is relatively thick, for example, 8000 mm, and the underlying pixel electrode 11 made of ITO is hardly etched, so that the etching rate of the overcoat film 12 is made larger. Is preferred. Therefore, when 20 to 30% oxygen gas is mixed with respect to the COF ₂ gas, the etching rate of the overcoat film 12 increases by 30 to 40%, and the etching time can be shortened. On the other hand, if the amount of oxygen gas added is increased to some extent, the etching rate of the overcoat film 12 decreases, so the flow rate ratio of oxygen gas to COF ₂ gas is preferably 2 or less.

Also in this case, the COF ₂ gas supply source 46 supplies diluted COF ₂ gas diluted with one or more kinds of inert gases such as nitrogen, helium, neon, and argon. May be. When an inert gas is added, the plasma state is stabilized and the etching uniformity can be improved.

In addition to the COF ₂ gas supply source 46, an inert gas supply source such as a cylinder may be provided. In this case as well, it goes without saying that piping, a solenoid valve and a mass flow controller associated with the inert gas supply source are provided. As described above, even when the inert gas is added, the flow rate ratio of the oxygen gas to the COF ₂ gas is preferably 2 or less, and more preferably 0.2 to 0.3.

  In the above embodiment, the case of dry etching a silicon film such as a silicon nitride film in the thin film transistor 10 of the inverted stagger type and the channel protective film type is described, but the present invention is not limited to this. For example, as shown as an example in FIG. 14, in a reverse stagger type channel etch type thin film transistor 10, a silicon film such as a silicon nitride film may be dry etched.

  The thin film transistor panel shown in FIG. 14 is different from the thin film transistor panel shown in FIG. 1 in that the channel protective film 5 is not provided, and a recess 4 a is formed on the upper surface of the channel region of the semiconductor thin film 4 instead. It is. In this case, the thickness of the region other than the channel region of the semiconductor thin film 4 is larger than the thickness of the semiconductor thin film 4 shown in FIG.

  Next, an example of a method for manufacturing the thin film transistor panel will be described. First, as shown in FIG. 15, a gate electrode 2 is formed by patterning a metal film made of chromium or the like formed by sputtering at a predetermined location on the upper surface of the glass substrate 1 by photolithography.

  Next, a gate insulating film 3 made of silicon nitride, an intrinsic amorphous silicon film (film for forming a semiconductor thin film 4) 21 and an n-type amorphous silicon film (ohmic film) are formed on the upper surface of the glass substrate 1 including the gate electrode 2 by plasma CVD. Film for forming contact layers 6 and 7) 24 is formed. In this case, the thickness of the genuine amorphous silicon film 21 is larger than the thickness of the genuine amorphous silicon film 21 shown in FIG.

  Next, a source / drain electrode forming film 25 made of a metal such as chromium is formed on the upper surface of the n-type amorphous silicon film 24 by sputtering. Next, by patterning a resist film applied to the source electrode 8 formation region and the drain electrode 9 formation region on the upper surface of the source / drain electrode formation film 25 by a screen printing method, a spin coating method, or the like by a photolithography method. Then, resist films 26 and 27 are formed.

  Next, when the source / drain electrode formation film 25 is wet-etched using the resist films 26 and 27 as a mask, the source / drain electrode formation film 25 in the regions other than the regions under the resist films 26 and 27 is removed, as shown in FIG. As described above, the source electrode 8 and the drain electrode 9 are formed under the resist films 26 and 27.

  Next, the n-type amorphous silicon film 24 and the intrinsic amorphous silicon film 21 are successively dry etched using the resist films 26 and 27 as a mask. In this case, first, the n-type amorphous silicon film 24 in a region other than under the resist films 26 and 27 is removed, and ohmic contact layers 6 and 7 are formed under the source electrode 8 and the drain electrode 9 as shown in FIG. .

  Next, the intrinsic amorphous silicon film 21 in a region other than under the resist films 26 and 27 is half-etched, and the thickness of the intrinsic amorphous silicon film 21 in a region other than under the ohmic contact layers 6 and 7 is set as shown in FIG. make it thin. In this state, a recess 4 a is formed on the upper surface of the intrinsic amorphous silicon film 21 between the ohmic contact layers 6 and 7. Next, the resist films 26 and 27 are peeled off.

  Next, as shown in FIG. 19, a resist film applied by a screen printing method, a spin coating method, or the like is patterned on the upper surface of the source electrode 8, the drain electrode 9, and the concave portion 4a therebetween by a photolithography method. Thus, a resist film 30 is formed. Next, when the intrinsic amorphous silicon film 21 is dry-etched using the resist film 30 as a mask, the intrinsic amorphous silicon film 21 in a region other than the area under the resist film 30 is removed, and as shown in FIG. A semiconductor thin film 4 is formed.

  In this state, the gate electrode 2, the gate insulating film 3, the semiconductor thin film 4 having the recess 4 a, the ohmic contact layers 6 and 7, the source electrode 8, and the drain electrode 9 form an inverted stagger type channel etch type thin film transistor 10. ing. Next, the resist film 30 is peeled off. Thereafter, through the same steps as in the above case, the thin film transistor panel shown in FIG. 14 is obtained.

  Here, the dry etching of the n-type amorphous silicon film 24 and the intrinsic amorphous silicon film 21 in this case is performed in the thin film transistor panel provided with the thin film transistor 10 of the inverted staggered type and the channel protective film type. The same conditions may be used as when the amorphous silicon film 21 is dry-etched.

Further, in the thin film transistor panel including the inverted staggered type and the channel protective film type thin film transistor 10, the overcoat film 12 is formed using an etching gas made of COF ₂ alone or an etching gas made of a mixed gas of COF ₂ and oxygen gas. The same conditions may be used as in the case of dry etching.

  By the way, in the thin film transistor panel including the inverted staggered thin film transistor 10, the gate electrode external portion made of the same metal as the gate electrode 2 is formed on the upper surface of the glass substrate 1 regardless of the channel protective film type or the channel etch type. A connection terminal is provided connected to the gate electrode 2. A drain electrode external connection terminal made of the same metal as the drain electrode 9 is connected to the drain electrode 9 on the upper surface of the gate insulating film 3.

  In such a thin film transistor panel, when the opening 13 is formed in the overcoat film 12, an opening is formed in the overcoat film 12 and the gate insulating film 3 in a portion corresponding to the gate electrode external connection terminal, and Then, an opening is formed in the overcoat film 12 in a portion corresponding to the drain electrode external connection terminal. Therefore, the base of the overcoat film 12 includes, in addition to the pixel electrode 11 made of ITO, an external connection terminal for a gate electrode and an external connection terminal for a drain electrode made of a metal such as chromium.

  In the above-described embodiment, the case where dry etching is performed on a silicon compound film such as a silicon nitride film, a true amorphous silicon film, or an n-type amorphous silicon film in a thin film transistor using amorphous silicon has been described. is not. For example, in a thin film transistor using polycrystalline silicon, the polycrystalline silicon film formed on the upper surface of the silicon nitride film may be dry-etched. Further, in a thin film diode (TFD) using silicon, a silicon compound film formed on the upper surface of the silicon nitride film may be dry-etched.

DESCRIPTION OF SYMBOLS 1 Glass substrate 2 Gate electrode 3 Gate insulating film 4 Semiconductor thin film 4a Recessed part 5 Channel protective film 6, 7 Ohmic contact layer 8 Source electrode 9 Drain electrode 10 Thin film transistor 11 Pixel electrode 12 Overcoat film 13 Opening 21 Intrinsic amorphous silicon film 22 Nitride Silicon film 23 Resist film 24 N-type amorphous silicon film 25 Source / drain electrode formation film 26, 27 Resist film 28 Resist film 30 Resist film 31 Reaction vessel 32 Lower electrode 33 Upper electrode 34 High frequency power supply 35 Workpiece 37 Vacuum pump 38 Gas inlet pipe 42, 43 Solenoid valve 44, 45 Mass flow controller 46 COF ₂ gas supply source 47 Oxygen gas supply source 48 Chlorine gas supply source

Claims (22)

The silicon nitride film formed on the amorphous silicon film is dry-etched using the amorphous silicon film as a stopper by parallel plate type dry etching using an etching gas containing COF ₂ and oxygen gas , and is applied to the COF ₂ gas. A dry etching method for a film containing silicon, wherein a flow ratio of the oxygen gas is 0.5-4 .   According to the first aspect of the present invention, when an inverted stagger type channel protective film type thin film transistor is manufactured, the amorphous silicon film is a genuine amorphous silicon film, and the silicon nitride film is dried on the genuine amorphous silicon film. A dry etching method for a film containing silicon, wherein a channel protective film pattern is formed by etching. In the invention according to claim 1 or 2, the dry etching method of a film containing silicon, wherein the flow ratio of oxygen gas to COF ₂ gas is 1.5-2. In the invention described in any one of claims 1 to 3, the dry etching method of a film containing silicon, characterized in that it comprises the etching gas further inert gas. In the invention described in any one of claims 1 to 4, wherein the dry etching is a dry etching method of a film containing silicon, which comprises carrying out in a vacuum atmosphere of 1 to 100 Pa. The amorphous silicon film formed on the silicon nitride film is dry-etched using the silicon nitride film as a stopper by parallel plate type dry etching using an etching gas containing COF ₂ and chlorine gas , and COF ₂ against chlorine gas. A dry etching method for a film containing silicon , wherein a gas flow ratio is 0.1-1 . According to a sixth aspect of the present invention, when an inversely staggered channel protective film type thin film transistor is manufactured, the amorphous silicon film is dry-etched to form a semiconductor thin film on the gate insulating film made of the silicon nitride film. A dry etching method for a film containing silicon, characterized in that: The invention according to claim 6 or 7 , wherein the amorphous silicon film is a genuine amorphous silicon film formed on the silicon nitride film and an n-type amorphous silicon film formed on the genuine amorphous silicon film. A dry etching method for a film containing silicon, characterized by: In the invention according to claim 8 , when manufacturing an inverted staggered type channel protective film type thin film transistor, the n-type amorphous silicon film and the genuine amorphous silicon film are continuously dry-etched to form the silicon nitride film. A dry etching method for a film containing silicon, comprising: forming a semiconductor thin film on the gate insulating film, and forming an ohmic contact layer on both sides of the upper surface of the semiconductor thin film. 10. The dry etching method for a film containing silicon according to claim 6, wherein a flow rate ratio of the COF ₂ gas to the chlorine gas is 0.25 to 0.5. In the invention described in any one of claims 6 to 10, a dry etching method of a film containing silicon, wherein the dry etching is a dry etching by cathode coupling. In the invention described in any one of claims 6 to 10, a dry etching method of a film containing silicon, wherein the dry etching is a dry etching by anode coupling. In the invention described in any one of claims 6 to 12, a dry etching method of a film containing silicon, characterized in that it comprises the etching gas further inert gas. In the invention described in any one of claims 6 to 13, wherein the dry etching is a dry etching method of a film containing silicon, which comprises carrying out in a vacuum atmosphere of 1 to 100 Pa. The parallel plate type dry etching using an etching gas containing at least COF _2, characterized in that dry etching of the silicon nitride film formed on the base on which an ITO film or chromium, the ITO film or chromium as a stopper A dry etching method for a film containing silicon. In the invention according to claim 15 , when an inverted stagger type channel protective film type or channel etch type thin film transistor is manufactured, an opening is formed in the overcoat film made of the silicon nitride film in a portion corresponding to the base by dry etching. A dry etching method for a film containing silicon, characterized in that: 17. The dry etching method for a film containing silicon according to claim 16 , wherein the etching gas is a single COF ₂ gas. 17. The dry etching method for a film containing silicon according to claim 16 , wherein the etching gas is a mixed gas containing COF ₂ gas and oxygen gas. 19. The dry etching method for a film containing silicon according to claim 18 , wherein a flow ratio of oxygen gas to COF ₂ gas is 2 or less. In the invention of claim 18, the dry etching method of a film containing silicon, wherein the flow ratio of oxygen gas to COF ₂ gas is 0.2 to 0.3. In the invention according to any one of claims 15 to 20, the dry etching method of a film containing silicon, characterized in that it comprises the etching gas further inert gas. The dry etching method for a film containing silicon according to any one of claims 15 to 21 , wherein the dry etching is performed in a vacuum atmosphere of 1 to 100 Pa.

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