JP5458760B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device applicable to a high voltage IC for driving an inverter or the like.

  Suitable for motor control of automobiles such as electric vehicles (EV) and hybrid vehicles (HEV) that require high withstand voltage (about 1200V), for example, high voltage ICs for inverter driving etc. that can comprehensively cover withstand voltages of 150V to 1200V, For example, it is disclosed in Japanese Patent Application Laid-Open No. 2006-148058 (Patent Document 1) and Japanese Patent Application Laid-Open No. 2006-324626 (Patent Document 2).

  In the high voltage IC, a level shift circuit is used for signal transmission between a low voltage region (for example, ± 15 V) and a high voltage region (for example, 600 V or more). However, when the level shift circuit is composed of MOS transistor elements formed on an SOI (Silicon On Insulator) substrate, a single MOS transistor element requires a withstand voltage of 600 V or more, which is difficult. Invented are the semiconductor devices disclosed in Patent Documents 1 and 2, which secure the breakdown voltage by connecting the MOS transistor elements in series.

  FIG. 8 is a basic equivalent circuit diagram of the semiconductor device 10, which is the semiconductor device disclosed in Patent Document 1 used for the high voltage IC of the inverter drive circuit.

In the semiconductor device 10 shown in FIG. 8, the MOS transistor elements _Tr 1 to Tr _n of n that are insulated and separated from each other (n ≧ 2), the ground low reference potential as a reference at (GND) side (GND potential) and power source Are sequentially connected in series between a predetermined high reference potential Vs as a reference on the side, with the GND side as the first stage and the power supply side as the nth stage. The gate terminal of the first-stage MOS transistor element Tr ₁ is an input terminal of the semiconductor device 10. The output of the semiconductor device 10 is taken out from a power supply side terminal of the n-th stage MOS transistor element Tr _n via a load resistor (not shown) having a predetermined resistance value. In this way, the reference potential of the output signal is converted (level shift) from the GND potential on the GND side of the input signal to the high reference potential Vs on the power supply side, and the output signal is inverted with respect to the input signal. It is taken out with.

In the operation of the semiconductor device 10 of FIG. 8, the voltage between the GND potential and the high reference potential Vs is divided by _n MOS transistor elements Tr _{1 to} Tr n, and each MOS transistor element from the first stage to the n-th stage is divided. Tr _{1 to} Tr _n share the respective voltage ranges. Therefore, compared to the case where the voltage between the GND potential and the high reference potential Vs is shared by one MOS transistor element, the breakdown voltage required for each MOS transistor element Tr _{1 to} Tr _n is approximately ₁ / _n. Become. Therefore, even a MOS transistor element having a normal withstand voltage that can be manufactured inexpensively using a general manufacturing method is necessary as a whole by appropriately setting the number n of MOS transistor elements in the semiconductor device 10 of FIG. Therefore, the semiconductor device can ensure a high breakdown voltage.

  FIG. 9 is a diagram showing a specific example of the semiconductor device 10 of FIG. 8 shown in the circuit diagram, and is a diagram showing an arrangement of each circuit element of the semiconductor device 10 applied to the level shift circuit of the high voltage IC 100. FIG. 10 is a cross-sectional view taken along one-dot chain line AA in FIG. 9 and shows the structure of each MOS transistor element.

As shown in the sectional view of FIG. 10, in the high voltage IC 100, the SOI structure in which the _n MOS transistor elements Tr _{1 to} Tr n in the semiconductor device 10 of FIG. 8 applied to the level shift circuit have the buried oxide film 3. It is formed on the n-conductivity type SOI layer 1 a of the semiconductor substrate 1. Under the buried oxide film 3 is a thick support substrate 2 made of silicon (Si), and the SOI substrate 1 is formed by bonding the substrates.

The n MOS transistor elements Tr _{1 to} Tr _n are lateral MOS (LDMOS) transistor elements and are isolated from each other by an element isolation isolation trench 4 reaching the buried oxide film 3. In the semiconductor device 10 shown in FIG. 10, a high-concentration impurity layer 1b is formed on the buried oxide film 3 in the SOI layer 1a in order to shield high-frequency potential interference caused by switching in the floating reference gate drive circuit. Yes.

As shown in FIG. 9, in the semiconductor device 10 of the high voltage IC100 is, n heavy island isolation trenches _T 1 through T _n are formed, are n MOS transistor elements _Tr 1 to Tr _n, which are insulated and separated from each other , The island regions surrounded by the n-fold island isolation trenches T _{1 to} T _n are sequentially arranged one by one so as to include high-stage MOS transistor elements therein.

  FIG. 11 is a diagram illustrating an example of the semiconductor device disclosed in Patent Document 2, and is a schematic diagram illustrating a basic configuration of the semiconductor device 20.

  A semiconductor device 20 shown in FIG. 11 includes n (n ≧ 2) transistor elements Tr and a resistance element (a voltage dividing resistor) connected in parallel between a GND potential which is a low reference potential and a predetermined high reference potential Vs. ) R and capacitive element (smoothing capacitor) C are parallel RC elements, and are divided into n parallel RC elements. From another point of view, the configuration of the semiconductor device 20 in FIG. 11 includes a line of transistor elements Tr and a line of resistance elements R connected in series between a low reference potential and a high reference potential Vs similar to FIG. In addition to the configuration, a line of a capacitive element C connected in series between a low reference potential and a high reference potential Vs is added. In the semiconductor device 20 shown in FIG. 11, the line of the resistance element R connected in series divides between the gate voltages of the transistor element Tr with respect to the direct current. The line of the capacitive element C connected in series divides between the gate voltages of the transistor element Tr with respect to the alternating current. Therefore, in the semiconductor device 20 of FIG. 11, both direct current and alternating current can be divided. Further, the line of the capacitive element C connected in series also functions as a line for releasing a surge current when a dV / dt surge occurs when the resistance value of the resistance element R is large.

JP 2006-148058 A JP 2006-324626 A

  The capacitor C of the semiconductor device 20 shown in FIG. 11 can be realized with various structures as disclosed in Patent Document 2, but requires a relatively large capacitance value.

  FIG. 12 is a diagram showing a semiconductor device 21 as a specific example of the semiconductor device 20 of FIG. 11 shown in a circuit diagram. 12A is a schematic plan view showing the arrangement of each circuit element of the semiconductor device 21, and FIG. 12B is a cross-sectional view taken along one-dot chain line BB in FIG. 12A. (C) is sectional drawing in the dashed-dotted line CC of FIG. 12 (a). In the semiconductor device 21 of FIG. 12, the same reference numerals are given to the same parts as those of the semiconductor device 10 shown in FIGS.

Figure 12 (a) In the element isolation trenches 4, and 12 fold island insulation separating the island regions each MOS transistor elements _Tr 1 _{to Tr 12} is disposed in the MOS transistor elements _Tr 1 _{to Tr 12} The isolation trenches T _{1 to} T ₁₂ are indicated by thick lines. Further, in FIG. 12, the parasitic capacitance associated with the buried oxide film 3, the element isolation trenches 4 and the island isolation trenches T ₁ through T _12, shown in the position in dotted lines code.

In the semiconductor device 21 shown in FIG. 12, twelve MOS transistor elements Tr _{1 to} Tr ₁₂ are sequentially connected in series between the low-side GND and the high-side Vs. Further, twelve resistor elements R _{1 to} R ₁₂ corresponding to the voltage dividing resistor R in FIG. 11 and capacitor elements C _{1 to} C ₁₂ corresponding to the smoothing capacitor C are sequentially placed between the low-side GND and the high-side Vs. Connected in series.

As shown in FIG. 12B, the resistance elements R _{1 to} R ₁₂ are formed as thin films above the SOI substrate 1. Further, the capacitive elements C _{1 to} C ₁₂ are configured by two parallel-connected capacitive elements as illustrated by symbols. One capacitive element connected in parallel is a capacitive element having the field oxide film 5 on the SOI substrate 1 as a dielectric layer. Capacitive element is used as one electrode of each island region of the insulating isolated SOI layer 1a in 12 fold island isolation trenches T ₁ through T _n, it can be simultaneously potential fixing each island region This structure . The other capacitive element connected in parallel is a capacitive element having the interlayer insulating film 6 as a dielectric layer.

In the semiconductor device 21 of FIG. 12, since the capacitive elements C _{1 to} C ₁₂ that require a relatively large capacitance value are configured by the two parallel connected capacitive elements, the capacitive elements C _{1 to} C ₁₂ are occupied. The area is reduced and the size can be reduced. Further, since the capacitive elements C _{1 to} C ₁₂ are capacitive elements having the field oxide film 5 and the interlayer insulating film 6 as dielectric layers, no special manufacturing process is required, and the capacitive elements C _{1 to} C ₁₂ can be manufactured at low cost. However, in the semiconductor device 21 of FIG. 12, in a preliminary test, a problem of dead time in which the switching operation cannot be transiently generated for a certain period immediately after the high reference potential Vs that changes in a pulse manner is turned off occurs.

  Therefore, the present invention is a semiconductor device in which n (n ≧ 2) MOS transistor elements are connected in series between a low reference potential and a high reference potential, and can ensure a high breakdown voltage. Each line of the resistor element and the capacitor element is connected in series between a low reference potential and a high reference potential, and biases the gate terminals of the MOS transistor elements in each stage except for one stage in a direct current and alternating current manner. Accordingly, an object of the present invention is to provide an inexpensive semiconductor device in which a dead time does not occur even immediately after turning off a high reference potential that changes in a pulse manner.

  The semiconductor device according to claim 1, wherein n (n ≧ 2) MOS transistor elements are insulated from the SOI layer of the SOI structure semiconductor substrate having a buried oxide film by an element isolation trench that reaches the buried oxide film, respectively. Each of the islands formed in isolation is formed with n-layer island isolation trenches reaching the buried oxide film in the SOI layer, and the n MOS transistor elements are surrounded by the n-layer island isolation trenches. Each of the n MOS transistor elements is arranged between a predetermined low reference potential that is a reference on the ground (GND) side and a predetermined high reference potential that is a reference on the power supply side. Are connected in series, with the power supply side being the nth stage, and n resistance elements are connected between the low reference potential and the high reference potential, and the GND side is the first stage. Are connected in series, with the n-th stage being sequentially connected in series, and the gate terminals of the MOS transistor elements in each stage excluding the MOS transistor element in the first stage are respectively connected between the resistor elements in each stage connected in series. The n capacitive elements, which are sequentially connected and have the SOI layer of each island region as one electrode, are connected between the low reference potential and the high reference potential, the GND side is the first stage, and the power supply side is As the n-th stage, the gate terminals of the MOS transistor elements at least lower than the center except for the first-stage MOS transistor element are connected in series, and are connected between the capacitor elements of each stage connected in series. In the remaining high-stage MOS transistor elements, the capacitor elements are connected in series through diode elements having an anode on the capacitor side and a cathode on the gate terminal side. A gate terminal is sequentially connected between the capacitor elements of each stage connected in series, and the gate terminal of the MOS transistor element of the first stage is an input terminal, and the MOS transistor of the nth stage An output is taken out from the power supply side terminal of the element.

  The above semiconductor device has a high withstand voltage, in which n (n ≧ 2) MOS transistor elements formed by isolation in an SOI layer of an SOI structure semiconductor substrate are connected in series between a low reference potential and a high reference potential. This is a semiconductor device capable of ensuring the above.

  The semiconductor device has a line composed of n resistance elements connected in series between a low reference potential and a high reference potential, and the MOS transistor elements in each stage excluding the first stage MOS transistor element Gate terminals are sequentially connected between the n resistance elements constituting the line. That is, the n resistance elements constituting the line are DC voltage dividing resistors between the low reference potential and the high reference potential that bias the gate terminals of the MOS transistor elements in each stage except the first stage. Function as.

  The semiconductor device has a line composed of n capacitive elements connected in series between a low reference potential and a high reference potential, and is at least lower than the center excluding the first-stage MOS transistor element. The gate terminals of the MOS transistor elements of the stage are sequentially connected between the capacitor elements of the respective stages connected in series via diode elements having the capacitor element side as an anode and the gate terminal side as a cathode, respectively, The gate terminals of the high-stage MOS transistor elements are sequentially connected between the series-connected capacitive elements. The n capacitive elements constituting the line function as an AC voltage dividing element between the low reference potential and the high reference potential, and the gate terminals of the MOS transistor elements at each stage except for the first stage are AC. Biasing is performed in a state (for example, when the high reference potential changes in a pulse manner, at the rise and fall of the pulse).

  The n capacitive elements in the semiconductor device are capacitive elements each having an SOI layer in each island region surrounded by n-fold island insulating isolation trenches as one electrode, and can be manufactured at low cost. . On the other hand, according to a preliminary test, in a semiconductor device having an alternating voltage dividing line composed of n capacitive elements each having an SOI layer in each island region as one electrode, a high voltage that changes in a pulsed manner. There was a problem of dead time in which switching operation could not be performed transiently for a certain period immediately after the reference potential was turned off.

  When the problem of the dead time was analyzed in detail by simulation, it was found that the dead time occurs as follows. That is, a semiconductor in which a resistive element which is a DC voltage dividing element and a capacitive element which is an AC voltage dividing element connected in series between a low reference potential and a high reference potential each bias the gate terminal of the same MOS transistor element In the device, in the ON state of the high reference potential, the potential of the support substrate under the buried oxide film is about half of the high reference potential, and the potential of the island region where the MOS transistor element lower than the center is arranged is It becomes lower than the potential. Therefore, in the island region, the parasitic capacitance of the buried oxide film is charged through the SOI layer that is the electrode of the resistance element biasing the gate potential of the MOS transistor element arranged there and the capacitive element connected thereto. It is in the state. Next, when the high reference potential is turned off, the discharge of the parasitic capacitance of the charged buried oxide film is not in time, and the drain voltage in the low-stage MOS transistor element on the GND side becomes 0 V or less. For this reason, it was found that a dead time during which a switching operation cannot be performed transiently occurs for a certain period immediately after the high reference potential is turned off.

  Therefore, in the above semiconductor device, the gate terminal of at least the MOS transistor element lower than the center excluding the first-stage MOS transistor element is connected between the capacitor elements of each stage connected in series with the anode side of the capacitor element. A configuration is adopted in which the gate terminals are sequentially connected via diode elements having the cathode side as a cathode. According to this configuration, the resistor element and the capacitor element that bias the gate terminal of the same MOS transistor element are not directly connected but are clamped by the diode element, and in the ON state of the high reference potential, the resistor element is interposed. Charging of the parasitic capacitance of the buried oxide film is suppressed. Therefore, even immediately after the high reference potential is turned off next time, the drain voltage in the low-stage MOS transistor element on the GND side does not become 0 V or less, and it is possible to prevent the occurrence of the dead time in which the switching operation cannot be performed. . In the semiconductor device as well, the capacitor element uses each island region of the SOI layer insulated and isolated by the n-fold insulation isolation trench as one electrode, and the potential of each island region can be simultaneously fixed by this structure. .

  As described above, the above-described semiconductor device is a semiconductor device in which n (n ≧ 2) MOS transistor elements are connected in series between a low reference potential and a high reference potential to ensure a high breakdown voltage. A resistor element and a capacitor element connected in series between a low reference potential and a high reference potential for biasing the gate terminals of the MOS transistor elements in each stage except the first stage on the GND side in a DC and AC manner, respectively. Thus, an inexpensive semiconductor device in which dead time does not occur even immediately after turning off the high reference potential that changes in a pulse manner can be obtained.

In particular, as in the semiconductor device according to claim 2, the gate terminal of the MOS transistor of each remaining stage excluding the M OS transistor of the first stage, while the capacitive element of each stage which are series connected In addition, it is preferable that the capacitor elements are sequentially connected via diode elements having the capacitor element side as an anode and the gate terminal side as a cathode. According to this, the operating characteristics of the n MOS transistor elements can be made more uniform.

  In the semiconductor device, it is preferable that each of the n capacitive elements is a capacitive element having a field oxide film formed on the SOI layer as a dielectric layer. . According to this, a special process for manufacturing the capacitive element is not required, and it can be manufactured at low cost.

  According to a fourth aspect of the present invention, each of the n capacitive elements is connected in parallel with a second capacitive element having a dielectric layer as an interlayer insulating film formed above the SOI layer. It is good also as a structure. The capacitor element needs a relatively large capacitance value to function as an AC voltage dividing element between a low reference potential and a high reference potential. However, by adding the second capacitor element, the occupied area is increased. The capacitance value of the capacitive element can be substantially increased without enlarging the thickness or adding a special manufacturing process, and a small and inexpensive semiconductor device can be obtained.

  In the semiconductor device, as described in claim 5, for example, the n MOS transistor elements arranged one by one in each island region are sequentially, the MOS transistor elements in the inner island region are on the power supply side, A configuration in which the MOS transistor element in the outer island region is on the GND side is preferable in reducing the influence of wiring and noise.

  7. The semiconductor device according to claim 6, wherein the semiconductor device includes a GND reference gate drive circuit that uses the low reference potential as a reference, and a floating that uses a potential obtained by changing the low reference potential and the high reference potential in a pulse manner. A reference gate drive circuit, a control circuit for controlling the GND reference gate drive circuit and the floating reference gate drive circuit, and an input / output signal of the control circuit interposed between the control circuit and the floating reference gate drive circuit Is suitable for the level shift circuit in a high voltage IC for driving an inverter constituted by a level shift circuit that shifts the level between the low reference potential and the high reference potential.

  In a floating reference gate drive circuit in a high voltage IC for driving an inverter, two potentials changing in a pulse manner between a low reference potential and a high reference potential are used as a reference, and a semiconductor device applied to a level shift circuit is first This corresponds to the case where the exemplified high reference potential changes in a pulse manner.

  The high-voltage IC may be, for example, a high-voltage IC for driving an inverter of an in-vehicle motor as described in claim 7, or an inverter driving of an in-vehicle air conditioner as described in claim 8. It may be a high voltage IC.

13 is a simulation model of the semiconductor device 21 shown in FIG. As a result of the operation simulation of the semiconductor device 21, (a) shows the drain potential and output signal pulse Vp of each of the MOS transistor elements Tr _{1 to} Tr ₁₂ when the high reference potential Vs changes in a pulse manner between 15V and 1215V. It is the figure shown repeatedly, (b) is an enlarged view of the part enclosed with the dashed-dotted line in (a). 1A is a schematic plan view illustrating an arrangement of circuit elements of a semiconductor device 22, and FIG. 1B is a cross-sectional view taken along one-dot chain line DD in FIG. (C) is a cross-sectional view taken along one-dot chain line EE in (a). It is a simulation model of the semiconductor device 22 shown in FIG. As a result of the operation simulation of the semiconductor device 22, (a) shows the drain potentials and output signal pulses Vp of the MOS transistor elements Tr _{1 to} Tr ₁₂ when the high reference potential Vs changes in a pulse manner between 15V and 1215V. It is the figure shown repeatedly, (b) is an enlarged view of the part enclosed with the dashed-dotted line in (a). (A), (b), respectively, the diode elements _A a, a plan view and a sectional view of _{A b.} Resistive element Rc, is a plan view and a sectional view of the capacitor Cc and a diode element A _c. 1 is a basic equivalent circuit diagram of a semiconductor device 10 in a semiconductor device disclosed in Patent Document 1 used for a high voltage IC of an inverter drive circuit. FIG. 9 is a diagram showing a specific example of the semiconductor device 10 of FIG. 8 shown in the circuit diagram, and is a diagram showing the arrangement of each circuit element of the semiconductor device 10 applied to the level shift circuit of the high voltage IC 100. It is sectional drawing in the dashed-dotted line AA of FIG. 9, and is a figure which shows the structure of each MOS transistor element. 1 is a diagram illustrating an example of a semiconductor device disclosed in Patent Document 2, and is a schematic diagram illustrating a basic configuration of a semiconductor device 20. FIG. FIG. 12 is a diagram showing a semiconductor device 21 as a specific example of the semiconductor device 20 of FIG. 11 shown in a circuit diagram.

  DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings.

  First, an operation simulation of the semiconductor device 21 was performed in order to clarify the cause of the dead time that is a problem of the semiconductor device 21 shown in FIG.

FIG. 1 is a simulation model of the semiconductor device 21 shown in FIG. In FIG. 1, reference numeral PC3 is a parasitic capacitance associated with the buried oxide film 3, reference numeral PC4 is parasitic capacitance associated with the element isolation trenches 4, reference numeral PCT on the island isolation trenches _T 1 _{through T 12} An accompanying parasitic capacitance PC6 is a parasitic capacitance associated with the interlayer insulating film 6. Further, a portion surrounded by an alternate long and short dash line corresponds to one island region insulated and isolated by the island insulation isolation trench and a MOS transistor element, a resistance element, and a capacitance element associated therewith.

FIG. 2 shows an operation simulation result of the semiconductor device 21 shown in FIG. 12. FIG. 2A shows the MOS transistor elements Tr ₁ to Tr ₁ when the high reference potential Vs changes in a pulse manner between 15V and 1215V. FIG. 2B is a diagram in which the drain potential of Tr ₁₂ and the output signal pulse Vp are overlapped, and FIG. 2B is an enlarged view of a portion surrounded by an alternate long and short dash line in FIG.

The twelve capacitor elements C _{1 to} C ₁₂ of the semiconductor device 21 have the SOI layer 1a in each island region surrounded by the twelve double island isolation trenches T _{1 to} T ₁₂ as one electrode. Therefore, as shown in FIG. 1, the simulation model of the semiconductor device 21 includes lines L _{1 to} L ₁₂ that fix the potential of the SOI layer 1 a in each island region from the capacitive elements C _{1 to} C ₁₂ .

  In the semiconductor device 21 shown in FIG. 12, a dead time during which a switching operation cannot be performed transiently, as shown in FIG. 2B, for a certain period immediately after the high reference potential Vs (= 1200 V) that changes in pulses is turned off. A problem occurs.

It was found that the dead time shown in FIG. 2B occurs as follows by detailed analysis of the simulation result. That is, the resistance elements R _{1 to} R ₁₂ that are DC voltage dividing elements connected in series between the low reference potential and the high reference potential Vs and the capacitor elements C _{1 to} C ₁₂ that are AC voltage dividing elements are respectively the same MOS. In the semiconductor device 21 in which the gate terminals of the transistor elements Tr _{1 to} Tr ₁₂ are biased, the potential of the support substrate 2 under the buried oxide film 3 is about half of the high reference potential Vs in the ON state of the high reference potential Vs. The potential of the island region where the MOS transistor elements Tr _{1 to} Tr _{6 that} are lower than the center is 600 V is lower than the potential of the support substrate 2. Therefore, in the island region, the resistance elements R _{1 to} R ₆ biasing the gate potentials of the MOS transistor elements Tr _{1 to} Tr ₆ arranged there and the electrodes of the capacitive elements C _{1 to} C ₆ connected thereto. The parasitic capacitance PC3 of the buried oxide film 3 is charged through the SOI layer 1a. Next, when the high reference potential Vs is turned OFF, the charged parasitic capacitance PC3 of the buried oxide film 3 cannot be discharged in time, and as shown in FIG. 2B, the low-stage MOS transistor element on the ground (GND) side. The drain voltage in Tr _{1 to} Tr ₅ becomes 0V or less. For this reason, it has been found that a dead time during which a switching operation cannot be performed transiently occurs for a certain period immediately after the high reference potential Vs is turned off.

  Based on the above analysis results, the semiconductor device 22 of FIG. 3 in which the occurrence of dead time was prevented was invented.

  FIG. 3 is a diagram showing a semiconductor device 22 as an example of the semiconductor device according to the present invention. FIG. 3A is a schematic plan view showing the arrangement of each circuit element of the semiconductor device 22, and FIG. 3B is a cross-sectional view taken along one-dot chain line DD in FIG. (C) is sectional drawing in the dashed-dotted line EE of Fig.3 (a). In the semiconductor device 22 of FIG. 3, the same reference numerals are given to the same parts as those of the semiconductor device 21 shown in FIG. 3C is the same as the cross-sectional structure taken along the alternate long and short dash line CC of the semiconductor device 21 shown in FIG.

  FIG. 4 is a simulation model of the semiconductor device 22 shown in FIG. Also in the simulation model of the semiconductor device 22 of FIG. 4, the same reference numerals are given to the same parts as those of the simulation model of the semiconductor device 21 of FIG. 1.

FIG. 5 is an operation simulation result of the semiconductor device 22 shown in FIG. 4. FIG. 5A shows each MOS transistor element Tr ₁ to Tr ₁ when the high reference potential Vs changes in a pulse manner between 15V and 1215V. FIG. 5B is a diagram in which the drain potential of Tr ₁₂ and the output signal pulse Vp are overlapped, and FIG. 5B is an enlarged view of a portion surrounded by an alternate long and short dash line in FIG.

Compared to the semiconductor device 21 shown in FIG. 12, the semiconductor device 22 shown in FIG. 3 has the gate terminals of the remaining MOS transistor elements Tr _{2 to} Tr ₁₂ except for the first-stage MOS transistor element Tr ₁ connected in series. The capacitor elements C _{1 to} C ₁₂ are not directly connected to each other, but are sequentially connected via the diode elements A _{2 to} A ₁₂ having the capacitor element side as an anode and the gate terminal side as a cathode, respectively. The only difference is that Other structures of the semiconductor device 22 shown in FIG. 3 are the same as those of the semiconductor device 21 shown in FIG.

That is, the semiconductor device 22 shown in FIG. 3 includes n (n ≧ 2 and n = 12 in the example of the semiconductor device 22 in FIG. 3) MOS transistors Tr _{1 to} Tr _{12 in} which the SOI having the buried oxide film 3. The SOI layer 1a of the structural semiconductor substrate 1 is formed by being isolated by element isolation trenches 4 reaching the buried oxide film 3 respectively. In addition, n-layer island isolation isolation trenches T _{1 to} T ₁₂ reaching the buried oxide film 3 are formed in the SOI layer 1a, and the n MOS transistor elements Tr _{1 to} Tr ₁₂ are connected to the n-layer island isolation isolation trench T _1. are arranged one by one in each island region surrounded by the through T _12. The n MOS transistor elements Tr _{1 to} Tr ₁₂ are arranged in a first stage between the GND side between a predetermined low reference potential that is a reference on the ground (GND) side and a predetermined high reference potential Vs that is a reference on the power supply side. The power supply side is connected in series with the nth stage.

Further, n resistance elements R _{1 to} R ₁₂ are sequentially connected in series between the low reference potential and the high reference potential, with the GND side as the first stage and the power supply side as the nth stage. The gate terminals of the remaining MOS transistor elements Tr _{2 to} Tr ₁₂ in the remaining stages excluding the MOS transistor element Tr ₁ in the stage are sequentially connected between the resistance elements R _{1 to} R _{12 in} the respective stages connected in series. It is connected.

Further, n-number of capacitance elements _C 1 _{-C 12} for the SOI layer 1a of each island region surrounded by the n-fold of the island isolation trenches _T 1 _{through T 12} and each one of the electrodes, the low reference potential and high Between the reference potentials Vs, the GND side is the first stage and the power supply side is the nth stage, which are sequentially connected in series.

The n capacitive elements C _{1 to} C ₁₂ will be described in more detail. As shown in FIG. 3B, each of the n capacitive elements C _{1 to} C ₁₂ includes a first capacitive element and a second capacitive element connected in parallel. . The first capacitor element is a capacitor element in which the field oxide film 5 formed on the SOI layer 1a is a dielectric layer, the SOI layer 1a in each island region under the field oxide film 5 is used as one electrode, The wiring layer formed on the field oxide film 5 is used as the other electrode. The second capacitor element is a capacitor element having an interlayer insulating film 6 formed above the SOI layer 1a as a dielectric layer, and the upper and lower wiring layers sandwiching the interlayer insulating film 6 are used as electrodes. The first capacitor element using the field oxide film 5 as a dielectric layer and the second capacitor element using the interlayer insulating film 6 as a dielectric layer do not require a special process for manufacturing, and are manufactured at low cost. be able to. Alternatively, the capacitive elements C _{1 to} C ₁₂ may be configured by only the first capacitive element having the field oxide film 5 as a dielectric layer. However, as will be described later, the capacitive elements C _{1 to} C ₁₂ require a relatively large capacitance value in order to function as an AC voltage dividing element between the low reference potential and the high reference potential Vs. When the capacitor element alone is used, the area occupied by the capacitor element increases. By adding the second capacitor element having the interlayer insulating film 6 as a dielectric layer, the capacitance value can be increased without increasing the occupied area or adding a special manufacturing process. An inexpensive semiconductor device can be obtained.

In the semiconductor device 22 of FIG. 3, MOS transistor elements _Tr 1 _{to Tr 12} of n which are arranged one by one in each island region surrounded by the n-fold of the island isolation trenches _T 1 _{through T 12} are sequentially The MOS transistor element in the inner island region is on the power supply side, and the MOS transistor element in the outer island region is on the GND side. This configuration is preferable for reducing the influence of wiring and noise. However, the present invention is not limited to this, and conversely, in the n MOS transistor elements Tr _{1 to} Tr ₁₂ , the MOS transistor elements in the inner island region are sequentially on the GND side, and the MOS transistor elements in the outer island region are on the power source side. It is good also as a certain structure.

In the semiconductor device 22 of FIG. 3, unlike the semiconductor device 21 of FIG. 12, the gate terminals of the remaining MOS transistor elements Tr _{2 to} Tr ₁₂ except for the first-stage MOS transistor element Tr ₁ are connected in series. between a capacitor which is connected _C 1 _{-C 12} of each stage, through the diode element _a 2 _{to a 12} in which the gate terminal side and the cathode to the capacitor _C 1 _{-C 12} side and the anode, respectively, sequentially connected Has been.

The semiconductor device 22 shown in FIG. 3 has the gate terminal of the first-stage MOS transistor element Tr ₁ as an input terminal and the power supply side of the n-th stage MOS transistor element Tr ₁₂ in the same manner as the semiconductor device 21 shown in FIG. Output is taken from the terminal.

In the semiconductor device 22 shown in FIG. 3, n (n ≧ 2) MOS transistor elements Tr _{1 to} Tr ₁₂ formed by being isolated from the SOI layer 1a of the SOI structure semiconductor substrate 1 have a low reference potential and a high reference potential. This is a semiconductor device that is connected in series between Vs and can ensure a high breakdown voltage.

As shown in FIG. 4, the semiconductor device 22 has a line composed of n resistance elements R _{1 to} R ₁₂ connected in series between a low reference potential and a high reference potential Vs. The gate terminals of the MOS transistor elements Tr _{2 to} Tr ₁₂ in each stage excluding the MOS transistor element Tr ₁ are sequentially connected between the n resistance elements R _{1 to} R ₁₂ constituting the line. . That is, the n resistance elements R _{1 to} R ₁₂ constituting the line bias the gate terminals of the MOS transistor elements Tr _{2 to} Tr ₁₂ in each stage except the first stage, and have a low reference potential and a high level. Functions as a DC voltage dividing resistor between reference potentials.

The semiconductor device 22 has a line composed of n capacitive elements C _{1 to} C ₁₂ connected in series between the low reference potential and the high reference potential Vs, and the first stage MOS transistor element Tr. The gate terminals of the remaining MOS transistor elements Tr _{2 to} Tr ₁₂ except for ₁ are connected between the capacitive elements C _{1 to} C ₁₂ of each stage connected in series, and the capacitive elements C _{1 to} C ₁₂ side are anodes. Are sequentially connected via diode elements A _{2 to} A ₁₂ having the gate terminal side as a cathode. Therefore, as can be seen from FIG. 4, unlike the semiconductor device 21 of FIG. 1, the resistance elements R _{2 to} R ₁₂ are directly connected to the island regions surrounded by the n-fold island isolation trenches T _{1 to} T _12. Absent. The n capacitive elements C _{1 to} C ₁₂ constituting the line function as AC voltage dividing elements between the low reference potential and the high reference potential Vs, and the MOS transistors in each stage except the first stage The gate terminals of the elements Tr _{2 to} Tr ₁₂ are biased in an alternating state (for example, when the high reference potential Vs shown in FIG. 5A changes in a pulse manner, at the rise and fall of the pulse).

The n capacitive elements C _{1 to} C ₁₂ in the semiconductor device 22 are capacitive elements each having the SOI layer 1a in each island region surrounded by n-fold island insulating isolation trenches T _{1 to} T ₁₂ as one electrode. As described above, it can be manufactured at low cost. On the other hand, according to a preliminary test, the semiconductor of FIG. 12 having an alternating voltage dividing line composed of n capacitive elements C _{1 to} C ₁₂ each having the SOI layer 1a of the same island region as one electrode. In the device 21, as described with reference to FIGS. 1 and 2, there is a problem of dead time in which the switching operation cannot be performed transiently for a certain period immediately after the high reference potential Vs that changes in a pulsed manner is turned off.

Similarly, as described with reference to FIGS. 1 and 2, when the problem of the dead time was analyzed by simulation, it was found that the dead time occurs as follows. That is, the resistance elements R _{1 to} R ₁₂ that are DC voltage dividing elements connected in series between the low reference potential and the high reference potential Vs and the capacitor elements C _{1 to} C ₁₂ that are AC voltage dividing elements are respectively the same MOS. In the semiconductor device 21 that biases the gate terminals of the transistor elements Tr _{2 to} Tr ₁₂ , the potential of the support substrate 2 under the buried oxide film 3 becomes about half of the high reference potential Vs when the high reference potential Vs is ON. , through the SOI layer 1a is an electrode of the capacitor _C 1 -C ₇ that the resistance element _R 1 to R ₇ which biases the gate potential of MOS transistor elements _Tr 2 to Tr ₆ of the low-stage the center connected thereto, The parasitic capacitance PC3 of the buried oxide film 3 is charged. Then high reference potential Vs is turned OFF, discharge too late parasitic capacitance PC3 of the buried oxide film 3 has been charged, the drain voltage becomes 0V or less in the MOS transistor elements _Tr 2 to Tr ₆ of the low-stage of the GND side . For this reason, it has been found that a dead time during which a switching operation cannot be performed transiently occurs for a certain period immediately after the high reference potential Vs is turned off.

Therefore, in the semiconductor device 22 shown in FIGS. 3 and 4, the gate terminals of the MOS transistor elements Tr _{2 to} Tr ₁₂ in each stage excluding the first stage MOS transistor element Tr ₁ are connected in series. The capacitor elements C _{1 to} C ₁₂ are sequentially connected via diode elements A _{2 to} A ₁₂ having the capacitor elements C _{1 to} C ₁₂ as an anode and the gate terminal side as a cathode, respectively. Adopted. According to this configuration, the resistor element Ri (i = 2,..., N) that biases the gate terminal of the same MOS transistor element and the capacitor element Ci are not directly connected but are clamped by the diode element Ai. In the ON state of the high reference potential Vs, charging of the parasitic capacitance PC3 of the buried oxide film 3 via the resistance element Ri is suppressed. Therefore, in the semiconductor device 22, as shown in FIG. 5, immediately after the high reference potential Vs is turned off, the low-stage MOS transistor elements Tr _{1 to} Tr on the GND side as shown in the simulation result of FIG. The drain voltage at ₆ does not become 0 V or less, and it is possible to prevent the occurrence of dead time in which the switching operation cannot be performed. In the semiconductor device 22 shown in FIG. 3 and FIG. 4 as well, the capacitive elements C _{1 to} C ₁₂ connected in series are formed of the SOI layer 1 a that is insulated and separated by n-fold island insulation isolation trenches T _{1 to} T ₁₂ . Each island region is used as one electrode. With this structure, the potential of each island region can be fixed simultaneously in a transient state when the high reference potential Vs is ON and OFF.

As can be seen from the above description, the insertion of the diode element is not necessary for all the MOS transistor elements Tr _{2 to} Tr ₁₂ except the first-stage MOS transistor element Tr ₁ . The gate terminals of at least the lower-stage MOS transistor elements Tr _{2 to} Tr ₆ excluding the first-stage MOS transistor element Tr ₁ are connected between the series-connected capacitive elements C _{1 to} C ₇ . The remaining high-stage MOS transistor elements Tr _{7 to} Tr ₁₂ are sequentially connected via diode elements A _{2 to} A ₆ having the capacitive elements C _{1 to} C ₇ as an anode and the gate terminal side as a cathode, respectively. the gate terminal of the, between the series connected capacitive elements C ₇ -C ₁₂ for each stage, respectively, may be formed by sequentially connection configuration. However, like the semiconductor device 22 of FIG. 3, by inserting the diode elements A _{2 to} A ₁₂ into all the MOS transistor elements Tr _{2 to} Tr ₁₂ except the first-stage MOS transistor element Tr ₁ , The operating characteristics of the _twelve MOS transistor elements Tr _{1 to} Tr ₁₂ can be made more uniform.

6 and 7 are diagrams showing examples of forming the diode elements A _{2 to} A ₁₂ , respectively. FIG 6 (a), (b), respectively, the diode elements _A a, a plan view and a sectional view of _{A b,} 7, resistive element Rc, plan view of the capacitor Cc and a diode element _{A c} and section FIG. In FIGS. 6 and 7, the same parts as those in FIG.

The diode elements A _a and A _b shown in FIGS. _6A and _6B are both diode elements made of polycrystalline silicon, and the diode element A _a shown in FIG. Diode elements having conductive type regions arranged side by side on field oxide film 5. The diode element Ab shown in FIG. _6B is a diode element in which a p-conductivity type region and an n-conductivity type region are stacked on the field oxide film 5 and arranged in a vertical arrangement.

A diode element _Ac shown in FIG. 7 is also a diode element made of polycrystalline silicon, and is a diode element in which a p conductivity type region and an n conductivity type region are arranged side by side on the interlayer insulating film 6. As in the diode element _Ac of FIG. 7, the space can be saved by forming on the capacitor element Cc together with the voltage dividing resistor Rc.

The diode elements A _{2 to} A ₁₂ in the semiconductor device 22 in FIG. 3 are not limited to the formation examples in FIGS. 6 and 7, and are formed in, for example, the SOI layer 1 a that is insulated and separated by the element insulation isolation trench 4. It may be a diode element or a diode element formed as a separate element on a substrate different from the SOI substrate 1.

  As described above, each of the semiconductor devices described above can ensure a high breakdown voltage in which n (n ≧ 2) MOS transistor elements are connected in series between the low reference potential and the high reference potential Vs. A semiconductor device that can be connected in series between a low reference potential and a high reference potential Vs that bias the gate terminals of the MOS transistor elements of each stage excluding the first stage on the GND side in a direct and alternating manner. In addition, it is possible to provide an inexpensive semiconductor device that includes each line of the resistor element and the capacitor element and does not generate a dead time even immediately after the high reference potential Vs that changes in a pulse manner is turned off.

  Therefore, the semiconductor device includes a GND reference gate driving circuit based on the low reference potential, a floating reference gate driving circuit based on a potential obtained by changing the low reference potential and the high reference potential Vs in a pulse manner, A GND reference gate driving circuit, a control circuit for controlling the floating reference gate driving circuit, and an input / output signal of the control circuit that is interposed between the control circuit and the floating reference gate driving circuit and the low reference potential In a high voltage IC for driving an inverter constituted by a level shift circuit for level shifting between the high reference potentials, it is suitable for the level shift circuit.

  In a floating reference gate drive circuit in a high voltage IC for driving an inverter, two potentials changing in a pulse manner between a low reference potential and a high reference potential are used as a reference, and a semiconductor device applied to a level shift circuit is first This corresponds to the case where the exemplified high reference potential changes in a pulse manner.

  The high voltage IC may be, for example, a high voltage IC for driving an inverter of an in-vehicle motor, or a high voltage IC for driving an inverter of an in-vehicle air conditioner.

10,20～22 semiconductor device Tr ₁ to Tr ₁₂ MOS transistor element _{R, R 1 ~R 12, R} c resistive element _{C, C 1 ~C 12, C} c capacitive element A ₂ ~A _12, Aa~A _c diode Element 1 SOI structure semiconductor substrate (SOI substrate)
1a SOI layer 2 supporting substrate 3 buried oxide film T ₁ through T ₁₂ island isolation trenches 4 element isolation trenches 5 field oxide film 6 interlayer insulating film

Claims (8)

n (n ≧ 2) MOS transistor elements are formed on the SOI layer of the SOI structure semiconductor substrate having a buried oxide film by being insulated and separated by element isolation trenches that reach the buried oxide film,
An n-fold island insulating isolation trench reaching the buried oxide film is formed in the SOI layer,
The n MOS transistor elements are arranged one by one in each island region surrounded by the n-fold island isolation trench,
The n MOS transistor elements have a first stage on the GND side and a first stage on the power supply side between a predetermined low reference potential that is a reference on the ground (GND) side and a predetermined high reference potential that is a reference on the power supply side. n stages are connected in series,
n resistance elements are sequentially connected in series between the low reference potential and the high reference potential, with the GND side as the first stage and the power supply side as the nth stage,
The gate terminals of the MOS transistor elements of each stage excluding the MOS transistor element of the first stage are sequentially connected between the resistor elements of the respective stages connected in series.
The n capacitive elements each having the SOI layer in each island region as one electrode are sequentially connected in series between the low reference potential and the high reference potential, with the GND side as the first stage and the power supply side as the nth stage. Connected,
The gate terminal of at least the lower-stage MOS transistor element excluding the first-stage MOS transistor element has a capacitor element side as an anode and a gate terminal side as a cathode between the series-connected capacitor elements. Each is connected sequentially through the diode elements
The gate terminals of the remaining high-stage MOS transistor elements are sequentially connected between the series-connected capacitive elements, respectively.
The gate terminal in the MOS transistor element of the first stage is an input terminal,
An output is taken out from a terminal on the power supply side in the n-th stage MOS transistor element. n (n ≧ 2) MOS transistor elements are formed on the SOI layer of the SOI structure semiconductor substrate having a buried oxide film by being insulated and separated by element isolation trenches that reach the buried oxide film,
An n-fold island insulating isolation trench reaching the buried oxide film is formed in the SOI layer,
The n MOS transistor elements are arranged one by one in each island region surrounded by the n-fold island isolation trench,
The n MOS transistor elements have a first stage on the GND side and a first stage on the power supply side between a predetermined low reference potential that is a reference on the ground (GND) side and a predetermined high reference potential that is a reference on the power supply side. n stages are connected in series,
n resistance elements are sequentially connected in series between the low reference potential and the high reference potential, with the GND side as the first stage and the power supply side as the nth stage,
The gate terminals of the MOS transistor elements of each stage excluding the MOS transistor element of the first stage are sequentially connected between the resistor elements of the respective stages connected in series.
The n capacitive elements each having the SOI layer in each island region as one electrode are sequentially connected in series between the low reference potential and the high reference potential, with the GND side as the first stage and the power supply side as the nth stage. Connected,
The gate terminals of the remaining MOS transistor elements of the respective stages excluding the first-stage MOS transistor elements are connected between the capacitor elements of the respective stages connected in series, and the capacitor element side is an anode and the gate terminal side is a cathode. via the diode element, respectively, Ri Na are sequentially connected,
The gate terminal in the MOS transistor element of the first stage is an input terminal,
Semiconductors devices outputted from the power supply side terminal of the MOS transistor of the n-th stage is characterized <br/> Rukoto retrieved.   3. The semiconductor device according to claim 1, wherein each of the n capacitive elements is a capacitive element having a field oxide film formed on the SOI layer as a dielectric layer.   4. The second capacitor element having a dielectric layer as an interlayer insulating film formed above the SOI layer is connected in parallel to each of the n capacitor elements. 5. The semiconductor device as described in any one.   The n MOS transistor elements arranged one by one in each island region are such that, in order, the MOS transistor elements in the inner island region are on the power supply side, and the MOS transistor elements in the outer island region are on the GND side. The semiconductor device according to any one of claims 1 to 4. The semiconductor device is
A GND reference gate drive circuit based on the low reference potential, a floating reference gate drive circuit based on a potential obtained by pulse-changing the low reference potential and the high reference potential, the GND reference gate drive circuit, and the floating A control circuit for controlling a reference gate driving circuit, and interposed between the control circuit and the floating reference gate driving circuit, and the input / output signals of the control circuit are leveled between the low reference potential and the high reference potential In a high voltage IC for driving an inverter constituted by a level shift circuit to be shifted,
6. The semiconductor device according to claim 1, which is applied to the level shift circuit.   The semiconductor device according to claim 6, wherein the high voltage IC is a high voltage IC for driving an inverter of a vehicle-mounted motor.   7. The semiconductor device according to claim 6, wherein the high voltage IC is a high voltage IC for driving an inverter of an in-vehicle air conditioner.

Images