JP5459617B2 - Electrophoretic display device driving method, electrophoretic display device, and electronic apparatus - Google Patents

Description

  The present invention relates to a method for driving an electrophoretic display device, an electrophoretic display device, and an electronic apparatus.

  2. Description of the Related Art As an active matrix electrophoretic display device, one having a switching transistor and a memory circuit (SRAM: Static Random Access Memory) in a pixel is known (see Patent Document 1).

JP 2008-268853 A

  In the electrophoretic display device described in Patent Document 1, in order to display an image, a potential corresponding to either high level or low level is stored in an SRAM (pixel SRAM circuit) provided in the pixel. And the display was performed by applying the voltage based on the memorize | stored electric potential to a microcapsule.

However, in this type of electrophoretic display device, for example, when a black background is displayed as “12:34” on a white background, the current display black character “4: 4” is rewritten. ”Is written in the SRAM of each pixel, and the black character“ 4 ”is erased to make this portion white, and then the black image“ 5 ”is displayed. It is necessary to display the black “5” by writing in the SRAM of the pixel. Thus, when a part of the display is rewritten, it is necessary to input an image signal at least twice. Further, in this case, there is a problem that a period in which white characters are displayed is generated, so that the quality is not sufficient for display on the digital watch.
For example, in the case of performing four-tone display of black, dark gray, light gray, and white, after rewriting the display by writing an image signal designating at least a black and white writing area to the SRAM of each pixel. Therefore, it is necessary to rewrite the image signal for designating the dark gray and light gray writing area to the SRAM and perform the second rewriting. That is, it is necessary to input an image signal at least twice in order to perform four gradation display.

  The present invention has been made in view of the above problems, and drives an electrophoretic display device capable of reducing the number of times of data transfer when switching display images and reducing power consumption for data transfer. An object is to provide a method, an electrophoretic display device, and an electronic device. In addition, the driving method for changing the density of the pixels whose density is changed is that the current display gradually disappears and the next display gradually appears regardless of the first or second gradation (for example, white or black). It is an object of the present invention to provide an electrophoretic display device driving method, an electrophoretic display device, and an electrophoretic display device with improved display quality.

  In order to solve the above-described problem, the electrophoretic display device driving method of the present invention includes an electrophoretic element including electrophoretic particles sandwiched between a pair of substrates, and includes a display unit including a plurality of pixels. A pixel electrode formed for each pixel on the display; a counter electrode facing the plurality of pixel electrodes via the electrophoretic element; a first control line connected to each of the pixels; A first set of control lines composed of a second control line, a second set of control lines composed of a third control line and a fourth control line, and image signal data for each pixel. A first memory circuit that stores data, a data line that supplies image signal data, a first pixel switching element that connects the first memory circuit, the pixel electrode, and the first set of control lines A first connection connecting either one of the control lines. A second memory circuit that stores data of the image signal, a second pixel switching element that connects the data line and the second memory circuit, the pixel electrode, and the second set And a second switch circuit that connects any one of the control lines to the control line, the method for driving an electrophoretic display device, wherein the first memory is connected via the first pixel switching element. A first step of inputting image signal data to the circuit and inputting the image signal data to the second memory circuit via the second pixel switching element; and an output from the first memory circuit. And a second step of controlling the first switch circuit based on an output from the second memory circuit based on an output from the second memory circuit.

  According to this configuration, in the data transfer period (first step) of the image display operation, the pixel that changes the gradation display from the first gradation display or the second gradation display, and the first gradation display Alternatively, the image signal data input to the first memory circuit and the second memory circuit can be different image data from the second gradation display to a pixel whose gradation display is not changed. Thereby, the image signal of the pixel that changes the gradation display from the first gradation and the pixel that does not change the gradation display, the pixel that changes the gradation display from the second gradation, and the pixel that does not change the gradation display are displayed. Since the data transfer can be performed by a single data transfer, power consumption for the data transfer can be reduced. In the data display period (second step) of the image display operation, the pixel electrode of each pixel is connected to the first control line or the second control line via the first switch circuit. To the third control line or the fourth control line. Therefore, by supplying a potential to the first control line to the fourth control line, or by setting a high impedance state (Hi-Z state), the potentials of the pixel electrodes in pixels having different image signal data are different from each other. can do. Accordingly, in the data display period, the pixel that changes the gradation display from the first gradation display to the second gradation or another gradation (third gradation), and the second gradation display A display change in which the current display gradually disappears and the next display gradually appears at the same time as the pixel changing the gradation display to the first gradation or another gradation (fourth gradation). It becomes possible to make it. In other words, when the user visually recognizes the display unit, there is a blank display period when switching the display image, or the display is smoothly displayed so as not to feel uncomfortable due to sudden switching from the previous image to the next image. Switchable display can be realized and display quality can be improved.

In addition, the driving method of the electrophoretic display device of the present invention includes an electrophoretic element including electrophoretic particles sandwiched between a pair of substrates, and includes a display unit including a plurality of pixels. From a pixel electrode formed for each pixel, a counter electrode facing the plurality of pixel electrodes via the electrophoretic element, and a first control line and a second control line connected to each of the pixels A first set of control lines, a second set of control lines consisting of a third control line and a fourth control line, and a first set of image signal data stored for each pixel. Any one of a memory circuit, a data line for supplying image signal data, and a first pixel switching element that connects the first memory circuit, and a control line in the pixel electrode and the first set of control lines A first switch circuit for connecting the Any one of a second memory circuit that stores the data, a second pixel switching element that connects the data line and the second memory circuit, and a control line in the pixel electrode and the second set of control lines And a second switch circuit for connecting the image signal data to the first memory circuit via the first pixel switching element. A first step of inputting and inputting image signal data to the second memory circuit via the second pixel switching element, and the first switch circuit based on an output from the first memory circuit And controlling the second switch circuit based on an output from the second memory circuit, and in the first step, the second control line and the image The first memory that controls the pixels that do not change the gradation display of the data of the first set of image signals, in which the electrodes are connected and the fourth control line and the pixel electrode are connected. A second set of image signals that are input to the circuit and the second memory circuit, the second control line and the pixel electrode are connected, and the third control line and the pixel electrode are connected. Is input to the first memory circuit and the second memory circuit that control the pixel that changes the gradation display from the first gradation display to the second gradation display, and the first memory circuit The data of the third set of image signals, in which the control line and the pixel electrode are connected, and the fourth control line and the pixel electrode are connected, is transferred from the second gradation display to the first floor. The first memory circuit and the second memory that control the pixels that change the gradation display to the gradation display. In the second step, the second wave is input to the first control line while inputting a rectangular wave that repeats the first potential and the second potential to the counter electrode for one period or more in the second step. A high impedance state in which the third control line and the fourth control line are electrically disconnected, respectively, and the second control line is supplied with the potential input to the counter electrode. The first control line and the second control line while inputting a rectangular wave that repeats the first potential and the second potential to the counter electrode for one period or more. In a high impedance state where each is electrically disconnected, the first potential is supplied to the third control line, and the potential input to the counter electrode is supplied to the fourth control line. Repeatedly display step and And wherein the door.

  In the first step, in the pixel in which the data of the first set of image signals is input to the first memory circuit and the second memory circuit, the electrophoretic particles do not migrate in the second step, and the level in the previous display is reduced. The gradation display (the gradation display of the first gradation or the second gradation) is not changed. Further, in the first step, the pixels in which the data of the second set of image signals are input to the first memory circuit and the second memory circuit are positively charged electrophoretic particles and negatively charged. Electrophoretic particles do not migrate in the first display step of the second step, but migrate in the second display step. On the other hand, in the first step, the pixels in which the data of the third set of image signals are input to the first memory circuit and the second memory circuit are positively charged electrophoretic particles and negatively charged. Electrophoretic particles migrate in the first display step of the second step and do not migrate in the second display step. In the second step, the first display step and the second display step are alternately repeated, so that the pixel whose gradation display is changed is changed to the first display or the second gradation display. At the same time, regardless of whether or not there is a display change, the previous display gradually disappears and the next display gradually appears. That is, the display can be changed smoothly, and the display quality can be improved.

In addition, the driving method of the electrophoretic display device of the present invention includes an electrophoretic element including electrophoretic particles sandwiched between a pair of substrates, and includes a display unit including a plurality of pixels. From a pixel electrode formed for each pixel, a counter electrode facing the plurality of pixel electrodes via the electrophoretic element, and a first control line and a second control line connected to each of the pixels A first set of control lines, a second set of control lines consisting of a third control line and a fourth control line, and a first set of image signal data stored for each pixel. Any one of a memory circuit, a data line for supplying image signal data, and a first pixel switching element that connects the first memory circuit, and a control line in the pixel electrode and the first set of control lines A first switch circuit for connecting the Any one of a second memory circuit that stores the data, a second pixel switching element that connects the data line and the second memory circuit, and a control line in the pixel electrode and the second set of control lines And a second switch circuit for connecting the image signal data to the first memory circuit via the first pixel switching element. A first step of inputting and inputting image signal data to the second memory circuit via the second pixel switching element, and the first switch circuit based on an output from the first memory circuit And controlling the second switch circuit based on the output from the second memory circuit, and in the first step, the first control line and the image The first set of image data that controls the pixel that displays the first gradation is set to the data of the first set of image signals that are connected to the electrode and the third control line is connected to the pixel electrode. The second set of memory circuits and the second memory circuit are connected, the second control line and the pixel electrode are connected, and the fourth control line and the pixel electrode are connected. Data of an image signal is input to the first memory circuit and the second memory circuit that control the pixel that displays the second gradation, and the first control line and the pixel electrode are connected to each other. Changing the gradation display from the first gradation display to the third gradation display for the data of the third set of image signals in which the fourth control line and the pixel electrode are connected. Input to the first memory circuit and the second memory circuit for controlling a pixel, and the second control line And the pixel electrode are connected and the third control line and the pixel electrode are connected. Data of a fourth set of image signals is displayed from the second gradation display to the fourth gradation display. To the first memory circuit and the second memory circuit that control the pixel that changes the gradation display, and in the second step, the first potential and the second potential with respect to the counter electrode The second potential is supplied to the first control line, the first potential is supplied to the second control line, and the third control is performed while inputting a rectangular wave that repeats the potential for one period or more. A first display step for bringing the line and the fourth control line into a high impedance state electrically disconnected, and a rectangular wave that repeats the first potential and the second potential with respect to the counter electrode While inputting more than one period, the first control line and the second control line A second display for supplying the second potential to the third control line and supplying the first potential to the fourth control line, in a high impedance state in which the control lines are electrically disconnected. And the step of performing the second display step subsequent to the first display step .

  In the first step, in the pixel in which the data of the first set of image signals is input to the first memory circuit and the second memory circuit, the electrophoretic particles do not migrate in the second step, and the level in the previous display is reduced. The tone display (the tone display of the first tone) is not changed. In addition, in the first step, the pixels in which the data of the second set of image signals are input to the first memory circuit and the second memory circuit are not subjected to electrophoretic particles in the second step, and the pre-display The gradation display (gradation display of the second gradation) is not changed. Further, in the first step, the pixels in which the data of the third set of image signals are input to the first memory circuit and the second memory circuit are positively charged in the second display step of the second step. Both the electrophoretic particles and the negatively charged electrophoretic particles migrate to change the gradation display smoothly from the first gradation to the third gradation. Further, in the first step, the pixels in which the data of the fourth set of image signals are input to the first memory circuit and the second memory circuit are positively charged in the second display step of the second step. Both the electrophoretic particles and the negatively charged electrophoretic particles migrate to smoothly change the gradation display from the second gradation to the fourth gradation. As a result, in the second step, the display change is such that the pixel whose gradation display is changed is displayed at the same time regardless of the first or second gradation, and the previous display gradually disappears and the next display gradually appears. In other words, the display can be changed smoothly, and the display quality can be improved. In addition, high-precision electric field control like gray scale display formed from a plurality of gradations can be performed, and display quality can be improved.

In addition, the driving method of the electrophoretic display device of the present invention includes an electrophoretic element including electrophoretic particles sandwiched between a pair of substrates, and includes a display unit including a plurality of pixels. From a pixel electrode formed for each pixel, a counter electrode facing the plurality of pixel electrodes via the electrophoretic element, and a first control line and a second control line connected to each of the pixels A first set of control lines, a second set of control lines consisting of a third control line and a fourth control line, and a first set of image signal data stored for each pixel. Any one of a memory circuit, a data line for supplying image signal data, and a first pixel switching element that connects the first memory circuit, and a control line in the pixel electrode and the first set of control lines A first switch circuit for connecting the Any one of a second memory circuit that stores the data, a second pixel switching element that connects the data line and the second memory circuit, and a control line in the pixel electrode and the second set of control lines And a second switch circuit for connecting the image signal data to the first memory circuit via the first pixel switching element. A first step of inputting and inputting image signal data to the second memory circuit via the second pixel switching element, and the first switch circuit based on an output from the first memory circuit And controlling the second switch circuit based on an output from the second memory circuit, and in the first step, the second control line and the image The first memory that controls the pixels that do not change the gradation display of the data of the first set of image signals, in which the electrodes are connected and the fourth control line and the pixel electrode are connected. A second set of image signals that are input to the circuit and the second memory circuit, the second control line and the pixel electrode are connected, and the third control line and the pixel electrode are connected. Is input to the first memory circuit and the second memory circuit that control the pixel that changes the gradation display from the first gradation display to the second gradation display, and the first memory circuit The data of the third set of image signals, in which the control line and the pixel electrode are connected, and the fourth control line and the pixel electrode are connected, is transferred from the second gradation display to the first floor. The first memory circuit and the second memory that control the pixels that change the gradation display to the gradation display. In the second step, the second wave is input to the first control line while inputting a rectangular wave that repeats the first potential and the second potential to the counter electrode for one period or more in the second step. And the second control line is set to a high impedance state in which the second control line and the fourth control line are electrically disconnected from each other. Features .

  In the first step, in the pixel in which the data of the first set of image signals is input to the first memory circuit and the second memory circuit, the electrophoretic particles do not migrate in the second step, The gradation display (the gradation display of the first gradation or the second gradation) is not changed. Further, in the first step, the pixels in which the data of the second set of image signals are input to the first memory circuit and the second memory circuit are the positively charged electrophoretic particles and Both negatively charged electrophoretic particles migrate and change the gradation display smoothly from the first gradation to the second gradation. Further, in the first step, the pixels in which the data of the third set of image signals are input to the first memory circuit and the second memory circuit are the positively charged electrophoretic particles and Both negatively charged electrophoretic particles migrate and change the gradation display smoothly from the second gradation to the first gradation. As a result, in the second step, the display change is such that the pixel whose gradation display is changed is displayed at the same time regardless of the first or second gradation, and the previous display gradually disappears and the next display gradually appears. In other words, the display can be changed smoothly, and the display quality can be improved. Further, by changing the period of the second step, it is possible to keep the pixels for changing the gradation display in the intermediate gradation display, so that the high accuracy like the gray scale display formed from a plurality of gradations can be achieved. Display quality can be improved by performing appropriate electric field control.

  The electrophoretic display device of the present invention includes a signal supply unit that supplies a potential to the first control line, the second control line, the third control line, the fourth control line, and the counter electrode. Selection signal supply means for supplying a selection signal for defining an on-timing of the switching element to the first pixel switching element and the second pixel switching element provided for each pixel, and through the first pixel switching element Data supply means for supplying image signal data to the first memory circuit and to the second memory circuit via the second pixel switching element, respectively. A driving method is executed. Accordingly, it is possible to provide an electrophoretic display device in which power consumption for data transfer is reduced and display quality is improved.

  An electronic apparatus according to the present invention includes the electrophoretic display device described above. Thereby, it is possible to provide an electronic device with reduced power consumption for data transfer and improved display quality.

1 is a configuration diagram of an electrophoretic display device 100 according to an embodiment of the present invention. FIG. 2 is a circuit configuration diagram of a pixel 40 in the electrophoretic display device 100 shown in FIG. 1. FIG. 2 is a partial cross-sectional view of a display unit 5 in the electrophoretic display device 100 shown in FIG. It is a schematic cross section of the microcapsule 20 shown in FIG. FIG. 4 is an operation explanatory diagram of the electrophoretic element 32 shown in FIGS. 2 and 3. 4 is an explanatory diagram used for describing a first driving method of the electrophoretic display device 100. FIG. It is a timing chart used for description of the 1st drive method. It is the figure which showed the connection state of the pixel 40 corresponding to previous image display period S101. It is the figure which showed the connection state of the pixel 40 corresponding to image display period ST32a. It is the figure which showed the connection state of the pixel 40 corresponding to image display period ST32b. It is the figure which showed the connection state of the pixel 40 corresponding to next image display period S103. 10 is an explanatory diagram used for describing a second driving method of the electrophoretic display device 100. FIG. It is a timing chart used for description of the 2nd drive method. It is the figure which showed the connection state of the pixel 40 corresponding to previous image display period S101. It is the figure which showed the connection state of the pixel 40 corresponding to image display period ST32a. It is the figure which showed the connection state of the pixel 40 corresponding to image display period ST32b. It is a timing chart used for description of the 3rd drive method. It is the figure which showed the connection state of the pixel 40 corresponding to image display period ST32a. It is a figure which shows the wristwatch which is an example of an electronic device. It is a figure which shows the electronic paper which is an example of an electronic device. It is a figure which shows the electronic notebook which is an example of an electronic device.

DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, an embodiment of an electrophoretic display device driving method, an electrophoretic display device, and an electronic apparatus according to the invention will be described with reference to the drawings.
FIG. 1 is a schematic configuration diagram of an electrophoretic display device 100 according to the present embodiment.
The electrophoretic display device 100 includes a display unit 5 in which a plurality of pixels 40 are arranged in a matrix. Around the display unit 5, a scanning line driving circuit 61, a data line driving circuit 62, a controller 63 (control unit), and a common power supply modulation circuit 64 are arranged. The scanning line driving circuit 61, the data line driving circuit 62, and the common power supply modulation circuit 64 are each connected to the controller 63. The controller 63 comprehensively controls the above circuit based on image data and a synchronization signal supplied from the host device.

In the display unit 5, a plurality of scanning lines 66 extending from the scanning line driving circuit 61 and a plurality of data lines 68 extending from the data line driving circuit 62 are formed, and at the intersections of the data lines 68 and the scanning lines 66. Correspondingly, a pixel 40 is provided.
The scanning line driving circuit 61 is connected to each pixel 40 via two consecutive scanning lines 66 among m scanning lines 66 (Y1, Y2,..., Ym), and is controlled by the controller 63. Originally, the scanning lines 66 from the first line to the m-th line are sequentially selected. The scanning line driving circuit 61 supplies a selection signal that defines the ON timing to the first selection transistor ST1 (see FIG. 2) provided in the pixel 40 via the selected odd-numbered scanning line 66. Further, the scanning line driving circuit 61 supplies a selection signal that defines the on-timing to the second selection transistor ST2 (see FIG. 2) provided in the pixel 40 via the selected even-numbered scanning line 66.

The data line driving circuit 62 is connected to each pixel 40 via n data lines 68 (X1, X2,..., Xn). The data line driving circuit 62 supplies image signal data defining 2-bit pixel data corresponding to each of the pixels 40 to the pixels 40 via the data lines 68 under the control of the controller 63.
In the present embodiment, a low level (L) image signal is supplied to the pixel 40 when the pixel data “0” is defined, and a high level (H) image is defined when the pixel data “1” is defined. It is assumed that a signal is supplied to the pixel 40.

  The display unit 5 also includes seven global wirings (low potential power line 49, high potential power line 50, common electrode wiring 55, first control line 91, second control line 92 extending from the common power modulation circuit 64. , A third control line 93 and a fourth control line 94) are provided, and each wiring is connected to the pixel 40. Under the control of the controller 63, the common power supply modulation circuit 64 generates various signals to be supplied to each of the above wirings, and electrically connects and disconnects these wirings (high impedance).

FIG. 2 is a circuit configuration diagram of the pixel 40.
The pixel 40 includes a first selection transistor ST1 (first pixel switching element), a first latch circuit LAT1 (first memory circuit), a first switch circuit SC1, and a second selection transistor ST2. (Second pixel switching element), a second latch circuit LAT2 (second memory circuit), a second switch circuit SC2, an electrophoretic element 32, a pixel electrode 35, and a common electrode 37 are provided. It has been. The electrophoretic element 32 is sandwiched between the pixel electrode 35 and the common electrode 37.
The pixel 40 has an SRAM (Static Random Access Memory) system configuration in which image signal data is held as a potential by the first latch circuit LAT1 and the second latch circuit LAT2.

The first selection transistor ST1 is a switching element formed of an N-MOS (Negative Metal Oxide Semiconductor) transistor. The gate terminal of the first selection transistor ST1 is connected to the scanning line 66 to which the gate potential (Gate N) is supplied, the source terminal is connected to the data line 68, and the drain terminal is the data input terminal of the first latch circuit LAT1. Connected to N11.
The data input terminal N11 and the data output terminal N12 of the first latch circuit LAT1 are connected to the first switch circuit SC1. Further, the first switch circuit SC <b> 1 is connected to the pixel electrode 35, the first control line 91, and the second control line 92.

The second selection transistor ST2 is a switching element composed of an N-MOS transistor. The gate terminal of the second selection transistor ST2 is connected to a scanning line 66 to which a gate potential (Gate N + 1) different from the gate terminal of the first selection transistor ST1 is supplied, and the source terminal is connected to the first selection transistor ST1. Connected to the same data line 68, the drain terminal is connected to the data input terminal N21 of the second latch circuit LAT2.
The data input terminal N21 and the data output terminal N22 of the second latch circuit LAT2 are connected to the second switch circuit SC2. The second switch circuit SC2 is connected to the pixel electrode 35, the third control line 93, and the fourth control line 94.

  The first latch circuit LAT1 includes a transfer inverter INV1 and a feedback inverter INV2. Both the transfer inverter INV1 and the feedback inverter INV2 are C-MOS inverters. The transfer inverter INV1 and the feedback inverter INV2 have a loop structure in which the other output terminal is connected to each other's input terminal, and each inverter has a high potential connected via a high potential power supply terminal PH1. A high potential power supply voltage is supplied from the power supply line 50, and a low potential power supply voltage is supplied from the low potential power supply line 49 connected via the low potential power supply terminal PL1.

  The transfer inverter INV1 includes a P-MOS transistor PM1 (Positive Metal Oxide Semiconductor) whose drain terminal is connected to the data output terminal N12, and an N-MOS transistor NM1. The source terminal of the P-MOS transistor PM1 is connected to the high potential power supply terminal PH1, and the source terminal of the N-MOS transistor NM1 is connected to the low potential power supply terminal PL1. The gate terminals of the P-MOS transistor PM1 and the N-MOS transistor NM1 (the input terminal of the transfer inverter INV1) are connected to the data input terminal N11 (the output terminal of the feedback inverter INV2).

  The feedback inverter INV2 includes a P-MOS transistor PM2 and an N-MOS transistor NM2 whose drain terminals are connected to the data input terminal N11. The gate terminals of the P-MOS transistor PM2 and the N-MOS transistor NM2 (input terminal of the feedback inverter INV2) are connected to the data output terminal N12 (output terminal of the transfer inverter INV1).

In the first latch circuit LAT1 configured as described above, when image control data (pixel data “1”) having a pixel signal at a high level (H) is stored, the data output terminal N12 of the first latch circuit LAT1 has a low level. The signal (L) is output.
On the other hand, when image control data (pixel data “0”) having a low pixel signal is stored in the first latch circuit LAT1, a high level (H) signal is output from the data output terminal N12.

The first switch circuit SC1 includes a first transmission gate TG1 and a second transmission gate TG2.
The first transmission gate TG1 includes a P-MOS transistor PM3 and an N-MOS transistor NM3.
The source terminals (input terminals of the first transmission gate TG1) of the P-MOS transistor PM3 and the N-MOS transistor NM3 are connected to the first control line 91, and the drain terminals of the P-MOS transistor PM3 and the N-MOS transistor NM3. (Output terminal of the first transmission gate TG1) is connected to the pixel electrode 35.
The gate terminal of the P-MOS transistor PM3 is connected to the data input terminal N11 of the first latch circuit LAT1, and the gate terminal of the N-MOS transistor NM3 is connected to the data output terminal N12 of the first latch circuit LAT1. Yes.

The second transmission gate TG2 includes a P-MOS transistor PM4 and an N-MOS transistor NM4.
The source terminals of the P-MOS transistor PM4 and the N-MOS transistor NM4 (the input terminal of the second transmission gate TG2) are connected to the second control line 92, and the drain terminals of the P-MOS transistor PM4 and the N-MOS transistor NM4. (Output terminal of the second transmission gate TG2) is connected to the pixel electrode 35 together with the output terminal of the first transmission gate TG1.
The gate terminal of the P-MOS transistor PM4 is connected to the data output terminal N12 of the first latch circuit LAT1, and the gate terminal of the N-MOS transistor NM4 is connected to the data input terminal N11 of the first latch circuit LAT1. Yes.

  The second latch circuit LAT2 is a latch circuit having a configuration similar to that of the first latch circuit LAT1, and includes a transfer inverter INV3 including a P-MOS transistor PM5 and an N-MOS transistor NM5, and a P-MOS transistor. A feedback inverter INV4 including PM6 and an N-MOS transistor NM6 is included. The second latch circuit LAT2 also outputs a low level (L) signal from the data output terminal N22 of the second latch circuit LAT2 when image control data having a pixel signal high level (H) is stored. On the other hand, the second latch circuit LAT2 outputs a high level (H) signal from the data output terminal N22 when image control data having a pixel signal of a low level (L) is stored.

The second switch circuit SC2 includes a third transmission gate TG3 and a fourth transmission gate TG4.
The third transmission gate TG3 includes a P-MOS transistor PM7 and an N-MOS transistor NM7.
The source terminals of the P-MOS transistor PM7 and the N-MOS transistor NM7 (the input terminal of the third transmission gate TG3) are connected to the third control line 93, and the drain terminals of the P-MOS transistor PM7 and the N-MOS transistor NM7. (Output terminal of the third transmission gate TG3) is connected to the pixel electrode 35.
The gate terminal of the P-MOS transistor PM7 is connected to the data input terminal N21 of the second latch circuit LAT2, and the gate terminal of the N-MOS transistor NM7 is connected to the data output terminal N22 of the second latch circuit LAT2. Yes.

The fourth transmission gate TG4 includes a P-MOS transistor PM8 and an N-MOS transistor NM8.
The source terminals of the P-MOS transistor PM8 and the N-MOS transistor NM8 (the input terminal of the fourth transmission gate TG4) are connected to the fourth control line 94, and the drain terminals of the P-MOS transistor PM8 and the N-MOS transistor NM8. (Output terminal of the fourth transmission gate TG4) is connected to the pixel electrode 35 together with the output terminal of the third transmission gate TG3.
The gate terminal of the P-MOS transistor PM8 is connected to the data output terminal N22 of the second latch circuit LAT2, and the gate terminal of the N-MOS transistor NM8 is connected to the data input terminal N21 of the second latch circuit LAT2. Yes.

  In the pixel 40 described above, the first switch circuit SC1 is controlled by the output signal (holding potential) of the first latch circuit LAT1, and the second switch is controlled by the output signal (holding potential) of the second latch circuit LAT2. The circuit SC2 is controlled. Then, by the switching operation by the first switch circuit SC1 and the second switch circuit SC2, one of the control lines of the first set of control lines including the first control line 91 and the second control line 92; Two control lines, one of the control lines of the second set of control lines 93 and the fourth control line 94, are connected to the pixel electrode 35. Then, one of the two control lines to be connected is set to a high impedance state (Hi-Z state), and a potential is supplied to the other, whereby the pixel electrode 35 is supplied with these first control lines 91. Any one of the potentials S1 to S4 of the fourth control line 94 is input.

For example, first, when the data (pixel data “0”) of the low level (L) image signal is stored in the first latch circuit LAT1, and the high level (H) signal is output from the data output terminal N12, the first latch circuit LAT1 One transmission gate TG1 is turned on, and the first control line 91 and the pixel electrode 35 are electrically connected. Next, when the high-level (H) image signal data (pixel data “1”) is stored in the second latch circuit LAT2, and a low-level (L) signal is output from the data output terminal N22, the fourth latch circuit LAT2 The transmission gate TG4 is turned on, and the fourth control line 94 and the pixel electrode 35 are electrically connected. For example, if the fourth control line 94 is maintained in the Hi-Z state and the potential S1 is supplied to the first control line 91, the potential S1 input to the pixel electrode 35 and the common electrode wiring 55 are used. The electrophoretic element 32 is driven based on the potential difference from the potential Vcom input to the common electrode 37, so that the pixel 40 receives the image signal input to the first latch circuit LAT1 and the second latch circuit LAT2. Are displayed with gradation corresponding to the data (2 bits).
Hereinafter, the image data D1 input to the first latch circuit LAT1 and the image data D2 input to the second latch circuit LAT2 are stored in the first latch circuit LAT1 and the second latch circuit LAT2 of the pixel 40. The input image signal data (2 bits) is, as data (D1, D2), (upper, lower) = (D1, D2), and the image data input to the first latch circuit LAT1 is higher It shall be described on the side.

  Next, FIG. 3 is a partial cross-sectional view of the electrophoretic display device 100 in the display unit 5. The electrophoretic display device 100 has a configuration in which an electrophoretic element 32 formed by arranging a plurality of microcapsules 20 in a single layer is sandwiched between an element substrate 30 and a counter substrate 31. In the display unit 5, a plurality of pixel electrodes 35 are arranged on the electrophoretic element 32 side of the element substrate 30, and the electrophoretic elements 32 are bonded to the pixel electrodes 35 through an adhesive layer 33.

  The element substrate 30 is a substrate made of glass, plastic, or the like and is not required to be transparent because it is disposed on the side opposite to the image display surface. The pixel electrode 35 is an electrode in which nickel plating and gold plating are laminated in this order on a Cu foil, or an electrode formed of Al, ITO (indium tin oxide), or the like. Although not shown, between the pixel electrode 35 and the element substrate 30, the scanning line 66, the data line 68, the first selection transistor ST1, and the second selection transistor ST2 shown in FIGS. The first latch circuit LAT1, the second latch circuit LAT2, the first switch circuit SC1, the second switch circuit SC2, and the like are formed.

  On the other hand, the counter substrate 31 is a substrate made of glass, plastic, or the like, and is a transparent substrate because it is disposed on the image display side. A planar common electrode (opposite electrode) 37 facing the plurality of pixel electrodes 35 is formed on the counter substrate 31 on the side of the electrophoretic element 32, and the electrophoretic element 32 is provided on the common electrode 37. The common electrode 37 is a transparent electrode formed of MgAg, ITO, IZO (indium / zinc oxide), or the like.

  In general, the electrophoretic element 32 is formed in advance on the counter substrate 31 side, and is handled as an electrophoretic sheet including the adhesive layer 33. In the manufacturing process, the electrophoretic sheet is handled in a state where a protective release sheet is attached to the surface of the adhesive layer 33. And the display part 5 is formed by affixing the said electrophoretic sheet which peeled off the peeling sheet with respect to the element board | substrate 30 (The pixel electrode 35, various circuits, etc.) which were manufactured separately. For this reason, the adhesive layer 33 exists only on the pixel electrode 35 side of the electrophoretic element 32. The display unit 5 is formed. For this reason, the adhesive layer 33 exists only on the pixel electrode 35 side of the electrophoretic element 32.

  FIG. 4 is a schematic cross-sectional view of the microcapsule 20. The microcapsule 20 has a particle size of about 50 μm, for example, and has a dispersion medium 21, a plurality of white particles 27 (for example, negatively charged electrophoretic particles), and a plurality of black particles 26 (for example, positively). A spherical body encapsulating charged electrophoretic particles). As shown in FIG. 3, the microcapsule 20 is sandwiched between the common electrode 37 and the pixel electrode 35, and one or more microcapsules 20 are arranged in one pixel 40.

The outer shell portion (wall film) of the microcapsule 20 is formed using a translucent polymer resin such as an acrylic resin such as polymethyl methacrylate or polyethyl methacrylate, a urea resin, or gum arabic.
The dispersion medium 21 is a liquid that disperses the white particles 27 and the black particles 26 in the microcapsules 20. Examples of the dispersion medium 21 include water, alcohol solvents (methanol, ethanol, isopropanol, butanol, octanol, methyl cellosolve, etc.), esters (ethyl acetate, butyl acetate, etc.), ketones (acetone, methyl ethyl ketone, methyl isobutyl ketone, etc.). ), Aliphatic hydrocarbons (pentane, hexane, octane, etc.), alicyclic hydrocarbons (cyclohexane, methylcyclohexane, etc.), aromatic hydrocarbons (benzene, toluene, benzenes having a long-chain alkyl group ( Xylene, hexylbenzene, hebutylbenzene, octylbenzene, nonylbenzene, decylbenzene, undecylbenzene, dodecylbenzene, tridecylbenzene, tetradecylbenzene)), halogenated hydrocarbons (methylene chloride, chloroform, tetrachloride) Element, and 1,2-dichloroethane), can be exemplified a carboxylate, it may be other oils. These substances can be used alone or as a mixture, and a surfactant or the like may be further blended.

The white particles 27 are particles (polymer or colloid) made of a white pigment such as titanium dioxide, zinc white, and antimony trioxide, and are used, for example, by being negatively charged. The black particles 26 are particles (polymer or colloid) made of a black pigment such as aniline black or carbon black, and are used by being charged positively, for example.
These pigments include electrolytes, surfactants, metal soaps, resins, rubbers, oils, varnishes, compound charge control agents, titanium-based coupling agents, aluminum-based coupling agents, silanes as necessary. A dispersant such as a system coupling agent, a lubricant, a stabilizer, and the like can be added.
Further, instead of the black particles 26 and the white particles 27, for example, pigments such as red, green, and blue may be used. According to this configuration, color display can be performed by displaying red, green, blue, or the like on the display unit 5.

FIG. 5 is an operation explanatory diagram of the electrophoretic element. FIG. 5A shows the case where the pixel 40 displays white, and FIG. 5B shows the case where the pixel 40 displays black.
In the electrophoretic display device 100, a first latch circuit LAT1 that stores data of an image signal input via the first selection transistor ST1 and a control signal input via the second selection transistor ST2 are stored. The first latch circuit LAT2 controls the first switch circuit SC1 and the second switch circuit SC2, respectively, and the first control line 91 and the second control line 92 are controlled. The two control lines and the pixel electrode 35 are electrically connected to any one of the control lines and one of the control lines of the second set of control lines including the third control line 93 and the fourth control line 94. Connect to. Then, one of the two control lines is maintained in a high impedance state (Hi-Z state) and a potential is supplied to the other, whereby the first control lines 91 to 91 are provided to the pixel electrode 35. One of the potentials S1 to S4 of the fourth control line 94 is input. As a result, a predetermined potential is input to the pixel electrode 35, and the pixel 40 is displayed in black or white based on the potential difference between the pixel electrode 35 and the common electrode 37, as shown in FIG.

5A, the common electrode 37 is held at a relatively high potential and the pixel electrode 35 is held at a relatively low potential. As a result, the negatively charged white particles 27 are attracted to the common electrode 37, while the positively charged black particles 26 are attracted to the pixel electrode 35. As a result, when this pixel is viewed from the common electrode 37 side which is the display surface side, white (W) is recognized.
In the case of black display shown in FIG. 5B, the common electrode 37 is held at a relatively low potential, and the pixel electrode 35 is held at a relatively high potential. As a result, the positively charged black particles 26 are attracted to the common electrode 37, while the negatively charged white particles 27 are attracted to the pixel electrode 35. As a result, when this pixel is viewed from the common electrode 37 side, black (B) is recognized.

[First driving method]
Next, a driving method of the electrophoretic display device according to the present embodiment will be described with reference to FIGS.
FIG. 6 is an explanatory diagram used for explaining the first driving method. FIG. 6A is an explanatory diagram showing a display state of the display unit 5. FIG. 6A shows a two-gradation display state in the previous image and the next image of four pixels among the pixels 40 arranged in the display unit 5. Hereinafter, the four pixels are distinguished from the pixel 40A, the pixel 40B, the pixel 40C, and the pixel 40D. FIG. 6B shows image signal data (2 bits) input to the first latch circuit LAT1 and the second latch circuit LAT2 of the pixels 40A to 40D when the next image display is performed. Yes.

FIG. 7 is a timing chart used for explaining the first driving method. In FIG. 7, the previous image display period S101 for displaying the previous image shown in FIG. 6A, the power-off period S102, and the next image display period S103 for displaying the next image shown in FIG. The potentials of the pixel electrodes of the pixels 40A to 40D when the operation is performed and the display is changed from the previous image to the next image in FIG. 6A are shown. Specifically, the potential N11A of the data input terminal N11 of the first latch circuit LAT1 of the pixel 40A shown in FIG. 6A, the potential N21A of the data input terminal N21 of the second latch circuit LAT2, and the pixel electrode 35 are shown. The potential VA is shown. Similarly to the pixel 40A, the pixels 40B to 40D have the potentials N11B to N11D of the data input terminal N11 of the first latch circuit LAT1, the potentials N21B to N21D of the data input terminal N21 of the second latch circuit LAT2, and the pixel electrodes. 35 potentials VB to VD are shown.
FIG. 7 also shows the potential Vdd of the high potential power supply line 50, the potential Vcom of the common electrode 37, the potential S1 of the first control line 91, the potential S2 of the second control line 92, and the potential of the third control line 93. S3 and the potential S4 of the fourth control line 94 are shown. Note that the potential Vss of the low-potential power line 49 is not shown in FIG. 10, but is a low level potential L (0 V).

  8 to 11 are schematic diagrams illustrating connection states of the pixel circuits of the pixels 40A to 40D in each period illustrated in FIG. In each of FIGS. 8 to 11, pixels 40A to 40D and first control lines 91 to fourth control lines 94 are shown, and are based on the first switch circuit SC1 and the second switch circuit SC2 that constitute the pixel circuit. The switching operation is represented. FIG. 8 is a diagram illustrating a connection state of the pixels 40 corresponding to the previous image display period S101, and FIG. 9 is a diagram illustrating a connection state of the pixels 40 corresponding to the image display period ST32a. FIG. 10 is a diagram illustrating a connection state of the pixels 40 corresponding to the image display period ST32b, and FIG. 11 is a diagram illustrating a connection state of the pixels 40 corresponding to the next image display period S103. In FIGS. 8 to 11, in order to make the drawings easy to see, the pixels 40 </ b> A to 40 </ b> D shown in FIG.

In the first driving method of the electrophoretic display device of this embodiment, first, the previous image is displayed on the display unit 5 in the previous image display period S101. In the display unit 5, as shown in FIG. 6A, the pixels 40A and 40B are displayed in black, and the pixels 40C and 40D are displayed in white.
The previous image display period S101 includes an image signal input period ST11 and an image display period ST12.

In the image signal input period ST11, a potential of about 5 V (high level; high level potential H (5 V) in FIG. 7) is supplied from the common power supply modulation circuit 64 to each pixel 40 of FIG. And a potential of about 0 V (indicated as a low level potential L (0 V) in FIG. 7) through the low potential power line 49. The first latch circuit LAT1 and the second latch circuit LAT2 of each pixel are driven.
At this time, the common electrode wiring 55, the first control line 91, the second control line 92, the third control line 93, and the fourth control line 94 shown in FIG. (Hi-Z).

The scanning line driving circuit 61 in FIG. 1 inputs a selection signal to the scanning line Y1. By this selection signal, the first selection transistor ST1 of the pixel 40 connected to the scanning line Y1 is driven, and the first latch circuit LAT1 of the pixel 40 connected to the scanning line Y1 is connected to the data lines X1, X2,. , Xn, respectively.
The data line driving circuit 62 in FIG. 1 supplies image signal data to the first latch circuit LAT1 of the pixel 40 connected to the scanning line Y1 by supplying image signals to the data lines X1, X2,. input.
When the image signal is input, the scanning line driving circuit 61 stops supplying the selection signal to the scanning line Y1, and cancels the selection state of the pixels 40 connected to the scanning line Y1.
Subsequently, the scanning line driving circuit 61 inputs a selection signal to the scanning line Y2. By this selection signal, the second selection transistor ST2 of the pixel 40 connected to the scanning line Y2 is driven, and the second latch circuit LAT2 of the pixel 40 connected to the scanning line Y2 receives the data lines X1, X2,. , Xn, respectively.
The data line driving circuit 62 inputs image signal data to the second latch circuit LAT2 of the pixel 40 connected to the scanning line Y2 by supplying image signals to the data lines X1, X2,.
When the image signal data is input, the scanning line driving circuit 61 stops supplying the selection signal to the scanning line Y2, and cancels the selection state of the pixels 40 connected to the scanning line Y2.
The above operation is sequentially executed up to the pixels 40 connected to the scanning line Ym, and image signal data is input to the first latch circuit LAT1 and the second latch circuit LAT2 of all the pixels 40. Thereby, in the image signal input period ST11, the potential corresponding to the image data is stored in the first latch circuit LAT1 and the second latch circuit LAT2 of the pixel 40 constituting the display unit 5.

In this image signal input period ST11, each of the first latch circuit LAT1 and the second latch circuit LAT2 of each of the pixels 40A to 40D shown in FIG. 6A has 2-bit image data (0, 0). , (0, 1), (1, 0), (1, 1) are stored. Thereby, in the pixel 40A, as shown in FIG. 7, the potential N11A of the data input terminal N11 of the first latch circuit LAT1 of the pixel 40A becomes the low level potential L (0 V), and the data of the second latch circuit LAT2 The potential N21A of the input terminal N21 is also the low level potential L (0 V). Then, as shown in FIG. 8, the first control line 91 and the third control line 93 are connected to the pixel electrode 35. At this time, the common electrode wiring 55, the first control line 91, the second control line 92, the third control line 93, and the fourth control line 94 are electrically disconnected by the common power supply modulation circuit 64. Therefore, the electrophoretic element 32 is not driven yet.
Further, as shown in FIG. 7, in the pixel 40B storing the image data (0, 1), the potential N11B of the data input terminal N11 of the first latch circuit LAT1 becomes the low level potential L (0V), and the second The potential N21B of the data input terminal N21 of the latch circuit LAT2 becomes the high level potential H (5V). The first control line 91 and the fourth control line 94 are connected to the pixel electrode 35.

Further, as shown in FIG. 7, in the pixel 40C storing the image data (1, 0), the potential N11C of the data input terminal N11 of the first latch circuit LAT1 becomes the high level potential H (5V), and the second The potential N21C of the data input terminal N21 of the latch circuit LAT2 becomes the low level potential L (0 V). The second control line 92 and the third control line 93 are connected to the pixel electrode 35.
Further, as shown in FIG. 7, in the pixel 40D storing the image data (1, 1), the potential N11D of the data input terminal N11 of the first latch circuit LAT1 becomes the high level potential H (5V), and the second The potential N21D of the data input terminal N21 of the latch circuit LAT2 is also the high level potential H (5V). The second control line 92 and the fourth control line 94 are connected to the pixel electrode 35.

Next, the process proceeds to the image display period ST12.
In the image display period ST12, the common power supply modulation circuit 64 applies a high level (second potential) potential of approximately 15 V to the high potential power supply line 50 (shown as a high level potential H (15 V) in FIG. 7). Supply. The common power supply modulation circuit 64 supplies a low level potential L (0 V) to the low potential power supply line 49. Therefore, image signal data held at the high level potential H (5 V) in the first latch circuit LAT1 or the second latch circuit LAT2 is held at a higher high level potential H (15 V).
Further, the common power supply modulation circuit 64 sets the potential S1 of the first control line 91 to the high level potential H (15V) and sets the potential S2 of the second control line 92 to the low level potential L (0V). Further, the common power supply modulation circuit 64 maintains the Hi-Z state of the third control line 93 and the fourth control line 94, and the common electrode wiring 55 has a low level potential L (0 V) and a high level potential H (15 V). ) In a predetermined cycle, and a rectangular wave pulse is supplied.

  Thereby, in the pixel 40A and the pixel 40B, the potential of the pixel electrode 35 is the same as the potential S1 of the first control line 91. The potential VA of the pixel electrode 35 and the potential VB of the pixel electrode 35 are both high level potential H (15 V). In the pixels 40 </ b> A and 40 </ b> B, the electrophoretic element 32 is driven by a potential difference generated between each pixel electrode 35 (high level potential H) while the potential Vcom of the common electrode 37 is the low level potential L. Thereby, as shown in FIG. 8, the pixel 40A and the pixel 40B are displayed in black. Note that during the period in which the potential Vcom of the common electrode 37 is the high level potential H, since the potential VA, the potential VB, and the potential Vcom are the same potential, the electrophoretic element 32 is not driven, and the pixels 40A and 40B The display does not change.

  In the pixels 40C and 40D, the potential of the pixel electrode 35 is the same as the potential S2 of the second control line 92. The potential VC of the pixel electrode 35 and the potential VD of the pixel electrode 35 are both low level potential L (0 V). In the pixels 40C and 40D, the electrophoretic element 32 is driven by a potential difference generated between each pixel electrode 35 (low level potential L) while the potential Vcom of the common electrode 37 is the high level potential H. Thereby, as shown in FIG. 8, the pixels 40C and 40D are displayed in white. Note that during the period in which the potential Vcom of the common electrode 37 is at the low level potential L, the electrophoretic element 32 is not driven because the potential VC, the potential VD, and the potential Vcom are the same potential, and the pixels 40C, 40D The display does not change.

Thus, the previous image shown in FIG. 6A is displayed on the display unit 5 in the previous image display period S101.
Then, the process proceeds to the power-off period S102. In the power-off period S102, the first control line 91 and the second control line 92 are both in the Hi-Z state. As described above, the pixel electrodes 35 belonging to the pixels 40A to 40D are connected to the first control line 91 or the second control line 92 via the first switch circuit SC1 and the second switch circuit SC2. Therefore, all the pixel electrodes 35 are set to the Hi-Z state. The common electrode 37 is also set to the Hi-Z state by the common power supply modulation circuit 64.

In the power-off period S102, the high-potential power line 50 and the low-potential power line 49 are also in the Hi-Z state. As a result, the first latch circuit LAT1 and the second latch circuit LAT2 are turned off, and power consumption during a period in which an image is held can be suppressed.
Note that in the power-off period S102, the high-potential power line 50 and the low-potential power line 49 may be in a state of holding predetermined high-level potential and low-level potential. In this case, since the first latch circuit LAT1 and the second latch circuit LAT2 maintain the energized state, the image signal data corresponding to the first image input in the previous image display period S101 can be held.
Further, when the energization state of the first latch circuit LAT1 and the second latch circuit LAT2 is maintained, the power supply voltage of the first latch circuit LAT1 and the second latch circuit LAT2 is such that the retained data is not lost. You may descend to For example, when the electrophoretic element 32 is driven in the previous image display period S101 described above, the power supply voltage of the first latch circuit LAT1 and the second latch circuit LAT2 needs to be about 10 to 15 V, but the power is off. In the period S102, the power supply voltage can be reduced to about 2 to 5V. Thereby, power consumption of the pixel circuit in the power-off period S102 can be suppressed.

Next, the process proceeds to the next image display period S103 for displaying the next image shown in FIG.
As shown in FIG. 7, the next image display period S103 includes an image signal input period ST31 (first step), an image display period ST32a (first display step in the second step), and an image display period ST32b (second step). 2nd display step in the above step).
The image data written in the image signal input period ST31 of the next image display period S103 is data shown in FIG. 6B, and the pixel 40A maintains the black display and the pixel 40B changes the display from the black display to the white display. In this case, the pixel 40C changes the display from white display to black display, and the pixel 40D maintains the white display. That is, when the display is changed from the previous image to the next image shown in FIG. 6A, the gradation (display state) of the pixels 40B and 40C changes, but the display states of the pixels 40A and 40D do not change.

In the image signal input period ST31 (first step), as in the above-described image signal input period ST11, the common power supply modulation circuit 64 supplies each pixel 40 to the high level potential H (through the high potential power supply line 50). 5V) is supplied with a low level potential L (0 V) via a low potential power line 49. As a result, the first latch circuit LAT1 and the second latch circuit LAT2 of each pixel are driven.
At this time, the common electrode wiring 55, the first control line 91, the second control line 92, the third control line 93, and the fourth control line 94 are electrically connected to the Hi-Z by the common power supply modulation circuit 64. It is in a state.

  In the image signal input period ST31, as in the above-described image signal input period ST11, the scanning line driving circuit 61 and the data line driving circuit 62 are provided with the first latch circuit LAT1 and the second latch circuit LAT2 of each pixel 40. To store the image data. In each of the first latch circuit LAT1 and the second latch circuit LAT2 of the pixels 40A to 40D shown in FIG. 6A, 2-bit image data (1, 1), ( 1, 0), (0, 1), (1, 1) are stored.

Thereby, in the pixel 40A, as shown in FIG. 7, the potential N11A of the data input terminal N11 of the first latch circuit LAT1 of the pixel 40A becomes the high level potential H (5V), and the data of the second latch circuit LAT2 The potential N21A of the input terminal N21 is also the high level potential H (5V). In the pixel 40 </ b> A, the second control line 92 and the fourth control line 94 are connected to the pixel electrode 35. At this time, the common electrode wiring 55, the first control line 91, the second control line 92, the third control line 93, and the fourth control line 94 are set in the Hi-Z state by the common power supply modulation circuit 64. Therefore, the electrophoretic element 32 is not driven yet.
As shown in FIG. 7, in the pixel 40B storing the image data (1, 0), the potential N11B of the data input terminal N11 of the first latch circuit LAT1 becomes the high level potential H (5V), and the second The potential N21B of the data input terminal N21 of the latch circuit LAT2 becomes the low level potential L (0 V). In the pixel 40 </ b> B, the second control line 92 and the third control line 93 are connected to the pixel electrode 35.

Further, as shown in FIG. 7, in the pixel 40C storing the image data (0, 1), the potential N11C of the data input terminal N11 of the first latch circuit LAT1 becomes the low level potential L (0V), and the second The potential N21C of the data input terminal N21 of the latch circuit LAT2 becomes the high level potential H (5V). In the pixel 40 </ b> C, the first control line 91 and the fourth control line 94 are connected to the pixel electrode 35.
Further, as shown in FIG. 7, in the pixel 40D storing the image data (1, 1), as in the pixel 40A, the potential N11D of the data input terminal N11 of the first latch circuit LAT1 is the high level potential H (5V). ), And the potential N21D of the data input terminal N21 of the second latch circuit LAT2 also becomes the high level potential H (5 V). In the pixel 40 </ b> D, the second control line 92 and the fourth control line 94 are connected to the pixel electrode 35.

Next, the process proceeds to the image display period ST32a (first display step in the second step).
In the image display period ST32a, the common power supply modulation circuit 64 supplies a high level potential H (15V) to the high potential power supply line 50 and supplies a low level potential L (0V) to the low potential power supply line 49. Therefore, image signal data held at the high level potential H (5 V) in the first latch circuit LAT1 or the second latch circuit LAT2 is held at a higher high level potential H (15 V).
The common power supply modulation circuit 64 sets the potential S1 of the first control line 91 to the high level potential H (15 V) in the image display period ST32a. Further, the common power supply modulation circuit 64 supplies the second control line 92 and the common electrode wiring 55 with a rectangular wave pulse that repeats the low level potential L (0 V) and the high level potential H (15 V) at a predetermined cycle. . Further, the common power supply modulation circuit 64 maintains the Hi-Z state of the third control line 93 and the fourth control line 94.

  As a result, as shown in FIG. 9, in the pixel 40A, the pixel 40B, and the pixel 40D, the potential of the pixel electrode 35 is the same as the potential S2 of the second control line 92. The potential VA of the pixel electrode 35, the potential VB of the pixel electrode 35, and the potential VD of the pixel electrode 35 are all the same as the potential Vcom of the common electrode 37. Therefore, in the pixel 40A, the pixel 40B, and the pixel 40D, since no potential difference is generated between the common electrode 37 and the pixel electrode 35, the electrophoretic elements (black particles 26 and white particles 27) in the electrophoretic element 32 do not move. Thereby, as shown in FIG. 9, the black display of the pixel 40A and the pixel 40B is maintained, and the white display of the pixel 40D is maintained.

  On the other hand, in the pixel 40C, the potential of the pixel electrode 35 is the same as the potential S1 of the first control line 91. The potential VD of the pixel electrode 35 becomes a high level potential H (15 V). In the pixel 40 </ b> D, the electrophoretic element 32 is driven by a potential difference generated between the common electrode 37 and the pixel electrode 35 (high level potential H) while the potential Vcom of the common electrode 37 is at the low level potential L. As a result, as shown in FIG. 9, the black particles 26 migrate from the pixel electrode 35 toward the common electrode 37, and the white particles 27 migrate from the common electrode 37 toward the pixel electrode 35. Note that, during the period in which the potential Vcom of the common electrode 37 is the high level potential H, the potential VC and the potential Vcom are the same potential, so the electrophoretic elements (the black particles 26 and the white particles 27) in the electrophoretic element 32 are Do not run. Here, depending on the length of the image display period ST32a, the white density of the pixel 40C changes toward a higher density. For example, as the period of the image display period ST32a is longer, the number of black particles 26 that move to the common electrode 37 side increases (conversely, the white particles 27 that move to the pixel electrode 35 side also increase), and the white density of the pixel 40C. Changes toward higher concentrations.

  Thus, in the image display period ST32a, the gradation display of the pixel 40A, the pixel 40B, and the pixel 40D is not changed, and the gradation display of the previous image (gradation display in the previous image display period S101) is maintained. The display state of the pixel 40C gradually changes from white (second gradation) to black (first gradation).

Next, the process proceeds to the image display period ST32b (second display step in the second step).
In the image display period ST32b, the common power supply modulation circuit 64 maintains the potential states of the high potential power supply line 50 and the low potential power supply line 49 in the image display period ST32a. Therefore, the image signal data held in the first latch circuit LAT1 or the second latch circuit LAT2 is held at the potential in the image display period ST32a.
In the image display period ST32b, the common power supply modulation circuit 64 sets the first control line 91 and the second control line 92 to the Hi-Z state, and sets the potential S3 of the third control line 93 to the low level potential L ( 0V). Further, the common power supply modulation circuit 64 supplies the fourth control line 94 and the common electrode wiring 55 with a rectangular wave pulse that repeats the low level potential L (0 V) and the high level potential H (15 V) at a predetermined cycle. .

  Thereby, as shown in FIG. 10, in the pixel 40A, the pixel 40C, and the pixel 40D, the potential of the pixel electrode 35 is the same as the potential S4 of the fourth control line 94. The potential VA of the pixel electrode 35, the potential VC of the pixel electrode 35, and the potential VD of the pixel electrode 35 are all the same potential as the potential Vcom of the common electrode 37. Therefore, in the pixel 40A, the pixel 40C, and the pixel 40D, since no potential difference is generated between the common electrode 37 and the pixel electrode 35, the electrophoretic elements (black particles 26 and white particles 27) in the electrophoretic element 32 do not move. Thereby, as shown in FIG. 10, the black display of the pixel 40A is maintained, and the white display of the pixel 40D is maintained. In the pixel 40C, display of the image display period ST32a is maintained.

  On the other hand, in the pixel 40B, the potential of the pixel electrode 35 is the same as the potential S3 of the third control line 93. Then, the potential VB of the pixel electrode 35 becomes the low level potential L (0 V). In the pixel 40B, during the period in which the potential Vcom of the common electrode 37 is the high level potential H, the electrophoretic element 32 is driven by a potential difference generated between the pixel electrode 35 (low level potential L). Thus, as shown in FIG. 10, the white particles 27 migrate from the pixel electrode 35 toward the common electrode 37, and the black particles 26 migrate from the common electrode 37 toward the pixel electrode 35. Note that during the period in which the potential Vcom of the common electrode 37 is the low level potential L, the potential VB and the potential Vcom are the same potential, and thus the electrophoretic elements (black particles 26 and white particles 27) in the electrophoretic element 32 are Do not run. Here, depending on the length of the image display period ST32b, the black density of the pixel 40B changes toward a lower density. For example, as the period of the image display period ST32b is longer, the number of white particles 27 moving to the common electrode 37 side increases (in contrast, the black particles 26 moving to the pixel electrode 35 side also increase), and the black density of the pixel 40C. Changes towards a thinner concentration.

  Thus, in the image display period ST32b, the gradation display of the pixel 40A and the pixel 40D is not changed, and the gradation display of the previous image (gradation display in the previous image display period S101) is maintained. Further, the display state of the pixel 40C is not changed, and the display state in the image display period ST32a is maintained. The display state of the pixel 40B gradually changes from black (first gradation) to white (second gradation).

By repeating the operation of shifting to the image display period ST32a described above following the image display period ST32b and further shifting from the image display period ST32a to the image display period ST32b, the display of the pixels 40A to 40D is as follows. Change. In the image signal input period ST31, the gradation display of the pixel 40A and the pixel 40D in which the first set of data (1, 1) is input to the latch circuit is not changed, and the gradation display of the previous image is performed in the next image display period S103. (Gradation display in the previous image display period S101) is maintained. The display state of the pixel 40B in which the second set of data (1, 0) is input to the latch circuit in the image signal input period ST31 is changed from black (first gradation) to white (second gradation). It changes gradually and is changed to white in the next image display period S103. The display state of the pixel 40C in which the third set of data (0, 1) is input to the latch circuit in the image signal input period ST31 is changed from white (second gradation) to black (first gradation). It changes gradually and is changed to black in the next image display period S103.
FIG. 11 shows a display state of the pixels 40A to 40D at the final time of the next image display period S103 after the image display period ST32a and the image display period ST32b are repeated a plurality of times. 11 shows the connection state of the image display period ST32b corresponding to FIG. 7, the final period of the next image display period S103 does not necessarily end with the image display period ST32b, and the image display period ST32a is the final period. Needless to say, it may be.

  As described above, the pixel (pixel 40B) that changes the gradation display from black (first gradation), the pixel (pixel 40A) that does not change the gradation display, and the gradation from white (second gradation). Data transfer of the image signal to the pixel (pixel 40C) whose display is changed and the pixel (pixel 40D) whose gradation display is not changed can be performed once in the image signal input period ST31, thereby reducing power consumption for data transfer. be able to. In addition, in the data display period (image display period ST32a and image display period ST32b), a pixel (pixel 40B) that changes the gradation display from black (first gradation) display to white (second gradation) display. In the image display period ST32a, the black particles 26 and the white particles 27 do not migrate, and in the image display period ST32b, the black particles 26 and the white particles 27 migrate. On the other hand, the pixel (pixel 40C) that changes the gradation display from the white (second gradation) display to the black (first gradation) display has the black particles 26 and the white particles 27 in the image display period ST32a. In the image display period ST32b, the black particles 26 and the white particles 27 do not migrate. By alternately repeating the image display period ST32a and the image display period ST32b, the black particles 26 and the white particles 27 in the electrophoretic elements 32 of the pixels 40B and 40D whose gradation display is changed are gradually shared from the pixel electrode 35. It can be migrated to the electrode 37 or from the common electrode 37 to the pixel electrode 35. As a result, the image display on the display unit 5 can be changed so that the previous display gradually disappears and the next display gradually appears, that is, the display can be changed smoothly, thereby improving the display quality. it can.

[Second Driving Method]
Next, a second driving method of the electrophoretic display device according to this embodiment will be described with reference to FIGS.
FIG. 12 is an explanatory diagram used for explaining the first driving method. FIG. 12A is an explanatory diagram illustrating a display state of the display unit 5. FIG. 12A shows a display state of four gradations in the previous image and the next image of four pixels among the pixels 40 arranged in the display unit 5. Hereinafter, the four pixels are distinguished from the pixel 40A, the pixel 40B, the pixel 40C, and the pixel 40D. FIG. 12B shows image signal data (2 bits) input to the first latch circuit LAT1 and the second latch circuit LAT2 of the pixels 40A to 40D when the next image display is performed. Yes.
In the description of the second driving method, as shown in FIG. 12A, the pixels 40A and 40B that are in white display (second gradation) in the previous image display period S101 are replaced with the image in the next image display period S103. The display is changed to black display (first gradation) in the display period ST32a (first display step of the second step). Further, the pixel 40C and the pixel 40D that are in black display (first gradation) in the previous image display period S101 are white in the image display period ST32a (first display step of the second step) in the next image display period S103. The display is changed to display (second gradation). In the image display period ST32b (second display step of the second step) of the next image display period S103, the display of the pixels 40A and 40D is not changed, and the pixel 40B is displayed from the black display (first gradation). The display is changed to dark gray display (third gradation), and the display of the pixel 40D is changed from white display (second gradation) to light gray display (fourth gradation).

  FIG. 13 is a timing chart used for explaining the second driving method. In FIG. 13, the operation is performed in the order of the previous image display period S101 for displaying the previous image shown in FIG. 12, the power-off period S102, and the next image display period S103 for displaying the next image shown in FIG. The potential of the pixel electrode of each of the pixels 40A to 40D when the display is changed from the previous image to the next image in (a) is shown.

  14 to 16 are schematic diagrams illustrating connection states of the pixel circuits of the pixels 40A to 40D in each period illustrated in FIG. In each of FIGS. 14 to 16, pixels 40 </ b> A to 40 </ b> D and first control lines 91 to fourth control lines 94 are shown, and are based on the first switch circuit SC <b> 1 and the second switch circuit SC <b> 2 that constitute the pixel circuit. The switching operation is represented. FIG. 14 is a diagram illustrating a connection state of the pixels 40 corresponding to the previous image display period S101, and FIG. 15 is a diagram illustrating a connection state of the pixels 40 corresponding to the image display period ST32a. FIG. 16 is a diagram illustrating a connection state of the pixels 40 corresponding to the image display period ST32b. In FIGS. 14 to 16, the pixels 40 </ b> A to 40 </ b> D shown in FIG. 12A are arranged in a line in the horizontal direction in the drawing in order to make the drawings easy to see.

In the second driving method of the electrophoretic display device of the present embodiment, first, the previous image is displayed on the display unit 5 in the previous image display period S101. In the display unit 5 shown in FIG. 12A, the pixels 40A and 40B are displayed in white, and the pixels 40C and 40D are displayed in black.
The previous image display period S101 includes an image signal input period ST11 and an image display period ST12.
The previous image display period S101 in the second driving method is the same as the previous image display period S101 in the first driving method described above except that the image data stored in the pixel 40 is different, and the other operations are the same. Description is omitted as appropriate.

  In the image signal input period ST11, the common power supply modulation circuit 64 drives the first latch circuit LAT1 and the second latch circuit LAT2 of each pixel. At this time, the common electrode wiring 55, the first control line 91, the second control line 92, the third control line 93, and the fourth control line 94 are electrically connected to the Hi-Z by the common power supply modulation circuit 64. It is in a state.

In the image signal input period ST11, the scanning line driving circuit 61 and the data line driving circuit 62 correspond to the first latch circuit LAT1 and the second latch circuit LAT2 of the pixel 40 constituting the display unit 5 corresponding to the image data. Memorize the potential.
In the image signal input period ST11, the first latch circuit LAT1 and the second latch circuit LAT2 of each of the pixels 40A to 40D shown in FIG. , (1, 0), (0, 1), (0, 0) are stored. Thereby, in the pixel 40 </ b> A, the second control line 92 and the fourth control line 94 are connected to the pixel electrode 35. In the pixel 40 </ b> B, the second control line 92 and the third control line 93 are connected to the pixel electrode 35. In the pixel 40 </ b> C, the first control line 91 and the fourth control line 94 are connected to the pixel electrode 35. In the pixel 40 </ b> D, the first control line 91 and the third control line 93 are connected to the pixel electrode 35.

Next, the process proceeds to the image display period ST12.
In this image display period ST12, the common power supply modulation circuit 64 supplies a high level potential H (15V) to the high potential power supply line 50 and supplies a low level potential L (0V) to the low potential power supply line 49. Therefore, image signal data held at the high level potential H (5 V) in the first latch circuit LAT1 or the second latch circuit LAT2 is held at a higher high level potential H (15 V).
Further, the common power supply modulation circuit 64 sets the potential S1 of the first control line 91 to the high level potential H (15V) and sets the potential S2 of the second control line 92 to the low level potential L (0V). Further, the common power supply modulation circuit 64 maintains the Hi-Z state of the third control line 93 and the fourth control line 94, and the common electrode wiring 55 has a low level potential L (0 V) and a high level potential H (15 V). ) In a predetermined cycle, and a rectangular wave pulse is supplied.

Thereby, in the pixel 40A and the pixel 40B, the potential of the pixel electrode 35 becomes the same potential as the potential S2 of the second control line 92. The potential VA of the pixel electrode 35 and the potential VB of the pixel electrode 35 are both low level potential L (0 V). In the pixels 40 </ b> A and 40 </ b> B, the electrophoretic element 32 is driven by a potential difference generated between each pixel electrode 35 (low level potential L) while the potential Vcom of the common electrode 37 is the high level potential H. Thereby, as shown in FIG. 14, the pixel 40A and the pixel 40B are displayed in white.
In the pixels 40C and 40D, the potential of the pixel electrode 35 is the same as the potential S1 of the first control line 91. The potential VC of the pixel electrode 35 and the potential VD of the pixel electrode 35 are both high level potential H (15 V). In the pixels 40 </ b> C and 40 </ b> D, the electrophoretic element 32 is driven by a potential difference generated between each pixel electrode 35 (high level potential H) while the potential Vcom of the common electrode 37 is the low level potential L. Thereby, as shown in FIG. 14, the pixels 40C and 40D are displayed in black.

Thus, the previous image shown in FIG. 12A is displayed on the display unit 5 in the previous image display period S101.
Then, the process proceeds to the power-off period S102. In the power-off period S102, the first control line 91 and the second control line 92 are both in the Hi-Z state. As described above, the pixel electrodes 35 belonging to the pixels 40A to 40D are connected to the first control line 91 or the second control line 92 via the first switch circuit SC1 and the second switch circuit SC2. Therefore, all the pixel electrodes 35 are set to the Hi-Z state. The common electrode 37 is also set to the Hi-Z state by the common power supply modulation circuit 64.

Next, the process proceeds to the next image display period S103 for displaying the next image shown in FIG.
As shown in FIG. 13, the next image display period S103 includes an image signal input period ST31 (first step), an image display period ST32a (first display step in the second step), and an image display period ST32b (second step). 2nd display step in the above step).
The image data written in the image signal input period ST31 of the next image display period S103 is data shown in FIG. 12B, and is data that reversely displays the pixels 40A to 40D.

In the image signal input period ST31 (first step), as in the above-described image signal input period ST11, the common power supply modulation circuit 64 supplies each pixel 40 to the high level potential H (through the high potential power supply line 50). 5V) is supplied with a low level potential L (0 V) via a low potential power line 49. As a result, the first latch circuit LAT1 and the second latch circuit LAT2 of each pixel are driven.
At this time, the common electrode wiring 55, the first control line 91, the second control line 92, the third control line 93, and the fourth control line 94 are electrically connected to the Hi-Z by the common power supply modulation circuit 64. It is in a state.

  In the image signal input period ST31, as in the above-described image signal input period ST11, the scanning line driving circuit 61 and the data line driving circuit 62 are provided with the first latch circuit LAT1 and the second latch circuit LAT2 of each pixel 40. To store the image data. In each of the first latch circuit LAT1 and the second latch circuit LAT2 of the pixels 40A to 40D shown in FIG. 12A, 2-bit image data (0, 0), ( 0, 1), (1, 0), (1, 1) are stored. These data are complementary to the data input in the above image signal input period ST11.

Thereby, as shown in FIG. 15, in the pixel 40 </ b> A, the first control line 91 and the third control line 93 are connected to the pixel electrode 35.
In the pixel 40 </ b> B, the first control line 91 and the fourth control line 94 are connected to the pixel electrode 35.
In the pixel 40 </ b> C, the second control line 92 and the third control line 93 are connected to the pixel electrode 35.
In the pixel 40 </ b> D, the second control line 92 and the fourth control line 94 are connected to the pixel electrode 35.
At this time, the common electrode wiring 55, the first control line 91, the second control line 92, the third control line 93, and the fourth control line 94 are set in the Hi-Z state by the common power supply modulation circuit 64. Therefore, the electrophoretic element 32 is not driven yet.

Next, the process proceeds to the image display period ST32a (first display step in the second step).
In the image display period ST32a, the common power supply modulation circuit 64 supplies a high level potential H (15V) to the high potential power supply line 50 and supplies a low level potential L (0V) to the low potential power supply line 49. Therefore, image signal data held at the high level potential H (5 V) in the first latch circuit LAT1 or the second latch circuit LAT2 is held at a higher high level potential H (15 V).
In the image display period ST32a, the common power supply modulation circuit 64 sets the potential S1 of the first control line 91 to the high level potential H (15V) and sets the potential S2 of the second control line 92 to the low level potential L (0V). ). Further, the common power supply modulation circuit 64 maintains the Hi-Z state of the third control line 93 and the fourth control line 94. The common power supply modulation circuit 64 supplies the common electrode wiring 55 with a rectangular wave pulse that repeats a high level potential H (15 V) and a low level potential L (0 V) at a predetermined cycle.

As a result, as shown in FIG. 15, in the pixel 40 </ b> A and the pixel 40 </ b> B, the potential of the pixel electrode 35 is the same as the potential S <b> 1 of the first control line 91. Then, the potential VA and the potential VB of the pixel electrode 35 become a high level potential H (15 V).
In the pixels 40C and 40D, the potential of the pixel electrode 35 is the same as the potential S2 of the second control line 92. Then, the potential VC and the potential VD of the pixel electrode 35 become the low level potential L (0 V). Thus, in the image display period ST32a, the pixel 40A and the pixel 40B change to black (first gradation), and the pixel 40C and the pixel 40D change to white (second gradation).

Next, the process proceeds to the image display period ST32b (second display step in the second step).
In the image display period ST32b, the common power supply modulation circuit 64 maintains the potential states of the high potential power supply line 50 and the low potential power supply line 49 in the image display period ST32a. Therefore, the image signal data held in the first latch circuit LAT1 or the second latch circuit LAT2 is held at the potential in the image display period ST32a.
In addition, the common power supply modulation circuit 64 sets the first control line 91 and the second control line 92 to the Hi-Z state in the image display period ST32b. Further, the common power supply modulation circuit 64 sets the potential S3 of the third control line 93 to the high level potential H (15V) and sets the potential S4 of the fourth control line 94 to the low level potential L (0V). The common power supply modulation circuit 64 continues to supply the common electrode wiring 55 with a rectangular wave pulse that repeats the high level potential H (15 V) and the low level potential L (0 V) at a predetermined cycle.

Thereby, as shown in FIG. 16, in the pixel 40 </ b> A and the pixel 40 </ b> C, the potential of the pixel electrode 35 becomes the same potential as the potential S <b> 3 of the third control line 93. The potential VA of the pixel electrode 35 and the potential VC of the pixel electrode 35 are both high level potential H (15 V). In the pixels 40B and 40D, the potential of the pixel electrode 35 is the same as the potential S4 of the fourth control line 94. The potential VB of the pixel electrode 35 and the potential VD of the pixel electrode 35 are both low level potential L (0 V).
Accordingly, in the pixel 40A and the pixel 40D, since the potential of the pixel electrode 35 is the same as that in the image display period ST32a, the electrophoretic elements (black particles 26 and white particles 27) in the electrophoretic element 32 do not move. Accordingly, as shown in FIG. 16, in the image signal input period ST31, the pixel 40A in which the first set of data (0, 0) is input to the latch circuit maintains the black (first gradation) display. Further, the white (second gradation) display of the pixel 40D in which the second set of data (1, 1) is input to the latch circuit in the image signal input period ST31 is maintained.

In the pixel 40B, since the potential VB of the pixel electrode 35 changes from the high level potential H (15V) in the image display period ST32a to the low level potential L (0V), the potential Vcom of the common electrode 37 is changed to the high level potential H (15V). ), The electrophoretic element 32 is driven by a potential difference generated between the pixel electrode 35 (low level potential L). Accordingly, as shown in FIG. 16, the white particles 27 migrate from the pixel electrode 35 toward the common electrode 37, and the black particles 26 migrate from the common electrode 37 toward the pixel electrode 35. Note that during the period in which the potential Vcom of the common electrode 37 is the low level potential L, the potential VB and the potential Vcom are the same potential, and thus the electrophoretic elements (black particles 26 and white particles 27) in the electrophoretic element 32 are Do not run. Here, depending on the length of the image display period ST32b, the black density of the pixel 40B changes toward a lower density. For example, as the period of the image display period ST32b is longer, the number of white particles 27 moving to the common electrode 37 side increases (in contrast, the black particles 26 moving to the pixel electrode 35 side also increase), and the black density of the pixel 40C. Changes towards a thinner concentration. Therefore, by defining the length of the image display period ST32b, the migration of the white particles 27 and the black particles 26 is stopped before, for example, the black particles 26 reach the intermediate point between the common electrode 37 and the pixel electrode 35. Thus, the pixel 40B can be displayed in dark gray.
That is, as shown in FIG. 16, in the image signal input period ST31, the pixel 40B in which the third set of data (0, 1) is input to the latch circuit is changed from black (first gradation) to dark gray (third Change the display to).

  In the pixel 40C, the potential VC of the pixel electrode 35 changes from the low level potential L (0V) in the image display period ST32a to the high level potential H (15V), and thus the potential Vcom of the common electrode 37 is changed to the low level potential L (0V). ), The electrophoretic element 32 is driven by a potential difference generated between the pixel electrode 35 (high level potential H). Accordingly, as shown in FIG. 16, the black particles 26 migrate from the pixel electrode 35 toward the common electrode 37, and the white particles 27 migrate from the common electrode 37 toward the pixel electrode 35. Note that, during the period in which the potential Vcom of the common electrode 37 is the high level potential H, the potential VC and the potential Vcom are the same potential, so the electrophoretic elements (the black particles 26 and the white particles 27) in the electrophoretic element 32 are Do not run. Here, depending on the length of the image display period ST32b, the white density of the pixel 40C changes toward a higher density. For example, as the period of the image display period ST32b is longer, the number of black particles 26 moving to the common electrode 37 side increases (conversely, the white particles 27 moving to the pixel electrode 35 side also increase), and the white density of the pixel 40C. Changes toward higher concentrations. Therefore, by defining the length of the image display period ST32b, the migration of the white particles 27 and the black particles 26 is stopped before, for example, the white particles 27 reach the intermediate point between the common electrode 37 and the pixel electrode 35. Thus, the pixel 40C can be displayed in light gray. That is, as shown in FIG. 16, in the image signal input period ST31, the pixel 40C in which the fourth set of data (1, 0) is input to the latch circuit is changed from white (second gradation) to light gray (fourth). Change the display to).

  As described above, in the second driving method, the pixel (pixel 40B) that changes the gradation display from black (first gradation) to dark gray (third gradation) and gradation display are displayed. A pixel that does not change (pixel 40A), a pixel that changes gradation display from white (second gradation) to light gray (fourth gradation) (pixel 40C), and a pixel that does not change gradation display (pixel 40D) The data transfer of the image signal with respect to () can be performed once in the image signal input period ST31, so that the power consumption for the data transfer can be reduced. In the data display period (image display period ST32a and image display period ST32b), a pixel (pixel 40B) that changes the gradation display from black (first gradation) to dark gray (third gradation display). And electrophoretic particles (white particles 27 and black particles 26) in pixels (pixel 40C) that change the gradation display from white (second gradation display) to light gray (fourth gradation). Can be gradually migrated from the pixel electrode 35 to the common electrode 37 or from the common electrode 37 to the pixel electrode 35. As a result, the image display on the display unit 5 can be changed so that the previous display gradually disappears and the next display gradually appears, that is, the display can be changed smoothly, and the display quality can be improved. . In addition, high-precision electric field control like gray scale display formed from a plurality of gradations can be performed, and display quality can be improved.

  Note that the gradation display is changed from black (first gradation) to dark gray (third gradation), and the gradation is changed from white (second gradation) to light gray (fourth gradation). Although the driving method for changing the tone display has been described, the present invention is not limited to this example. The tone display is changed from black (first tone) to light gray (fourth tone), and white ( A driving method of changing the gradation display from the second gradation) to dark gray (third gradation) may be used. For example, by defining the length of the image display period ST32b in the second driving method, in the pixel 40B, after the black particles 26 pass through the intermediate point between the common electrode 37 and the pixel electrode 35, the pixel 40C The white particle 27 is stopped after passing through the intermediate point between the common electrode 37 and the pixel electrode 35, so that the pixel 40B can be displayed in light gray and the pixel 40C can be displayed in dark gray.

[Third driving method]
Next, a third driving method of the electrophoretic display device according to this embodiment will be described with reference to FIGS.
FIG. 17 is a timing chart used for explaining the third driving method. In FIG. 17, the next image display period S103 in the first driving method shown in FIG. 7 is divided into an image signal input period ST31 (first step) and an image display period ST32a (first display step in the second step). ). FIG. 18 is a schematic diagram illustrating a connection state of the pixel circuits of the pixels 40A to 40D in the image display period ST32a illustrated in FIG.

In the third driving method, the image signal input period ST31 in the previous image display period S101, the power-off period S102, and the next image display period S103 shown in FIG. 17 is the same as the first driving method shown in FIG. Therefore, explanation is omitted. That is, at the end of the image signal input period ST31, the connection state of the pixel circuits of the pixels 40A to 40D is as shown in FIG.
In the pixel 40A, the second control line 92 and the fourth control line 94 are connected to the pixel electrode 35, and in the pixel 40B, the second control line 92 and the third control line 93 are connected to the pixel electrode 35. Connected. In the pixel 40C, the first control line 91 and the fourth control line 94 are connected to the pixel electrode 35. In the pixel 40D, the second control line 92 and the fourth control line 94 are connected to the pixel 40. Connected to the electrode 35.

In the image display period ST32a, the common power supply modulation circuit 64 supplies a high level potential H (15V) to the high potential power supply line 50 and supplies a low level potential L (0V) to the low potential power supply line 49. Therefore, image signal data held at the high level potential H (5 V) in the first latch circuit LAT1 or the second latch circuit LAT2 is held at a higher high level potential H (15 V).
In the image display period ST32a, the common power supply modulation circuit 64 sets the potential S1 of the first control line 91 to the high level potential H (15V) and sets the potential S3 of the third control line 93 to the low level potential L (0V). ). In addition, the common power supply modulation circuit 64 maintains the Hi-Z state of the second control line 92 and the fourth control line 94. Further, the common power supply modulation circuit 64 supplies the common electrode wiring 55 with a rectangular wave pulse that repeats a low level potential L (0 V) and a high level potential H (15 V) at a predetermined cycle.

  Accordingly, as illustrated in FIG. 18, the pixel 40 </ b> A and the pixel 40 </ b> D have both the second control line 92 and the fourth control line 94 connected to the pixel electrode 35 in the Hi-Z state. 35 becomes a Hi-Z state. Thereby, as shown in FIG. 18, the black display of the pixel 40A and the white display of the pixel 40D are maintained.

  In the pixel 40B, the potential VB of the pixel electrode 35 becomes the same potential as the potential S3 of the third control line 93. Then, the potential VB of the pixel electrode 35 becomes the low level potential L (0 V). In the pixel 40B, during the period in which the potential Vcom of the common electrode 37 is the high level potential H, the electrophoretic element 32 is driven by a potential difference generated between the pixel electrode 35 (low level potential L). Thereby, as shown in FIG. 17, the white particles 27 migrate from the pixel electrode 35 toward the common electrode 37, and the black particles 26 migrate from the common electrode 37 toward the pixel electrode 35. Note that during the period in which the potential Vcom of the common electrode 37 is the low level potential L, the potential VB and the potential Vcom are the same potential, and thus the electrophoretic elements (black particles 26 and white particles 27) in the electrophoretic element 32 are Do not run. Here, depending on the length of the image display period ST32a, the black density of the pixel 40B changes toward a lower density. For example, as the period of the image display period ST32a is longer, the number of white particles 27 moving to the common electrode 37 side increases (in contrast, the black particles 26 moving to the pixel electrode 35 side also increase), and the black density of the pixel 40B. Concentration changes as the concentration gets thinner.

  In the pixel 40 </ b> C, the potential VC of the pixel electrode 35 is the same as the potential S <b> 1 of the first control line 91. Then, the potential VC of the pixel electrode 35 becomes a high level potential H (15 V). In the pixel 40 </ b> C, the electrophoretic element 32 is driven by a potential difference generated between the common electrode 37 and the pixel electrode 35 (high level potential H) while the potential Vcom of the common electrode 37 is at the low level potential L. Accordingly, as shown in FIG. 17, the black particles 26 migrate from the pixel electrode 35 toward the common electrode 37, and the white particles 27 migrate from the common electrode 37 toward the pixel electrode 35. Note that, during the period in which the potential Vcom of the common electrode 37 is the high level potential H, the potential VC and the potential Vcom are the same potential, so the electrophoretic elements (the black particles 26 and the white particles 27) in the electrophoretic element 32 are Do not run. Here, depending on the length of the image display period ST32a, the white density of the pixel 40C changes toward a higher density. For example, as the period of the image display period ST32a is longer, the number of black particles 26 that move to the common electrode 37 side increases (conversely, the white particles 27 that move to the pixel electrode 35 side also increase), and the white density of the pixel 40C. The concentration changes toward the higher concentration.

Thus, in the image display period ST32a, the gradation display of the pixel 40A and the pixel 40D storing the first set of data (1, 1) in the image signal input period ST31 is not changed, and the gradation display of the previous image (previous (Gradation display in the image display period S101) is maintained. Further, the display state of the pixel 40B storing the second set of data (1, 0) in the image signal input period ST31 gradually changes from black (first gradation) to white (second gradation), In the image signal input period ST31, the display state of the pixel 40C storing the third set of data (0, 1) gradually changes from white (second gradation) to black (first gradation). .
For example, during the period of the image display period ST32a, the black particles 26 reach the pixel electrode 35 and the white particles 27 reach the common electrode 37 in the pixel 40B, or the white particles 27 reach the pixel electrode 35 in the pixel 40C. Then, by defining the black particle 26 to be the longer of the time period for reaching the common electrode 37, the display state of the pixel 40B is set to white display (second gradation), and the display state of the pixel 40C is set to black display ( First gradation).
Further, by defining the length of the image display period ST32b to be short, in the pixel 40B, the migration of the white particles 27 and the black particles 26, for example, the black particles 26 at an intermediate point between the common electrode 37 and the pixel electrode 35. By stopping before reaching, the pixel 40B can be displayed in dark gray. Further, by defining the length of the period of the image display period ST32b to be short, in the pixel 40C, the migration of the white particles 27 and the black particles 26 is caused, for example, at the intermediate point between the common electrode 37 and the pixel electrode 35. By stopping before reaching, the pixel 40C can be displayed in light gray.

  Thus, in the third driving method, in the image signal input period ST31 (first step), the first latch circuit LAT1 and the second latch circuit LAT2 (first memory circuit and second memory circuit). ), The pixel (pixel 40A and pixel 40D) to which the image signal data of (1, 1) (first set of image signal data) is input is black (first step) in the image display period ST32b (second step). (1 gradation) or white (second gradation) gradation display is not changed. In addition, in the image signal input period ST31, a pixel (pixel) in which (1,0) image signal data (second set of image signal data) is input to the first latch circuit LAT1 and the second latch circuit LAT2. 40B) smoothly changes the gradation display from black to white in the image display period ST32b. Further, in the image signal input period ST31, a pixel (pixel) in which (0, 1) image signal data (third set of image signal data) is input to the first latch circuit LAT1 and the second latch circuit LAT2 40C) smoothly changes the gradation display from white to black in the image display period ST32b. As a result, in the second step, it is possible to smoothly change the display of the pixels whose gradation display is changed regardless of the black or white display, thereby improving the display quality. Further, by defining the period of the image display period ST32b, it is possible to keep the pixels for changing the gradation display in the intermediate gradation display, so that high accuracy such as gray scale display formed from a plurality of gradations can be achieved. Display quality can also be improved by performing appropriate electric field control.

(Electronics)
Next, a case where the electrophoretic display device 100 of each of the above embodiments is applied to an electronic device will be described.
FIG. 19 is a front view of the wrist watch 1000. The wrist watch 1000 includes a watch case 1002 and a pair of bands 1003 connected to the watch case 1002.
On the front surface of the watch case 1002, a display unit 1005 including the electrophoretic display device 100 of the above embodiment, a second hand 1021, a minute hand 1022, and an hour hand 1023 are provided. On the side surface of the watch case 1002, a crown 1010 and an operation button 1011 are provided as operation elements. The crown 1010 is connected to a winding stem (not shown) provided inside the case, and is integrally provided with the winding stem so that it can be pushed and pulled in multiple stages (for example, two stages) and can be rotated. . The display unit 1005 can display a background image, a character string such as date and time, or a second hand, a minute hand, and an hour hand.

  FIG. 20 is a perspective view illustrating a configuration of the electronic paper 1100. An electronic paper 1100 includes the electrophoretic display device 100 of the above embodiment in a display area 1101. The electronic paper 1100 is flexible and includes a main body 1102 made of a rewritable sheet having the same texture and flexibility as conventional paper.

  FIG. 21 is a perspective view showing the configuration of the electronic notebook 1200. An electronic notebook 1200 is obtained by bundling a plurality of the electronic papers 1100 and sandwiching them between covers 1201. The cover 1201 includes display data input means (not shown) for inputting display data sent from an external device, for example. Thereby, according to the display data, the display content can be changed or updated while the electronic paper is bundled.

  According to the wristwatch 1000, the electronic paper 1100, and the electronic notebook 1200 described above, the electrophoretic display device 100 according to the present invention is employed, so that a high-quality display with a smooth outline is possible and power saving is achieved. In addition, an electronic device having an excellent display portion is obtained. In addition, said electronic device illustrates the electronic device which concerns on this invention, Comprising: The technical scope of this invention is not limited. For example, the electrophoretic display device according to the present invention can be suitably used for a display portion of an electronic device such as a mobile phone or a portable audio device.

DESCRIPTION OF SYMBOLS 100 ... Electrophoretic display apparatus, 20 ... Microcapsule, 21 ... Dispersion medium, 26 ... Black particle, 27 ... White particle, 30 ... Element substrate, 31 ... Opposite substrate, 32 ... Electrophoretic element, 33 ... Adhesive layer, 35 ... Pixel electrode, 37 ... Common electrode,
40, 40A, 40B, 40C, 40D ... pixel, ST1 ... first selection transistor, ST2 ... second selection transistor,
49 ... Low-potential power line, 50 ... High-potential power line, 55 ... Common electrode wiring, 61 ... Scanning line drive circuit,
62 ... data line driving circuit, 63 ... controller, 64 ... common power supply modulation circuit, 66, Y1, Y2, Ym ... scanning line, 68, X1, Xn ... data line, 91 ... first control line, 92 ... second Control line 93, third control line, 94, fourth control line,
LAT1 ... first latch circuit, LAT2 ... second latch circuit, SC1 ... first switch circuit, SC2 ... second switch circuit, TG1 ... first transmission gate, TG2 ... second transmission gate, TG3 ... Third transmission gate, TG4 ... Fourth transmission gate,
NM1, NM2, NM3, NM4, NM5, NM6, NM7, NM8 ... N-MOS transistors,
PM1, PM2, PM3, PM4, PM5, PM6, PM7, PM8 ... P-MOS transistors,
INV1, INV2, INV3, INV4 ... inverter,
N11, N21 ... data input terminals, N12, N22 ... data output terminals,
H: High level potential, L: Low level potential,
S101 ... previous image display period, S102 ... power off period, S103 ... next image display period, ST11, ST31 ... image signal input period, ST12, ST32a, ST32b ... image display period

Claims (5)

An electrophoretic element including electrophoretic particles is sandwiched between a pair of substrates, and includes a display unit including a plurality of pixels. The display unit includes a pixel electrode formed for each pixel, and the electrophoresis A first set of control lines, a third control line, and a counter electrode opposed to the plurality of pixel electrodes via an element; a first control line and a second control line connected to each of the pixels; A second set of control lines comprising a fourth control line,
For each pixel, a first memory circuit that stores image signal data, a data line that supplies image signal data, and a first pixel switching element that connects the first memory circuit, and the pixel electrode And a first switch circuit that connects any one of the control lines in the first set of control lines, a second memory circuit that stores image signal data, the data lines, and the second memory circuit An electrophoretic display device including: a second pixel switching element that connects the pixel electrode; and a second switch circuit that connects the pixel electrode and one of the control lines of the second set of control lines. A driving method comprising:
Image signal data is input to the first memory circuit via the first pixel switching element, and image signal data is input to the second memory circuit via the second pixel switching element. 1 step,
A second step of controlling the first switch circuit based on an output from the first memory circuit and controlling the second switch circuit based on an output from the second memory circuit;
I have a,
In the first step,
The grayscale display is not changed for the data of the first set of image signals in which the second control line and the pixel electrode are connected and the fourth control line and the pixel electrode are connected. Input to the first memory circuit and the second memory circuit for controlling pixels;
The data of the second set of image signals, in which the second control line and the pixel electrode are connected and the third control line and the pixel electrode are connected, are obtained from the first gradation display. Input to the first memory circuit and the second memory circuit for controlling the pixel to change the gradation display to the second gradation display;
Data of a third set of image signals, in which the first control line and the pixel electrode are connected and the fourth control line and the pixel electrode are connected, are obtained from the second gradation display. Input to the first memory circuit and the second memory circuit for controlling the pixel to change the gradation display to the first gradation display;
In the second step,
While inputting a rectangular wave that repeats the first potential and the second potential to the counter electrode for one period or more, the second potential is supplied to the first control line, and the second control line is supplied to the second control line. A first display step of supplying a potential input to the counter electrode, and bringing the third control line and the fourth control line into a high impedance state that is electrically disconnected;
The first control line and the second control line were each electrically disconnected while inputting a rectangular wave that repeats the first potential and the second potential to the counter electrode for one period or more. A second display step is alternately repeated in which the first potential is supplied to the third control line and the potential input to the counter electrode is supplied to the fourth control line in a high impedance state. A driving method for an electrophoretic display device. An electrophoretic element including electrophoretic particles is sandwiched between a pair of substrates, and includes a display unit including a plurality of pixels. The display unit includes a pixel electrode formed for each pixel, and the electrophoresis A first set of control lines, a third control line, and a counter electrode opposed to the plurality of pixel electrodes via an element; a first control line and a second control line connected to each of the pixels; A second set of control lines comprising a fourth control line,
For each pixel, a first memory circuit that stores image signal data, a data line that supplies image signal data, and a first pixel switching element that connects the first memory circuit, and the pixel electrode And a first switch circuit that connects any one of the control lines in the first set of control lines, a second memory circuit that stores image signal data, the data lines, and the second memory circuit An electrophoretic display device including: a second pixel switching element that connects the pixel electrode; and a second switch circuit that connects the pixel electrode and one of the control lines of the second set of control lines. A driving method comprising:
Image signal data is input to the first memory circuit via the first pixel switching element, and image signal data is input to the second memory circuit via the second pixel switching element. 1 step,
A second step of controlling the first switch circuit based on an output from the first memory circuit and controlling the second switch circuit based on an output from the second memory circuit;
I have a,
In the first step,
The first control line and the pixel electrode are connected and the third control line and the pixel electrode are connected. The first set of image signal data is displayed in a first gradation. Input to the first memory circuit and the second memory circuit for controlling the pixel,
The second control line and the pixel electrode are connected, and the fourth control line and the pixel electrode are connected. The second set of image signal data is displayed in the second gradation. Input to the first memory circuit and the second memory circuit for controlling the pixel,
Data of a third set of image signals, in which the first control line and the pixel electrode are connected and the fourth control line and the pixel electrode are connected, are displayed from the first gradation display. Input to the first memory circuit and the second memory circuit for controlling the pixel to change the gradation display to a third gradation display;
Data of a fourth set of image signals, in which the second control line and the pixel electrode are connected, and the third control line and the pixel electrode are connected, are obtained from the second gradation display. Input to the first memory circuit and the second memory circuit for controlling the pixel to change the gradation display to the fourth gradation display;
In the second step,
While inputting a rectangular wave that repeats the first potential and the second potential to the counter electrode for one period or more, the second potential is supplied to the first control line, and the second control line is supplied to the second control line. A first display step of supplying the first potential and bringing the third control line and the fourth control line into a high impedance state electrically disconnected,
The first control line and the second control line were each electrically disconnected while inputting a rectangular wave that repeats the first potential and the second potential to the counter electrode for one period or more. A second display step of setting the high impedance state, supplying the second potential to the third control line, and supplying the first potential to the fourth control line; Subsequently, the second display step is performed , and the method for driving the electrophoretic display device. An electrophoretic element including electrophoretic particles is sandwiched between a pair of substrates, and includes a display unit including a plurality of pixels. The display unit includes a pixel electrode formed for each pixel, and the electrophoresis A first set of control lines, a third control line, and a counter electrode opposed to the plurality of pixel electrodes via an element; a first control line and a second control line connected to each of the pixels; A second set of control lines comprising a fourth control line,
For each pixel, a first memory circuit that stores image signal data, a data line that supplies image signal data, and a first pixel switching element that connects the first memory circuit, and the pixel electrode And a first switch circuit that connects any one of the control lines in the first set of control lines, a second memory circuit that stores image signal data, the data lines, and the second memory circuit An electrophoretic display device including: a second pixel switching element that connects the pixel electrode; and a second switch circuit that connects the pixel electrode and one of the control lines of the second set of control lines. A driving method comprising:
Image signal data is input to the first memory circuit via the first pixel switching element, and image signal data is input to the second memory circuit via the second pixel switching element. 1 step,
A second step of controlling the first switch circuit based on an output from the first memory circuit and controlling the second switch circuit based on an output from the second memory circuit;
I have a,
In the first step,
The grayscale display is not changed for the data of the first set of image signals in which the second control line and the pixel electrode are connected and the fourth control line and the pixel electrode are connected. Input to the first memory circuit and the second memory circuit for controlling pixels;
The data of the second set of image signals, in which the second control line and the pixel electrode are connected and the third control line and the pixel electrode are connected, are obtained from the first gradation display. Input to the first memory circuit and the second memory circuit for controlling the pixel to change the gradation display to the second gradation display;
Data of a third set of image signals, in which the first control line and the pixel electrode are connected and the fourth control line and the pixel electrode are connected, are obtained from the second gradation display. Input to the first memory circuit and the second memory circuit for controlling the pixel to change the gradation display to the first gradation display;
In the second step,
While inputting a rectangular wave that repeats the first potential and the second potential to the counter electrode for one period or more, the second potential is supplied to the first control line, and the third control line is supplied to the third control line. A driving method of an electrophoretic display device, wherein the first potential is supplied and the second control line and the fourth control line are electrically disconnected from each other in a high impedance state . Signal supply means for supplying a potential to the first control line, the second control line, the third control line, the fourth control line, and the counter electrode;
A selection signal supply means for supplying a selection signal for defining an ON timing of the switching element to the first pixel switching element and the second pixel switching element provided for each pixel;
Data supply means for supplying image signal data to the first memory circuit via the first pixel switching element and to the second memory circuit via the second pixel switching element;
The provided, an electrophoretic display device and executes the driving method of the electrophoretic display device according to any one of claims 1 to 3. An electronic apparatus comprising the electrophoretic display device according to claim 4 .

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