JP5459937B2 - Integrated circuit and audio device - Google Patents

Description

  The present invention relates to an integrated circuit and an audio device, and more particularly to an integrated circuit and an audio device that transfer audio data having different frequencies.

  In an audio system such as an in-vehicle audio system, for example, sound data such as a warning sound is stored in a ROM (Read Only Memory), and the sound data is transferred to a speaker when necessary. In such a case, it may be desired to transfer the same audio data with different sampling frequencies (see, for example, Patent Document 1).

FIG. 10 is a diagram showing a configuration of a conventional audio apparatus.
A conventional audio device 90 includes a ROM 91a that stores audio data of frequency (f), a ROM 91b that stores audio data of frequency (1/2 × f), a decoder 92, and a CPU (Central Processing Unit). ) 93, an I2S (The Inter-IC Sound Bus) 94 constituting an interface device for exchanging audio data, an audio processor 95, a D / A conversion circuit 96, a speaker 97, and a standard in an in-vehicle audio system MediaLB (Media Local Bus) 98 used for transferring voice data to a MOST (Media Oriented Systems Transport) network 80, which is a typical voice network, and a local channel for temporarily storing voice data sent to the MOST network 80 And a buffer 99.

  In the audio device 90, the CPU 93 gives a selection signal to the decoder 92, and either the audio data of the frequency (f) stored in the ROM 91a or the audio data of the frequency (1/2 × f) stored in the ROM 91b. The audio data is transferred in the order of I2S94 → audio processor 95 → D / A conversion circuit 96 → speaker 97. When the audio data is written in the local channel buffer 99, MediaLB 98 transfers the audio data to the MOST network 80.

As described above, conventionally, for example, when it is desired to use 44 KHz audio data and 22 KHz audio data, it is necessary to store them in storage means such as a ROM.
JP 2002-351826 A

  However, in the conventional technique, it is necessary to store as many pieces of audio data with different sampling in the ROM, so that there is a problem that the capacity of the ROM increases and the cost increases.

  The present invention has been made in view of these points, and an object of the present invention is to provide an integrated circuit and an audio device that can save the capacity of a storage medium.

  In one aspect, the integrated circuit transfers the audio data to the sampling unit that samples the audio data at the second sampling frequency, and is a first that is n (n is an integer of 1 or more) times the second sampling frequency. A controller that acquires first audio data having a sampling frequency, outputs the first audio data, and information indicating that the number of transfers of the first audio data is n times, and a transfer that stores information on the number of transfers A first voice data stored in the voice data storage unit based on the information on the number of transfers stored in the transfer number storage unit, and a voice data storage unit that stores the first voice data; There is provided an integrated circuit comprising: a transfer unit that transfers the same audio data to the sampling unit continuously n times.

  Moreover, in one aspect, the control which acquires audio | voice data which has 1st sampling frequency, and outputs audio | voice data and the information which shows the frequency | count of transfer of audio | voice data according to 2nd sampling frequency different from 1st sampling frequency A transfer number storage unit that stores the number of transfers, and an audio data storage unit that stores the audio data, and continuously stores the audio data stored in the audio data storage unit according to the transfer number of the transfer number storage unit And a transfer unit that transfers to the outside and a transfer unit that is provided to transfer audio data via the network and changes the length of the transfer permission signal output from the control unit according to the transfer count of the transfer count storage unit There is provided an integrated circuit comprising: a signal output unit; and an output unit that continuously transfers the audio data acquired by the control unit according to the length of the transfer permission signal. .

  Moreover, in one aspect, the audio | voice data storage part which stores 1st audio | voice data which has a 1st sampling frequency, 1st audio | voice data are acquired from an audio | voice data storage part, 1st audio | voice data, and 1st audio | voice data A control unit that outputs information indicating that the number of transfers is n (n is an integer equal to or greater than 1), a transfer number storage unit that stores information on the number of transfers, and an audio data storage that stores first audio data And a transfer unit that continuously transfers the same audio data as the first audio data stored in the audio data storage unit n times based on the information on the transfer number stored in the transfer number storage unit When the same audio data as the first audio data is continuously received n times from the transfer unit, the received audio data is sampled at the second sampling frequency that is 1 / n of the first sampling frequency. The audio device is provided, characterized in that it comprises a sampling unit for generating a second voice data having a second sampling frequency, the.

  According to the present invention, data of frequency (1 / n × f) can be created by transferring n times. Therefore, it is not necessary to store a plurality of data having different sampling frequencies in a ROM or the like, and the circuit scale can be reduced.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
First, an outline of the present invention will be described, and then an embodiment will be described.
FIG. 1 is a diagram showing an outline of the present invention.

The integrated circuit 1 includes a control unit 2 and a transfer unit 3.
The control unit 2 acquires the voice data to be transferred, and outputs the voice data and the number of times the voice data is transferred according to the frequency. This audio data is stored in advance in, for example, a storage device (ROM 6 in FIG. 1).

The transfer unit 3 includes an audio data storage unit 4 that stores audio data, and a transfer number storage unit 5 that stores the number of transfers.
In addition, the transfer unit 3 continuously transfers the audio data stored in the audio data storage unit 4 to the outside according to the transfer count of the transfer count storage unit 5. For example, if the number of transfers is two, the transfer is performed twice consecutively.

Here, the outside means, for example, another circuit in the substrate on which the integrated circuit 1 is mounted.
According to such an integrated circuit 1, the acquired audio data and the number of transfers are output by the control unit 2. The voice data and the number of transfers are stored by the transfer unit 3, and the voice data stored in the voice data storage unit 4 is continuously transferred to the outside according to the number of transfers stored in the transfer number storage unit 5. Is done.

Embodiments of the present invention will be described below.
FIG. 2 is a block diagram illustrating the audio apparatus according to the embodiment.
The audio device 10 is a device used in, for example, an in-vehicle audio system, and adopts the MOST standard that constitutes a standard audio network of the in-vehicle audio system.

The audio device 10 includes a ROM 11, an integrated circuit 12, an audio processor 13, a D / A conversion circuit 14, and a speaker 15.
The ROM 11 stores frequency (f) audio data (PCM data) and the like.

  The integrated circuit 12 is integrated on one chip, and includes a CPU 121, an I2S 122, a pulse width changing unit 123, a MediaLB 124, a local channel buffer 125, and a MOST NIC 126.

  The CPU 121 has a function of extracting audio data from the ROM 11 and outputting the audio data to the I2S 122 and the pulse width changing unit 123. In addition, the CPU 121 outputs not only audio data but also a signal (such as a write enable pulse described later) for controlling the audio data.

The I2S 122 is an interface device for exchanging audio data with the outside of the integrated circuit 12 according to an instruction from the CPU 121.
The I2S 122 includes a channel buffer 122a and a twice transfer flag register 122b.

  The channel buffer 122a is composed of a FIFO (First In First Out) buffer for storing audio data received from the CPU 121. The channel buffer 122a has a read pointer (write pointer).

  The two-time transfer flag register 122b is a register for storing a flag (hereinafter referred to as “two-time transfer flag”) for setting the number of times the audio data is transferred from the channel buffer 122a. The CPU 121 sets “0” in the two-time transfer flag. Alternatively, the number of transfers is determined by setting “1”. Detailed processing will be described later.

  The I2S 122 transmits (transfers) the audio data in the channel buffer 122a to the audio processor 13 while incrementing the read pointer of the channel buffer 122a. At this time, the number of times of reading is determined with reference to the twice transfer flag, and the reading pointer is incremented after reading the number of times.

  The pulse width changing unit 123 sends the audio data received from the CPU 121 to the MediaLB 124. Also, the pulse width of the write enable pulse received from the CPU 121 is changed according to the twice transfer flag and sent to the MediaLB 124.

The MediaLB 124 is a local serial bus for connecting a plurality of ICs to the MOST NIC 126, and operates in synchronization with the MOST NIC 126.
When receiving the audio data, the MediaLB 124 temporarily stores the data in the local channel buffer 125.

  The MediaLB 124 operates with a common clock (CLK) with the CPU 121, starts operating when a write enable pulse is input to the write enable terminal, and converts audio data written in the local channel buffer 125 to the MOST NIC 126. Send to.

The local channel buffer 125 is composed of, for example, a RAM (Random Access Memory) or the like, and temporarily stores audio data.
The MOST NIC 126 is a control unit that realizes a MOST network, and forms a MOST network that can transmit and receive signals to and from other MOST NICs.

The audio processor 13 includes an I2S 131 and a DSP (Digital Signal Processor) 132.
The I2S 131 constitutes an interface that receives data transmitted from the I2S 122.

The DSP 132 has a signal processing function, performs predetermined signal processing on the audio data input via the I2S 131, and sends it to the D / A conversion circuit 14.
The D / A conversion circuit 14 converts the input signal into an analog signal and sends it to the speaker 15.

  In such an audio apparatus 10, when outputting sound from the speaker 15, an analog signal is sent to the speaker 15 via the ROM 11, the CPU 121, the I2S 122, the audio processor 13, and the D / A conversion circuit 14. Hereinafter, a path from the ROM 11 to the speaker 15 is referred to as a “first path”.

  Further, when outputting sound from another speaker via the MOST network, the sound data is sent to another speaker via the ROM 11, CPU 121, pulse width changing unit 123, MediaLB 124, and MOST NIC 126. Hereinafter, the path from the ROM 11 to the MOST NIC 126 is referred to as a “second path”.

Next, the operation of the audio device 10 will be briefly described.
FIG. 3 is a diagram showing an output waveform of the integrated circuit.
The integrated circuit 12 transfers the audio data of the frequency (f) stored in the ROM 11 to the audio processor 13 twice. As a result, the audio processor 13 generates audio data of frequency (1/2 × f) by sampling at twice the cycle. For example, when only 44 KHz audio data is stored in the ROM 11, when transferring 22 KHz audio data, the integrated circuit 12 transfers the same audio data to the audio processor 13 twice. As a result, the audio processor 13 and the D / A conversion circuit 14 perform signal processing, so that the speaker 15 outputs a sound whose frequency is half, that is, 22 kHz.

Next, the audio data transfer operation of the integrated circuit 12 will be described. Since the first route and the second route have different transfer methods, description will be made in order.
FIG. 4 is a flowchart showing the transfer operation of the first path of the integrated circuit.

First, the CPU 121 writes “1” or “0” in the twice transfer flag register 122b in accordance with the frequency of the audio data to be transferred (step S1).
Next, the CPU 121 extracts audio data from the ROM 11 and sends it to the I2S 122 (step S2).

Upon receiving the audio data, the I2S 122 stores it in the channel buffer 122a (step S3).
Next, the I2S 122 checks the twice transfer flag (step S4). If the twice transfer flag is “1” (Yes in step S4), the same audio data is read out twice from the channel buffer 122a and sent to the audio processor 13. Thereafter, the read pointer is incremented (step S5).

  On the other hand, if the twice transfer flag is “0” (No in step S4), the audio data is read once from the channel buffer 122a and sent to the audio processor 13. Thereafter, the read pointer is incremented (step S6).

Thus, the transfer operation of the first path of the integrated circuit 12 is completed.
Thereafter, an analog signal is transferred to the speaker 15 via the audio processor 13 and the D / A conversion circuit 14.

Next, the transfer operation of the second path of the integrated circuit 12 will be described.
FIG. 5 is a flowchart showing the transfer operation of the second path of the integrated circuit.
First, the CPU 121 writes “1” or “0” in the twice transfer flag register 122b in accordance with the frequency of audio data transferred to another speaker via the MOST network (step S11).

  Next, the CPU 121 extracts audio data from the ROM 11 and sends it to the pulse width changing unit 123, and simultaneously sends a write enable signal to the pulse width changing unit 123 (step S12).

Next, the pulse width changing unit 123 checks the twice transfer flag (step S13).
If the twice transfer flag is “1” (Yes in step S13), the pulse width of the write enable pulse received from the CPU 121 is increased so that the same audio data is written twice, and the increased pulse width is set to audio. The data is sent to the MediaLB 124 together with the data (step S14).

  If the twice transfer flag is “0” (No in step S13), the write enable pulse received from the CPU 121 is sent to the MediaLB 124 together with the audio data (step S15).

  The MediaLB 124 writes the audio data once or twice in the local channel buffer 125 according to the write period specified by the pulse width of the received write enable pulse (step S16).

  Thereafter, the MediaLB 124 sends the audio data written in the local channel buffer 125 to the MOST NIC 126 (step S17). Here, when the same audio data is written twice, these are sent continuously.

The MOST NIC 126 transfers the received audio data to the MOST network (step S18).
Thus, the transfer operation of the second path of the integrated circuit 12 is completed.

Next, the audio data transfer method in the transfer operation of the integrated circuit 12 will be described in detail.
<Audio data transfer method of the first route>
FIG. 6 is a diagram illustrating a method of transferring audio data of the first route.

When transferring audio data of frequency (1/2 × f), since it is necessary to transfer twice, the CPU 121 sets the twice transfer flag “1” in the twice transfer flag register 122b.
Thereafter, the CPU 121 extracts the audio data from the ROM 11 and transfers it to the channel buffer 122a. As a result of examining the twice transfer flag register 122b, the I2S 122 increments the second transfer without incrementing the read pointer P1 in the first transfer because the two-time transfer flag is “1”. Note that the read audio data is discarded.

<Second-path audio data transfer method>
FIG. 7 is a diagram illustrating operation waveforms of MediaLB in the second path.
As shown in FIG. 7A, when the twice transfer flag is “0”, the pulse width changing unit 123 sends a write pulse (WRN) for one clock (one cycle) to the write enable terminal of the MediaLB 124. Data (WDATA) is written to the local channel buffer 125 once. On the other hand, as shown in FIG. 7B, when the twice transfer flag is “1”, the write pulse to the write enable terminal (WRN) is lengthened by one cycle (two cycles in total). As a result, the MediaLB 124 writes the same audio data (WDATA) in the local channel buffer 125 twice in succession.

  As described above, according to the audio device 10 of the present embodiment, the integrated circuit 12 transfers the audio data of the frequency (1/2 × f) from the audio data of one frequency (f) twice. Since it is created, it is not necessary to store a plurality of data having different sampling frequencies in different ROMs, and the capacity occupied by the audio data in the ROM can be saved. Further, there is no need to provide a selector or the like. Therefore, the audio device 10 can be reduced in size and the configuration can be simplified. Moreover, cost reduction can be achieved.

  In this embodiment, the case of transferring audio data of frequency (1/2 × f) has been described. However, the present invention is not limited to this, and audio data of frequency (1 / n × f) is transferred. You can also For example, when transferring audio data of frequencies (1/3 × f) and (1/4 × f), the integrated circuit 12 transfers the same audio data to the audio processor 13 three times and four times, respectively. When transferring audio data with a frequency (1 / n × f), the integrated circuit 12 transfers the same audio data to the audio processor 13 n times. In this case, for example, the number of times of transfer is set in the transfer flag. For example, when transferring three times, the value of the transfer flag is set to “3”, and when transferring four times, the value of the transfer flag is set to “4” to transfer audio data of an arbitrary frequency. be able to.

Next, an audio apparatus according to the second embodiment will be described.
FIG. 8 is a block diagram illustrating an audio apparatus according to the second embodiment.
Hereinafter, the audio device 10a of the second embodiment will be described focusing on the differences from the first embodiment described above, and description of similar matters will be omitted.

  The audio device 10a of the second embodiment is different from the audio device 10 in that the integrated circuit 12a includes a buffer 127 including a pulse width changing unit 123 between the CPU 121 and the MediaLB 124. The buffer 127 is composed of, for example, a RAM.

  In the integrated circuit 12a of the second embodiment, the CPU 121 writes audio data into the MediaLB 124 via the buffer 127. The writing method is the same as the audio data transfer method of the second path of the first embodiment.

  When the speaker 15 functions as the other speaker described above, that is, when audio data is transmitted from another MOST NIC via the MOST network, the audio data received by the MOST NIC 126 is buffered via the MediaLB 124. 127 is temporarily stored, and then sequentially sent to the CPU 121. Thereafter, the voice is output from the speaker 15 by performing the transfer operation of the first path.

  Next, the transfer operation of the integrated circuit of the second embodiment will be described. Since the transfer operation of the first path is the same as that of the first embodiment, only the transfer operation of the second path is described. explain.

FIG. 9 is a flowchart illustrating the transfer operation of the second path of the integrated circuit according to the second embodiment.
First, the CPU 121 writes “1” or “0” in the twice transfer flag register 122b in accordance with the frequency of audio data transferred to another speaker via the MOST network (step S21).

Next, the CPU 121 extracts audio data from the ROM 11 and sends it to the buffer 127, and at the same time sends a write enable signal to the buffer 127 (step S22).
Next, the pulse width changing unit 123 checks the twice transfer flag (step S23).

  If the twice transfer flag is “1” (Yes in step S23), the pulse width of the write enable pulse received from the CPU 121 is lengthened so that the same sound data is written twice, and the long pulse width is set to the sound data. At the same time, it is sent to MediaLB 124 (step S24).

  If the twice transfer flag is “0” (No in step S23), the write enable pulse received from the CPU 121 is sent to the MediaLB 124 as it is together with the audio data (step S25).

  The MediaLB 124 writes the audio data in the local channel buffer 125 according to the writing period specified by the pulse width of the received write enable pulse (step S26).

Thereafter, the MediaLB 124 sends the audio data written in the local channel buffer 125 to the MOST NIC 126 (step S27).
The MOST NIC 126 transfers the received audio data to the MOST network (step S28).

This completes the transfer operation of the second path of the integrated circuit 12a.
According to the audio device 10a of the second embodiment, the same effect as the audio device 10 of the first embodiment can be obtained.

And according to the audio apparatus 10a of 2nd Embodiment, transmission / reception of audio | voice data can be performed further efficiently.
As described above, the integrated circuit and the audio device of the present invention have been described based on the illustrated embodiment. However, the present invention is not limited to this, and the configuration of each unit is an arbitrary configuration having the same function. Can be substituted. Moreover, other arbitrary structures and processes may be added to the present invention.

It is a figure which shows the outline | summary of this invention. It is a block diagram which shows the audio apparatus of embodiment. It is a figure which shows the output waveform of an integrated circuit. It is a flowchart which shows the transfer operation | movement of the 1st path | route of an integrated circuit. It is a flowchart which shows the transfer operation | movement of the 2nd path | route of an integrated circuit. It is a figure which shows the transfer method of the audio | voice data of a 1st path | route. It is a figure which shows the operation | movement waveform of MediaLB in a 2nd path | route. It is a block diagram which shows the audio apparatus of 2nd Embodiment. It is a flowchart which shows the transfer operation | movement of the 2nd path | route of the integrated circuit of 2nd Embodiment. It is a figure which shows the structure of the conventional audio apparatus.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1, 12, 12a Integrated circuit 2 Control part 3 Transfer part 4 Audio | voice data storage part 5 Transfer frequency storage part 10, 10a Audio apparatus 13 Audio processor 14 D / A conversion circuit 15 Speaker 121 CPU
122 I2S
122a Channel buffer 122b Twice transfer flag register 123 Pulse width change unit 124 MediaLB
125 Local channel buffer 126 MOST NIC
127 Buffer P1 Read pointer

Claims (4)

An integrated circuit that transfers the audio data to a sampling unit that samples audio data at a second sampling frequency,
Wherein (the n 1 or more integer) n of the second sampling frequency to acquire the first audio data having a first sampling frequency is a factor, and the first audio data, the transfer number before Symbol first voice data n a control unit for outputting information indicating the times,
Wherein the transfer count storage unit that stores information transfer count, the first and a voice data storing unit for storing voice data, based on said transfer number storing unit the number of transfers information stored in the voice A transfer unit that transfers the same audio data as the first audio data stored in the data storage unit to the sampling unit continuously n times ;
An integrated circuit comprising:   The audio data storage unit includes a FIFO buffer, and the transfer unit is configured to respond to the number of transfers stored in the transfer number storage unit with the audio data stored in a portion indicated by a read pointer of the FIFO buffer. 2. The integrated circuit according to claim 1, wherein the read pointer of the FIFO buffer is moved after being transferred to the outside. A controller that acquires audio data having a first sampling frequency, and outputs the audio data and information indicating the number of transfers of the audio data according to a second sampling frequency different from the first sampling frequency;
The sound data stored in the sound data storage unit according to the number of transfers in the transfer number storage unit, comprising a transfer number storage unit for storing the transfer number and a sound data storage unit for storing the sound data A transfer unit that continuously transfers to the outside,
A transfer signal output unit provided for transferring the audio data via a network, and changing a length of a transfer permission signal output from the control unit according to the number of transfers in the transfer number storage unit; and the transfer An output unit that continuously transfers the audio data acquired by the control unit according to the length of the permission signal ;
An integrated circuit comprising:   An audio data storage unit for storing first audio data having a first sampling frequency;
  The first audio data is acquired from the audio data storage unit, and the first audio data and information indicating that the number of transfers of the first audio data is n (n is an integer equal to or greater than 1) are output. A control unit,
  A transfer number storage unit for storing the transfer number information; and a sound data storage unit for storing the first sound data, and the sound is stored based on the transfer number information stored in the transfer number storage unit. A transfer unit that transfers the same audio data as the first audio data stored in the data storage unit continuously n times;
  When the same audio data as the first audio data is received n times continuously from the transfer unit, the received audio data is sampled at a second sampling frequency that is 1 / n of the first sampling frequency. A sampling unit for generating second audio data having the second sampling frequency;
  An audio device comprising:

Images