JP5475438B2 - Protection controller with integrated operation test function - Google Patents

Description

  The present invention relates to a protection control device having a comprehensive operation test function.

  For faults that occur in the power system, so-called short-circuits, ground faults, etc., protection control devices installed for each element such as transmission lines, transformers, buses, and generators that form the power system are within the defensive range. The fault is removed by disconnecting the section including the fault point from the remaining healthy power system by tripping the circuit breaker. For this reason, it is strongly desired that the protective control device respond correctly.

  However, at present, such protection control devices are mainly digital protection control devices equipped with an algorithm for A / D converting system current and voltage information and determining system faults by software processing. For this reason, it is important to verify the operation because it is difficult to see from the outside.

  In the following, an outline of a digital protection control device and problems during operation verification will be described. First, in digital protection control devices for extra highs, the current and voltage information of the power system is sampled at a cycle of 30 degrees electrical angle and 3.75 degrees for high-speed ones, so-called protection relay operation is performed, and system failure Is detected.

  Furthermore, a sequence logic composed of a combination of input conditions such as the state of the device and the state of other devices and some protection relay calculation results is executed, and a final trip command, so-called trip command, is output.

  At this time, the digital type protection control device has a function of displaying the type of system failure and the operated protective relay element as the operation contents on the device screen, and at the same time, notifying a remote person by communication or passing the digital output. .

  In addition, according to the required specifications of the device for each power company, the protection control device may display the circuit breaker trip output or display after confirming that the breaker has actually broken. is there. In the latter case, since it depends on the response speed of the device, it is difficult to test all the cases.

  Advances in digital technology have led to the commercialization of devices that incorporate multiple protective relay elements in one device, operate multiple circuit breakers, and devices with integrated protection and control functions. The logic is becoming complex and enormous.

  In terms of functions, it is equipped with functions that can be carried out over several tens of seconds to several minutes, such as a reclosing circuit and an automatic recovery function, from a function of millisecond order in which a protective relay element operates and trips when a system fault occurs.

  For this reason, it is necessary to verify even complicated and different time order phenomena such as operation of another circuit breaker by a protection control device protecting another line during reclosing.

  The comprehensive operation test of the protection control device is carried out by a simulated power transmission line or a digital simulator at the time of shipment, but the verification facility is large in scale and requires a large number of man-hours for the test. In addition, if there is a function that is combined with one protection control device, even if a logic failure in the sequence logic is suspected at the desk study stage, it may not occur easily in the actual device. Is often difficult.

  In this regard, Patent Document 1 describes that an operation test is performed by installing a computer that generates a test signal outside the protection control device. Patent Document 2 describes a device including a function for generating a test signal inside the system stabilizing device.

JP-A-8-317544 Japanese Patent Laid-Open No. 2002-10493

  As described above, a large-scale test facility such as a simulated transmission line facility or a digital simulator is required to perform a comprehensive test of the protection control device function in the event of a system failure. In this regard, the devices disclosed in Patent Documents 1 and 2 have been improved in that large facilities are not required.

  However, due to the multi-functionalization of protection control devices in recent years, it is necessary to verify various combinations of time orders, such as events in the order of milliseconds, events in the order of minutes, hours, or minutes later. It has become to.

  In addition, the above verification may be difficult to reproduce not only during product development, but also when implementing countermeasures against infrequent phenomena occurring locally, and even if countermeasures are implemented In many cases, confirmation required labor.

  In this regard, the devices disclosed in Patent Documents 1 and 2 only disclose that a test input is prepared and a test is performed, but rarely, as a failure case that actually occurs, for example, from a ground fault to a short circuit. It does not take into account whether the failure is a sudden failure or is a failure across lines. It is only confirmed that it was operated (not) by applying an input, and this also describes how the device should be configured as a test device in the case of complex continuous events occurring in the power system. Absent. In other words, the devices of Patent Documents 1 and 2 are conscious of only a single failure case and do not consider a comprehensive test.

  In view of the above, the present invention enables a comprehensive operation check of sequence logic without special equipment.

In the present invention, a protection relay operation unit that performs a protection relay operation using a digital signal obtained by taking an analog signal of a power system, and a sequence logic unit that determines an output using a plurality of signals from the protection relay operation unit Including an output terminal for outputting the output of the sequence logic unit to the outside, and providing digital signals for the operation test of the first and second arithmetic devices for supplying an operation signal for the circuit breaker of the power system. A test input generation unit that provides a test input in place of the converted signal, and a signal that permits operation of the breaker of the power system is obtained at both of the output terminals of the first and second arithmetic units. In the protection control device with a comprehensive operation test function composed of a trip circuit for executing the operation of the circuit breaker,
In the first and second arithmetic units, an AND circuit for confirming that an operation signal for the circuit breaker of the power system is given from the respective output terminals, and an operating time of the circuit breaker that is activated by the output of the AND circuit Each of the delay timers outputs after the elapse of time, and when an operation test is performed by the test input generation unit, the output of the delay timer is given to the sequence logic unit as an operation signal of the circuit breaker.

  It is preferable to provide a setting unit that provides setting information used for the operation test of the first and second arithmetic devices.

  The setting unit sets and stores the test case selection unit for selecting the test case and the test signal in the test input generation unit at the time of the selected test case as information on the magnitude and phase angle at the elapsed time. 1 setting storage unit.

  The setting unit may include a second setting storage unit that sets the operation time of the circuit breaker simulated by the delay timer for each circuit breaker.

  The setting unit sets and stores the test case selection unit for selecting a test case and the test signal in the test input generation unit at the time of the selected test case as information on the magnitude and phase angle at the elapsed time. It is preferable to include a first setting storage unit and a second setting storage unit that sets the operation time of the circuit breaker simulated by the delay timer for each circuit breaker.

  According to the present invention, even if there is no equipment such as a simulated test power transmission facility, a wide range of tests can be performed easily.

It is a block diagram of the protection control apparatus which mounted the function of this invention. It is the block diagram which showed the relationship between a protection control apparatus and protection object. It is a block diagram inside the process board | substrate inside an apparatus. It is an example of the data which the process in this invention uses. It is an example of the data which sets the response time of a circuit breaker. It is an example of the arithmetic processing flowchart of this invention. It is an example of the human interface screen of a test setting. It is an example of the human interface screen of test data creation. It is an example of the human interface screen which sets the response time of a circuit breaker. It is an example showing the operation result at the time of the progress failure by a comprehensive operation test.

Examples of the present invention will be described below.

  FIG. 2 is a block diagram showing the relationship between the protection control device and the protection target. CT and VT are current transformers and voltage transformers for measuring system current and voltage information, respectively, and outputs from these are taken into the protection control device Ry via the input converter 4.

  The protection control device Ry includes a main detection processing board 5 and a failure detection processing board 6. In general, these processing boards 5 and 6 are divided into a main detection element for performing a protective relay operation and a fault detection element.

  The main detection element in the main detection processing board 5 performs a protective relay operation from its input and gives an output to the output circuit 8 when the sequence logic condition is satisfied. Similarly, also in the failure detection element in the failure detection processing board 6, the protection relay operation is performed from the input, and an output is given to the output circuit 9 when the sequence logic condition is satisfied.

  10 is a trip circuit for the circuit breaker CB. When the judgment in each detection board both detects an accident and the output circuits 8 and 9 output both, the trip circuit for the circuit breaker CB is executed. Eliminate power system accidents. In general, the principle of logic operation for detecting an accident in the main detection element and the failure detection element is different. Further, after recovery from the accident, the protection control device Ry having a reclosing function performs reclosing by the sequence logic and automatically turns on the circuit breaker CB.

  The operation of the circuit breaker CB is fed back to the protection control device Ry as a circuit breaker contact signal 110. The circuit breaker contact signal 110 to be fed back may be an actual contact signal of the circuit breaker CB, or may be replaced with the output of the circuit breaker trip circuit of the protection control device Ry.

  Further, the protection control device Ry of the figure is provided with a human interface processing board 7, and a communication line 120 is installed between the processing boards 5, 6, 7 and the output circuits 8, 9. The data of each part is shared through this communication line 120, and the breaker contact signal 110 and the like are displayed on-site by the human interface processing board 7, notified to a distant place, or sent to another device constituted by a general-purpose PC. Sent.

  In the example shown in the figure, the notification to the distant place is shown by the human interface processing board 7, but there are cases where a dedicated communication board is used or the output is passed to the telecon or the like by a digital output, etc. It depends on.

  FIG. 3 is a block diagram of the inside of the processing board, and the arithmetic unit CPU constituted by a computer is connected to an analog / digital converter A / D, a random access memory RAM, a nonvolatile memory ROM, and an external interface IF via a bus BUS. Has been.

  With this circuit, current and voltage data of the power system input from the analog filter AF via the analog / digital converter A / D is taken into the arithmetic device CPU. The arithmetic device CPU performs the protective relay operation and the sequence operation. The output result is output from the I / O interface IF to the output circuits 8 and 9 in FIG. The RAM is stored as a work in progress. The non-volatile memory ROM stores a set value used for the protective relay operation. Since the program is stored in the nonvolatile memory ROM inside the arithmetic unit CPU, the description is omitted. However, depending on the type of the arithmetic unit CPU, it is necessary to have the program in an external nonvolatile memory ROM.

  FIG. 1 is a block diagram showing the internal functions of the arithmetic unit CPU, which is a main component of the present invention. As shown in FIG. 1, there are an arithmetic unit CPU 1 for the main detection processing board 5 and an arithmetic unit CPU 2 for the accident detection processing board 6 as the arithmetic unit CPU. The plurality of arithmetic units CPU have the same configuration in terms of hardware configuration. In this apparatus, normally, the digital data of the current and voltage of the power system captured at the input terminal 11 is filtered by the digital filter processing unit 16, the accident determination processing is executed by the protective relay calculation unit 17, and the sequence Processing for outputting from the output terminal 19 to the output circuit 8 or 9 in FIG. 2 via the processing unit 18 is continuously performed. Further, the digital input necessary for the processing in the sequence processing unit 18 is taken in from the input terminal 12 and used.

  On the other hand, in the present invention, the input switching circuits 14 and 15 are provided and provided with a function capable of switching to the diagnostic signal from the input generation program 13 instead of the input signal from the input terminal 11 or 12.

  In addition, a signal that reaches the output terminal 19 via the sequence processing unit 18 is provided with a delay timer T that matches the actual response time of the circuit breaker CB, and can be input to the sequence logic. In the example shown in the figure, since the signal of the output terminal 19 of each arithmetic unit CPU is used instead of the contact signal of the circuit breaker CB, the coincidence of the signals of the two sets of output terminals 19 is obtained by the AND circuit 20 and interrupted. The operation command signal of the circuit breaker CB is simulated, and the output of the delay timer T that simulates the time until the operation of the circuit breaker CB is completed is used as the contact signal of the circuit breaker CB.

  In the above description, it is assumed that the breaking operation of the circuit breaker is simulated, but it goes without saying that the closing operation when the breaker is turned on can also be simulated easily.

  FIG. 7 shows a monitor screen implemented as part of the processing of the human interface processing board 7 of FIG. In the example shown in the figure, a setting screen for testing the arithmetic unit CPU in FIG. 1 is displayed. On the test setting screen, a test case selection unit 70, a setting button 73, and an execution button 74 are displayed. In the test case selection section 70, a case button 71 and a comment 72 about the execution contents are further displayed.

  The content of the setting screen in FIG. 7 assumes a so-called progress failure in which a short-circuit failure has occurred 50 ms after the occurrence of a ground fault in Case 1. Case 2 is a progressive failure in which a short-circuit failure occurs 100 ms after the occurrence of a ground fault. Case 3 is a progressive failure in which a short-circuit failure occurs 200 ms after the occurrence of a ground fault. Case 4 is a case where a ground fault has occurred 50 ms after the occurrence of a short-circuit fault.

  For example, here, the case 3 is selected by the case button 71, and the test is performed by pressing the execution button 74.

  When the test button 71 is pressed after selecting the test case button 71, the screen shifts to the test data setting screen shown in FIG. The setting screen of FIG. 8 is a screen for editing and setting of the case 3 selected this time. When the previous page is selected by the page switching unit 85, the screen returns to case 2, and when the next page is selected, the screen shifts to the editing screen of case 4. . A cancel button 87 is pressed to cancel the setting contents, and an end button 86 is pressed to end.

  There are three types of setting contents in this case, one of which is an elapsed time setting unit 81 until the occurrence of a progressive failure, an analog input setting unit 80 at the time of failure as an analog input in FIG. 1, and a failure time as a digital input in FIG. The digital input setting unit 84 of FIG. In the analog input setting unit 80, the failure phase is selected and the failure current and voltage at that time are set by the analog value setting unit 82, the phase angle of the failure current is set by the phase angle setting unit 83, and the digital input is set by the digital input setting unit 84. Determine the type of input.

  FIG. 4 shows analog and digital inputs based on the failure conditions set in this way. From the top, the elapsed time 41 for the case 1, case 2, case 3, and case 4 in FIG. The analog input 42, the second analog input 44, and the digital input 43 are shown. The analog inputs 42 and 44 are indicated by magnitude (gain) and phase angle at each elapsed time. For example, the data in the case of the progressive failure in case 3 selected in FIG. 7 includes the occurrence of a ground fault when the zero phase voltage becomes 30 volts at time 100 ms and the zero phase voltage returns to 0 volts at time 110 ms. At time 310 ms, 200 ms after that, the A-phase current is now 10 amperes, and the A-phase current is returned to 0 amperes at time 360 ms, thereby simulating the occurrence of a short-circuit failure as a progressive failure. Note that an end code is described at the end of the data, and thus the test data ends. The data in the case of the progressive failure in case 3 set in this way is stored in the input generation program 13 in FIG.

  It is also possible to cover the circuit breaker response with the function shown in FIG. 4, but in that case, it is necessary to know the output time of the protective relay operation beforehand. is there.

  In this case, the progress failure data stored in the input generation program 13 is expressed as an analog waveform as a zero-phase voltage a and an A-phase current b in FIG. That is, the zero-phase voltage a is generated from time t1 to t2, and the A-phase current b is generated from time t3 to t4. In this case, according to the setting in FIG. 4, the time between time t1 and t2 is 10 ms, the time between time t2 and t3 is 200 ms, and the time between time t3 and t4 is 50 ms. The magnitudes of the zero-phase voltage a and the A-phase current b are 30 volts and 10 amperes, respectively. In this example, the phase angle is not reflected.

  As is clear from the above description, in the present invention, since the test signal is stored as information on the time, the magnitude and the phase angle at that time, the test of any time period can be performed without consuming a large amount of memory. It becomes possible.

  In addition, a part of the setting screen in FIG. 7 includes a setting screen for the circuit breaker response time in FIG. 9. This is a setting screen for simulating the time required for breaking or turning on the circuit breaker in the delay timer T of FIG. In the setting screen of FIG. 9, the circuit breaker used here is described in the left column. The circuit breaker output position 91, the closing output position 92, the state position 93, the response delay time 94, and the state direction 95 are described for each circuit breaker CB. Can be set.

  FIG. 5 shows circuit breaker information set in this setting screen. Information set in the cutoff output position 91, the closing output position 92, the state position 93, the response delay time 94, and the state direction 95 is shown in FIG. Are recorded as a cutoff output DO51, a closing output DO52, a status input DI53, a response delay time 54, and a capture direction 55.

  Here, the setting of the cutoff output position 91, the closing output position 92, and the state position 93 is nothing but setting the position of the output terminal 19 or the input terminal 12 of FIG. That is, in the example of the circuit breaker CB1, the interruption output is taken in from 1 bit of the first I / O board, the input is taken in from 1 bit of the second I / O board, and the state input is two I / O boards. It means that the 4th bit of the eye is taken in and the delay time is set to 50 ms.

  In addition, FIG. 5 has another arrangement | sequence which produces the response of a circuit breaker so that apparatus response time can be switched. In this case, there is a case where the circuit breaker is turned on with positive logic and a case where the breaker is turned on with positive logic.

  FIG. 6 shows a processing flow chart when the comprehensive test in the apparatus of the present invention described above is performed. In this figure, the flow of normal processing and the flow at the time of conducting a comprehensive test are described.

  First, in step S61, it is determined whether this processing cycle is a normal processing or a comprehensive test is being performed. In the case of normal processing, the input switching circuits 14 and 15 in FIG. 1 are on the input terminals 11 and 12 side, and during the comprehensive test, the input switching circuits 14 and 15 in FIG. On the side.

  In the case of normal processing (the determination result in step S61 is “No”), in step S62, analog data is fetched from the input terminal 11 in FIG. 1, and in step S63, the digital filter processing in the digital filter processing unit 16 in FIG. In step S64, the relay calculation in the protection relay calculation unit 17 in FIG. 1 is performed.

  Subsequently, in step S65, digital data is fetched from the input terminal 12 in FIG. 1, and in step S66, the sequence process in the sequence logic unit 18 in FIG. 1 is performed. In step S67, the DO output process in the output terminal 19 in FIG. To implement.

  The above determination at the time of normal processing is executed by both of the two sets of processing boards 5 and 6 in FIG. 1 and is given to the output circuits 8 and 9 through the communication line 120 in FIG. The CB trip circuit 10 is driven.

  When the comprehensive test is performed (the determination result of step S61 is “Yes”), in step S68, it is confirmed that this is the first time for the comprehensive test. If it is the first time in step S68, a test case is selected. That is, the progress failure of case 3 is selected as the test case on the setting screen of FIG. 7, the elapsed time, the fault current, etc. are set on the setting screen of FIG. 8, and the execution button 74 of FIG. This completes the setting of analog input, and the test starts for the first time.

  In step S70, the confirmation time is checked and the completion of preparation in step S69 is awaited. When preparation is completed by pressing the execution button, input pattern switching processing is performed in step S71. In step S72, analog data is created based on the selected input pattern.

  At this time, the analog data is taken from the input generation program of FIG. 1, the digital filter processing in the digital filter processing unit 16 of FIG. 1 is performed in step S63, and the relay in the protective relay operation unit 17 of FIG. Perform the operation. The analog data in this case is an example of a progressive failure that occurs at different time intervals, such as the zero-phase voltage a and the A-phase current b in FIG.

  Subsequently, various digital information necessary for performing the processing in the sequence processing (step S66) is input. First, in step S73, the digital data 43 of FIG. 4 is captured. The digital data 43 is a signal of “1” and “0” in each processing cycle during the test period, and stores time-series changes.

  Next, in step S74 and step S75, an output condition of the circuit breaker is created. This is because the output from the output terminal 19 of FIG. 1 is obtained from both of the arithmetic units CPU1 and CPU2 and is matched by the AND circuit 20, and then the delay time determined in FIG. 5 (50 ms for CB1). This is contact information at each time until the elapsed time, and is a process for simulating the delay time of the circuit breaker. In step S75, it is confirmed that the AND circuit 20 has made a match. In step S76, it is confirmed that the time of the delay timer T in FIG. 1 has elapsed. In step S77, the digital data 43 in FIG. 4 is stored. Overwrite the contents. Thereby, after this time, it changes into the conditions that the circuit breaker was opened in the next sequence processing.

  In step S66, the sequence processing in the sequence logic unit 18 in FIG. 1 is performed using the digital input obtained as described above. In step S67, the DO output processing in the output terminal 19 in FIG. 1 is performed.

  In the general operation test of the present invention, the analog and digital inputs are prepared as described above, and the soundness in the digital device is checked. However, this can be done by simulating the operation of the circuit breaker CB. It has become possible to test over a wide range of digital devices that did not exist, or with long-term failure events.

  FIG. 10 shows an operation result at the time of a progressive failure according to the comprehensive operation test of the present invention. As an event, a zero-phase voltage a occurred due to a ground fault at time t1, but after a predetermined time (time t2). It is related to the progressive failure that has been recovered and that a short-circuit failure has occurred at time t3 and an A-phase current b has occurred.

  Such a failure example of the transmission line is an event that occurs rarely, but it must be verified that the protection control device Ry operates correctly even in such a case.

  First, in the first half of the ground fault, the ground fault overvoltage relay c on the main detection processing board side operates, but the overcurrent relay d does not operate and the result trip output e is not reached. At this time, the ground fault overvoltage relay f on the accident detection processing board side operates, but the overcurrent relay g does not operate, but the trip output h is obtained by the processing of the sequence processing unit. This trip output is held pending.

  Thereafter, when the ground fault is recovered at time t2, the ground fault overvoltage relays c and f are recovered.

  When a short circuit failure occurs at time t3, the ground fault overvoltage relays c and f do not operate, but the overcurrent relays d and g operate. In the processing of the sequence processing unit in the main detection processing board, the ground fault overvoltage relay c has been recovered, but since the operation content is retained, the overcurrent relay d is in operation. In consideration, the trip output h is obtained by the processing of the sequence processing unit.

  Since both the trip outputs h and e are obtained, the signals at steps S74 and S75 (AND circuit 20 in FIG. 1) in the flowchart of FIG. 6 change to “present”, and the circuit breaker operating condition is satisfied at time t6. After the elapse of t5 time from here, it is simulated that the circuit breaker is broken, and this condition change is fed back to the sequence processing unit. Accordingly, it is recognized that the circuit breaker is interrupted at time t7 within the comprehensive test apparatus.

  As described above, in the present invention, various analog and digital inputs are input and a test is performed, and the response operation of the protection control device can be confirmed by confirming what the result is.

  In particular, it is possible to easily evaluate sequence logic by registering typical operations of system faults in a memory in advance. In other words, it is possible to simulate things such as rare failure with a rare occurrence probability.

  In addition, since the response time of external equipment such as a circuit breaker is taken into consideration, the sequence logic can be evaluated depending on the equipment. As shown in FIG. 5, the response time of the circuit breaker is considerably different for each circuit breaker, but this point can also be simulated with high accuracy.

  As shown in FIG. 4, since the test analog input signal is input by a time setting method that expresses the magnitude and phase of each time, it is possible to perform tests of any time period without consuming a large amount of memory.

  Settings corresponding to external device refractory movements and unexpected delays, which are not possible in normal tests, are possible.

  Since the actual machine is used, functions such as HI screen display and distant display work, which leads to verification of software other than logic circuits.

  Even if there is no special equipment, the present invention provides a comprehensive operation test function by simulating a system failure as a function of the protection control device, and can be easily confirmed by a protection relay calculation and a comprehensive operation of sequence logic.

  In addition, it is possible to comprehensively verify not only the operation of the protection control device when a system fault occurs, but also functions that take a relatively long time such as reclosing and automatic recovery functions. With this function, verification can be performed easily in a short time when the sequence logic is changed. In addition, the function check can be performed without operating the on-site circuit breaker when the software is changed on site.

  According to the present invention, even if there is no equipment such as a simulation test power transmission facility, a wide range of tests can be performed easily, so that high reliability can be obtained as a protection control device, and thus wide use is expected. it can.

11 Input terminal 12 Input terminal 13 Input generation program 14 Input switching circuit 15 Input switching circuit 16 Digital filter processing unit 17 Protection relay operation unit 18 Sequence processing unit 19 Output terminal T Delay timer VT Voltage transformer CT Current transformer CB Breaker 4 Input converter 5 Main detection processing board 6 Fault detection processing board 7 Human interface processing board 8 Main detection output circuit 9 Fault detection output circuit 10 Trip circuit 110 Breaker contact signal 120 Communication line AF Analog filter A / D Analog Digital converter CPU Arithmetic unit RAM Random access memory ROM Non-volatile memory IF Interface circuit 51 Cutoff output DO
52 Input output DO
53 Status input DI
54 Device response time 55 Capture direction 91 Cutoff output position 92 Input / output position 93 Status input position 94 Response delay time 95 Status direction 70 Test case selection section 71 Case button 72 Comment entry field 73 Setting button 74 Execution button 80 Analog input setting section 81 Elapsed time setting unit 82 Analog value setting unit 83 Phase angle setting unit 84 Digital input setting unit 85 Page switching unit 86 End button 87 Cancel button 91 Cutout output position 92 Input output position 93 State input position 94 Response delay time 95 State direction

Claims (5)

A protection relay operation unit that performs a protection relay operation using a signal obtained by digitizing an analog signal of a power system, a sequence logic unit that determines an output using a plurality of signals from the protection relay operation unit, and the sequence A first and second arithmetic unit including an output terminal for outputting the output of the logic unit to the outside, and providing an operation signal for a circuit breaker of the power system; the digital unit for operation test of the first and second arithmetic units A signal permitting the operation of the circuit breaker of the electric power system is obtained at both the test input generation unit for giving a test input instead of the converted signal and the output terminals of the first and second arithmetic units. Sometimes, in the protection control device with a comprehensive operation test function composed of a trip circuit that executes the operation of the circuit breaker,
In each of the first and second arithmetic units, an AND circuit for confirming that an operation signal for a circuit breaker of a power system is given from each of the output terminals; A delay timer that outputs after the operation time of the circuit breaker, and outputs an output of the delay timer to the sequence logic unit as an operation signal of the circuit breaker during an operation test by the test input generation unit. Protection control device with operation test function. In the protection control apparatus with a comprehensive operation test function according to claim 1,
A protection control device with a comprehensive operation test function, comprising: a setting unit that provides setting information used for an operation test of the first and second arithmetic devices. In the protection control device with a comprehensive operation test function according to claim 2,
The setting unit sets and stores a test case selection unit for selecting a test case, and a test signal in the test input generation unit at the time of the selected test case as information on magnitude and phase angle at an elapsed time. A protection control device with a comprehensive operation test function. In the protection control device with a comprehensive operation test function according to claim 2,
The said setting part contains the 2nd setting memory | storage part which sets the operation time of the circuit breaker simulated by the said delay timer for every circuit breaker, The protection control apparatus with a comprehensive operation test function characterized by the above-mentioned. In the protection control device with a comprehensive operation test function according to claim 2,
The setting unit sets and stores a test case selection unit for selecting a test case, and a test signal in the test input generation unit at the time of the selected test case as information on magnitude and phase angle at an elapsed time. A protection control device with a comprehensive operation test function, comprising: a setting storage unit for 1 and a second setting storage unit for setting an operation time of the circuit breaker simulated by the delay timer for each circuit breaker.

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