JP5477588B2 - Semiconductor memory device and method of measuring potential of circuit thereof - Google Patents

Description

  The present invention relates to a semiconductor memory device having a monitor circuit system for monitoring a voltage state of internal wiring of a large-scale semiconductor memory device by a simple method and determining an operation state of an internal circuit, and a method for measuring a potential of the circuit.

  In large-scale semiconductor chips such as memories, the wiring length of the power supply etc. becomes long, and there is a problem that the margin of circuit operation disappears due to voltage drop due to parasitic resistance or rise of the reference voltage (VSS). It was difficult to confirm the failure mode due to the above factors. In addition, when a semiconductor chip is mass-produced, defects in the semiconductor chip may occur due to dust or defects in the process. For example, a wiring or a transistor in the chip may be destroyed and an unexpected current may flow, resulting in a decrease in yield. It was also common to do.

  Therefore, it is necessary to confirm the failure mode of the semiconductor chip by confirming the potential of the internal wiring of the semiconductor chip. However, for that purpose, the passivation film (protective film) of the chip needs to be peeled off, and the voltage is measured by applying a needle such as tungsten to a place to be confirmed. In addition, when a defective product is generated in the semiconductor chip due to a defect in the process, a current flows concentrated on the defective portion. Usually, as a technique for analyzing such breakdown current and leakage current, a technique for confirming a defective portion by performing OBIRCH light emission analysis by laser light irradiation and light emission confirmation by hot electron detection by electron beam irradiation is taken. It was.

JP 2008-171920 A

  However, this method has a problem that requires a large-scale device, takes time, and requires a lot of labor. There is also a problem that the accuracy of measurement is poor. Therefore, according to the present invention, by installing a means for measuring the voltage of the internal circuit as in Patent Document 1 in the semiconductor chip, the voltage state of the internal wiring is monitored by a simple method and the operation state of the internal circuit is determined. It is an object of the present invention to provide a monitor circuit system. It is another object of the present invention to provide a technique that can be used for failure analysis such as yield to analyze a defective portion in a short time.

The present invention, in order to solve the above problems, possess a memory cell array having memory elements arranged in a matrix in a matrix, a branch wiring connected to a ground node or the power supply node, the row and column directions of the memory cell array In a semiconductor memory device in which each memory element in the array is selected by a column decoder and a row decoder, each memory element has a monitor switch having a voltage measurement point connected to a branch wiring connected to a power supply node or a ground node A switch selection signal generating circuit for sequentially opening the gates of the monitor switches by selecting a row in the row direction and the column direction in synchronization with a clock signal, and selecting a column by the column scanning circuit. has, said switch selection signal generating circuit column scanning circuit to select a column to be stopped, the memo by selecting a said column to said column decoder To operate the device, the row scanning circuit semiconductor memory device, wherein a measure of the potential of the voltage measurement point via the monitor switch whose gate is opened by means of opening the gate select lines It is.

  In the semiconductor memory device according to the present invention, the semiconductor memory device further includes a plurality of sense amplifiers that amplify signals read from the memory elements of the memory cell array, and the at least one branch wiring is a ground node or a power supply node of the sense amplifier. This is a semiconductor memory device characterized in that the branch wirings are.

  According to the present invention, in the semiconductor memory device, the at least one branch wiring is a power supply ground node or a power supply power node branch wiring.

  According to the present invention, in the semiconductor memory device described above, the at least one branch wiring is a ground wiring of a control circuit or a branch wiring of a power supply node.

  In the semiconductor memory device according to the present invention, the switch selection signal generation circuit and the monitor switch sequentially transmit the potential of each part of the branch wiring to the monitor pad. This is a method for measuring the potential of the circuit.

  According to the present invention, in a semiconductor memory device, a voltage measurement point of a voltage monitor switch is connected in advance to a position where a potential is to be measured (particularly important as a circuit), and the gate of the monitor switch is opened to set the voltage measurement point. By connecting to the monitor pad PAD, the potential at the voltage measurement point is pulled out from the monitor pad PAD, and the potential at the voltage measurement point at the location to be measured is read. Thereby, there is an effect that a defective portion can be easily specified by observing the internal potential. Therefore, there is an effect that the operation margin can be confirmed at the trial production stage of the semiconductor memory device, and that an analysis when a defect occurs can be facilitated.

It is a block diagram of a circuit of a semiconductor memory device of the present invention. 1 is a circuit diagram of a 1-bit memory circuit of a semiconductor memory device of the present invention. It is a circuit diagram of a 16-bit memory circuit of the semiconductor memory device of the present invention. FIG. 3 is an overall layout diagram of the overall layout and power supply wiring configuration in a semiconductor chip of the semiconductor memory device of the present invention. It is a circuit diagram of a sense amplifier of the semiconductor memory device of the present invention. It is a circuit diagram of the REF circuit of the sense amplifier of the semiconductor memory device of the present invention. It is a circuit diagram of a monitor circuit of a 1st embodiment of the present invention. 1 is an overall layout diagram of a switch selection signal generation circuit according to a first embodiment of the present invention. FIG. 3 is an overall layout diagram showing installation positions of monitoring switches on branch wirings of a ground node VSS in the overall layout of the semiconductor chip of the semiconductor memory device according to the first embodiment of the present invention. 1 is a circuit diagram centering on a memory cell array portion according to a first embodiment of the present invention; FIG. (A) It is a graph showing the magnitude | size of the electric potential of each position of the branch wiring VSSh of the ground node VSS along the row line node WLh of the 1st Embodiment of this invention. (B) It is a graph showing the magnitude | size of the electric potential of the edge part of each branch wiring of the ground node VSS of the 1st Embodiment of this invention. It is a circuit diagram which shows the installation position to branch wiring VSSr of the switch for a monitor of the 2nd Embodiment of this invention. It is a graph showing the magnitude | size of the electric potential of each position of the branch wiring VSSr of the 2nd Embodiment of this invention. FIG. 10 is an overall layout diagram showing installation positions of monitoring switches on a branch wiring of a ground node VSS in an overall layout of a semiconductor chip of a semiconductor memory device according to a third embodiment of the present invention. It is a circuit diagram of the sense amplifier of the 3rd Embodiment of this invention.

<First Embodiment>
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram of a circuit of a semiconductor memory device 1 of a mask ROM, which is a nonvolatile semiconductor memory device according to an embodiment of the present invention, as a typical example of a memory.

  In this embodiment, the semiconductor memory device 1 includes a memory cell array 100, a row decoder 200, a column decoder 300, a column gate 400, a sense amplifier 500, a control circuit 600, an output buffer 700, and an address input circuit, as shown in FIG. It is comprised from 800.

  The control circuit 600 temporarily stores a control signal input from a host such as a connected microcomputer, and controls operation logic. The output buffer 700 outputs a data signal read from the memory cell array 100. The address input circuit 800 temporarily stores an address input from the outside of the semiconductor memory device 1, and the row decoder 200 and the column decoder 300 convert the address, and the memory element Mhk (h = 0) of the memory cell array 100. ˜m, k = 0 to n), a row selection signal and a column selection signal are generated.

  FIG. 2 shows an example of a circuit diagram of a 1-bit memory circuit when the semiconductor memory device 1 of FIG. 1 is a mask ROM. As shown in the circuit diagram of FIG. 2, in the memory cell array 100, memory elements M00 to M23, which are the smallest storage units, are regularly arranged in a matrix form vertically and horizontally in the area of the integrated circuit chip of the semiconductor memory device 1. The row line node WL0 of the row decoder 200 is connected to the gates of the memory elements M00 to M03 arranged in the row direction, and is selected by outputting a row selection signal. A row line node WL1 is commonly connected to the gates of the memory elements M10 to M13 arranged in the row direction, and a row line node WL2 is commonly connected to the gates of the memory elements M20 to M23. The branch wiring VSS0 of the ground node VSS is connected in common to the source terminals of the memory elements M00 to M03, and the branch wiring VSS1 of the ground node VSS is connected in common to the source terminals of the memory elements M10 to M13. The branch wiring VSS2 of the ground node VSS is connected in common to the source terminals of M20 to M23. For each memory element Mhk (h = 0 to 2, k = 0 to 3), a monitor switch S0, S1, Install S2 and other monitoring switches.

  The column line node BIT0 of the column gate 400 is connected in common to the drains of the memory elements Mh0 (h = 0 to 2) arranged in the column direction. Column line node BIT0 is connected to the source terminal of column select transistor CG0 of column gate 400. A column selection node COL0 of the column decoder 300 is connected to the gate of the column selection transistor CG0. The gate of the reference column selection transistor RF0 is also connected to the column selection node COL0. A column selection signal is transmitted from the column decoder 300 to the column selection node COL0 to drive the column selection transistor CG0 and the reference column selection transistor RF0 of the column gate 400. The drains of the column selection transistors CG 0 to CG 3 of the column gate 400 are connected to the common node COM of the sense amplifier 500. The drains of the reference column selection transistors RF0 to RF3 of the column gate 400 are connected to the reference common node REC of the sense amplifier 500. The drain terminals of the reference transistor Tr9 are connected to the source terminals of the reference column selection transistors RF0 to RF3, and the source terminal of the reference transistor Tr9 is connected to the branch line VSSr of the ground node VSS. The reference transistor Tr9 is controlled by connecting the REF node of the VREF circuit 507 to its gate terminal.

  The column line node BIT1 of the column gate 400 is commonly connected to the drains of the memory elements Mh1 (h = 0 to 2) arranged in the column direction, and the column line node BIT1 is connected to the column selection node COL1 of the column decoder 300. Connected to the source terminal of the column select transistor CG1 to which the gate is connected. The column line node BIT2 of the column gate 400 is commonly connected to the drains of the memory elements Mh2 (h = 0 to 2) arranged in the column direction, and the column line node BIT2 is connected to the column selection node COL2 of the column decoder 300. Is connected to the source terminal of the column selection transistor CG2 whose gate is connected to the source terminal. The drains of the memory elements Mh3 (h = 0 to 2) are commonly connected to the column line node BIT3 of the column gate 400, and the column line node BIT3 is connected to the column selection node COL3 of the column decoder 300. Connected to the source terminal of the column select transistor CG3.

  FIG. 3 shows a specific example of a 16-bit memory circuit of the mask ROM circuit. Since the semiconductor memory device 1 has a 16-bit configuration (having 16 output terminals Dout), the memory cell array 100 is divided into 16 blocks from 100-0 to 100-15. The common node COM0 is a 0th bit common node and is commonly connected to the 0th bit sense amplifier 500-0 and the column selection transistors CG0-0 to CGn-0 of the column gate 400. The common node COM15 is a 15th bit common node and is commonly connected to the 15th bit sense amplifier 500-15 and the column selection transistors CG0-15 to CGn-15 of the column gate 400. The source terminal of the 0-bit column selection transistor CGk-0 (k = 0 to n) is connected to the column line node BITk-0, and the source terminal of the 15-bit column selection transistor CGk-15 is the column line node BITk-. 15 is connected.

  Memory elements M00-0 to Mmn-0 are arranged in a matrix of (m + 1) × (n + 1) in the 0th bit memory cell array 100-0. Memory elements M00-15 to Mmn-15 are arranged in a matrix of (m + 1) × (n + 1) in the 15th bit memory cell array 100-15. The row line node WLh of the row decoder 200 is connected to the gate terminals of the memory devices Mh0-0 (h = 0 to m) to Mhn-0 arranged in the row direction in the 0th bit memory cell array 100-0. The column line node BITk-0 of the column gate 400 is connected in common to the drain terminals of the memory elements M0k-0 (k = 0 to n) to Mmk-0 arranged in the column direction. The source terminals of the memory elements are all connected in common to the ground node VSS (GND). However, the source terminals of the memory elements M00-0 to M0n-0 in the row direction are commonly connected to the branch wiring VSS0 of the ground node VSS, and the source terminals of the memory elements Mm0-0 to Mmn-0 in the row direction are commonly used. Are connected to the branch wiring VSSm of the ground node VSS.

An output signal is output from the output terminal Dout0 to the outside of the chip from the sense amplifier 500-0 for signal amplification of the 0th bit memory cell array 100-0 via the output buffer circuit 700. The memory cells cell arrays 100-1 to 100-15 for the first bit to the 15th bit have the same configuration, and output signals are output from the output terminals Dout1 to Dout15. That is, the memory elements for the 15th bit connect the source terminals of the memory elements M00-15 to M0n-15 in the row direction in common to the branch wiring VSS0 of the ground node VSS and connect the memory elements Mm0-15 in the row direction. The source terminal of Mmn-15 is commonly connected to the branch wiring VSSm of the ground node VSS. Here, the memory elements selected by the same row line node WLh in the 0th to 15th bit memory elements are divided into a plurality of groups, and each group is connected to one branch wiring VSSm. May be.

  Reference numerals 200-0 to 200-m denote row decoders, each of which includes a NAND circuit 201 to which a row address is input from the address input circuit 800 and an inverter 202 serving as a buffer, and outputs an output to the row line node WLh. Circuit. Row line nodes of the row decoder 200 are WL0 to WLm, and a row of the memory elements Mhk arranged in the memory cell array 100 is selected.

  Reference numerals 300-0 to 300-n denote column decoders, each of which includes a NAND circuit 301 to which a column address is input from an address input circuit 800 and an inverter 302 as a buffer, and outputs an output column selection signal as a column line. A circuit for outputting to the node COLk is included. A column selection signal is output from the column decoder 300 to the column selection node COLk, and the column selection transistors CGk-0 to CGk-n of the column gate 400 connected to the gate of the column selection node COLk are opened. When the gate of the 0th bit column selection transistor CGk-0 is opened, the common node COM0 of the sense amplifier 500-0 is connected to the column line node BITk-0 via the column selection transistor CGk-0. As a result, the column of the memory elements Mhk arranged in the memory cell array 100-0 is selected. Thus, a row is selected by the row decoder 200 and a column is selected by the column decoder 300, whereby the memory element Mhk is selected.

  FIG. 4 shows the overall layout and power supply wiring connections in the semiconductor chip of the integrated circuit of the semiconductor memory device 1. In the memory cell array 100, the sense amplifier 500, and the control circuit 600, the power supply node VCC is connected to the normal power supply pad VCC-P, and the ground node VSS is connected to the ground pad VSS-P. The ground node VSS is an area of the memory cell array 100, and branch lines VSS0, VSS1, VSS2,..., VSS (m−1), VSSm, VSS (m + 1), VSS (m + 2), VSS (m + 3),. Branches to VSS (2m) and VSS (2m + 1). On the other hand, since a large amount of large current and transient current flow through the output circuit 700 and the power supply circuit (charge pump circuit) 900, a dedicated power supply wiring separated from the normal power supply wiring is formed. That is, the output power supply node VCCO and the output ground node VSSO for the output circuit 700 and the power supply power node VCCP and the power supply ground node VSSP of the power supply circuit (charge pump circuit) 900 are separated from the normal power supply wiring. A dedicated power supply wiring is formed. For the output circuit 700, the output power supply node VCCO is wired from the output power supply pad VCCO-P, and the output ground pad VSSO-P (for output circuit) is connected to the output ground node VSSO. Wiring. Further, for the power supply circuit 900, a power supply power node VCCP is wired from the power supply power pad VCCP-P, and a power supply ground node VSSP is wired from the power supply ground pad VSSP-P (for power supply circuit). Thus, wiring is performed so that the influence of the power supply noise of the output circuit 700 and the power supply circuit (charge pump circuit) 900 does not affect an important analog circuit such as the sense amplifier 500.

(Sense amplifier)
FIG. 5 is an example of a circuit of the sense amplifier 500 in the semiconductor memory device 1. The sense amplifier 500 is a circuit that is most susceptible to the influence of power supply noise or voltage level. This sense amplifier 500 has a load circuit 502 composed of P-channel type load transistors Tr1 and Tr2, and also has an N-channel load circuit having a source terminal connected to the common node COM and a drain terminal connected to the drain terminal of the load transistor Tr2. A bias transistor Tr3 is included. In order to increase the speed of the bias transistor Tr3, a feedback bias circuit 501 including a P-channel transistor Tr4 and an N-channel transistor Tr5 is provided. The node of the connection point between the drain terminal of the transistor Tr4 and the drain terminal of the transistor Tr5 of the feedback bias circuit 501 is connected to the gate terminal of the bias transistor Tr3. Further, the source terminal of the transistor Tr5 is connected to the ground node VSS.

  The source terminal of the bias transistor Tr3 of the sense amplifier 500 is connected to the common node COM. The common node COM is commonly connected to the drain terminals of the column selection transistors CG0 to CGn of the column gate 400, as shown in FIGS. FIG. 5 shows one column selection transistor CGk typified by those column selection transistors. As shown in FIGS. 2 and 3, the gate terminal of the column selection transistor CGk is connected to the column selection node COLk, and the source terminal of the column selection transistor CGk is connected to the column line node BITk.

  The column line node BITk is commonly connected to the drain terminals of the memory elements M0k to Mmk of the memory cell array 100 as shown in FIGS. FIG. 5 shows one memory element Mhk typified by those memory elements. As shown in FIGS. 2 and 3, the gate terminal of the memory element Mhk is connected to the row line node WLh of the row decoder 200, and the source terminal of the memory element Mhk is connected to the ground node VSS. Here, as shown in FIGS. 2 and 3, the memory elements Mh0 to Mhn are connected to the ground node VSSh forming a common branch line. In other words, the ground node VSS has m + 1 branch wiring ground nodes from the ground node VSS0 to the ground node VSSm that form the branch wiring. Then, the memory elements M00 to M0n are connected to the ground node VSS0 of one branch wiring, and the memory elements Mm0 to Mmn are connected to the ground node VSSm of one branch wiring. However, when the memory cell array 100 is divided into left and right blocks as shown in FIG. 4, the ground node VSSh of one branch wiring intersects with the wiring of the ground node VSS which is the main trunk at the center and is connected at the center. Therefore, the main ground node VSS is divided into two left and right branch lines VSSh.

(Differential sense amplifier)
As shown in FIG. 5, the differential sense amplifier 503, which is the determination part of the circuit of the sense amplifier 500, is configured by a current mirror circuit. A signal from the memory element Mhk is input to one terminal of the differential input of the differential sense amplifier 503 via the bias transistor Tr3. That is, the column line node BITk connected to the drain terminal of the memory element Mhk whose gate is opened by connecting the row line node WLh to which the row selection signal is transmitted from the row decoder 200 to the gate is connected to the column from the column decoder 300. It is connected to the common node COM via the column selection transistor CGk that is selected by the selection signal and whose gate is opened. The common node COM is connected to one terminal of the differential input of the differential sense amplifier 503 via the bias transistor Tr3. Specifically, the drain terminal of the bias transistor Tr3, the source terminal of the load transistor Tr2 of the load circuit 502, and one differential input terminal of the differential sense amplifier 503 are connected to the same node, and the drain terminal of the bias transistor Tr3. The potential of the drain of the memory element Mhk is transmitted to one differential input terminal of the differential sense amplifier 503. The other differential input terminal of the differential sense amplifier 503 is connected to the reference terminal to which the source terminal of the reference load circuit 505 composed of the transistors Tr6 and Tr7 in the reference circuit 504 and the drain terminal of the reference bias transistor Tr8 are connected. A potential node REP is connected.

(Reference circuit)
The reference circuit 504 includes a reference feedback bias circuit 506 corresponding to the feedback bias circuit 501, a reference load circuit 505 corresponding to the load circuit 502, a reference bias transistor Tr8 corresponding to the bias transistor Tr3, and a memory element. A reference transistor Tr9, which is an element equivalent to Mhk, and a reference column selection transistor RFk corresponding to the column selection transistor CGk, are configured with a feedback bias circuit 501, a load circuit 502, a bias transistor Tr3, a column selection transistor CGk, and a memory element. The circuit configuration is symmetrical to the circuit configured by Mhk, the drain terminal of the reference load circuit 505 and the drain terminal of the reference bias transistor Tr8. A reference potential node REP connecting, adding a potential corresponding to the potential applied to the node of the differential input terminals of the memory device Mhk side. The reference column selection transistors RFk are a plurality of transistors corresponding to a plurality of column selection transistors CGk, such as the reference column selection transistors RF0 to RF3 corresponding to the column selection transistors CG0 to CG3 in FIG. The REF node of the VREF circuit 507 is connected to the gate terminal of the reference transistor Tr9. As a signal applied to the REF node, a VREF circuit 507 applies a reference transistor selection signal corresponding to a row selection signal applied to the row line node WLh connected to the gate of the memory element Mhk.

(VREF circuit)
A VREF circuit 507 is shown in FIG. The VREF circuit 507 is a feedback type comprising a transistor T1 having the same size as the memory element Mhk, a transistor T2 corresponding to the column selection transistor CGk, and transistors T6 and T7 corresponding to the feedback type bias circuit 501 of the sense amplifier circuit 500. A bias circuit 508, a load circuit 509 including transistors T4 and T5 corresponding to the load circuit 502, a transistor T3 corresponding to the bias transistor Tr3, and transistors T8, T9, and T10. The source terminal of the transistor T2 is connected to the drain of the transistor T1, and the source terminal of the transistor T3 and the feedback bias circuit 508 are connected to the drain of the transistor T2. Then, the gate terminal of the transistor T9 is connected to a node where the drain terminal of the transistor T3 and the drain terminal of the load circuit 509 are connected. The drain terminal of the transistor T8 is connected to the source terminal of the transistor T9, and the drain terminal and the gate terminal of the transistor T10 are connected to the drain terminal of the transistor T9 and the REF node. A reference transistor selection signal is output from the REF node toward the gate terminal of the reference transistor Tr9 of the reference circuit 504.

  The VREF circuit 507 makes the transistor T1 the same size as the memory element Mhk, thereby making the current flowing through the transistor T1 the same as the current Icell flowing through the memory element Mhk. Further, by making the size of the transistor T9 the same as that of the transistor T4, the current flowing through the transistor T9 is set to the same size as the current Icell flowing through the transistor T4. By making the length twice that of the reference transistor Tr9, the current flowing through the reference transistor Tr9 is reduced to one half of the current Icell flowing through the transistor T10.

(Sense amplifier operation)
As shown in FIG. 5, in the sense amplifier 500, the differential sense amplifier 503 generates a signal of the reference potential node REP generated by the reference circuit 504 and a signal from the memory element Mhk via the column selection transistor CGk, the bias transistor Tr3, and the like. Are read out from the memory cell array 100 by accurately detecting whether the memory element Mhk is charged or discharged.

The operation of the sense amplifier 500 will be described in detail below. The sense amplifier 500 first charges the column line node BITk from the power supply node VCC via the load circuit 502, the bias transistor Tr3, and the column selection transistor CGk whose gate is opened. When the column line node BITk is charged by about 1V, the output of the feedback bias circuit 501 becomes LOW, the charging of the column line node BITk is stopped, and the column line node BITk is clamped to approximately 1V. The reference circuit 504 side performs the same operation. However, since the current of the reference transistor Tr9 is set to be smaller than that of the memory element Mhk, the output of the sense amplifier 500 becomes “1” when the current flows through the memory element Mhk. When the memory element Mhk has a smaller current (does not flow), the output of the sense amplifier 500 becomes “0”, and a very small current can be detected.

  The sense amplifier 500 is characterized by its high speed, but since it uses the feedback bias circuit 501, it is sensitive to slight fluctuations in the power supply, and its operating point changes due to a small voltage drop. There are drawbacks. Although the semiconductor memory device 1 is designed to reduce the potential change as much as possible by wiring the power supply as shown in FIG. 4, in reality, the voltage changes due to various factors, and the operation margin is reduced. ing. However, since the power supply voltage of the semiconductor memory device 1 is low and the change in the power supply voltage is also a minute voltage, it has conventionally been difficult to analyze the change in the power supply voltage.

(Monitor circuit)
In order to solve this problem, in this embodiment, the monitor circuit shown in FIG. A switch selection circuit SE is installed for each memory element Mhk (h = 0 to m, k = 0 to n), and switch selection circuits SE00 to SEmn are installed in the semiconductor memory device 1. Then, as shown in FIG. 8, the row selection line 103 of the row scanning circuit 102 of the switch selection signal generation circuit 110 is wired along the row line node WLh (h = 0 to m) and arranged in the row direction. The switch selection circuit SEhk at the position of the memory element Mhk to be connected is connected. The column selection line 105 of the column scanning circuit 104 is wired in parallel to the wiring of the column line nodes corresponding to the column line nodes BITk-0 to BITk-15, and the column selection line 105 is arranged in the column direction. Is connected to the switch selection circuit SEhk installed at the position of the memory element Mhk arranged in the array. Here, in the case of the 16-bit semiconductor memory device 1, the switch selection circuit SEhk is installed by the number of memory elements Mhk, which is 16 times the number of memory addresses m × n. The case of the 1-bit semiconductor memory device 1 has been described.

  In addition, as shown in FIG. 7, the gates of the monitor switches S0 to Su are opened and closed by the signals of the two output terminals of the switch selection circuits SE00 to SEmn, as shown in FIG. The voltage measuring terminal of each monitor switch is connected to the position of the branch wiring of the ground node VSS to which the source terminal of the memory element Mhk is connected. In this way, the gate of the monitor switch for each memory element Mhk is opened by the switch selection circuit SEhk for each memory element Mhk, whereby the potential of the circuit for each memory element Mhk is transmitted to the monitor pad PAD. One switch selection circuit SEhk can be configured to be connected to a plurality of monitoring switches. In this case, the plurality of monitoring switches simultaneously transmit a plurality of voltage signals to a plurality of monitoring pads PAD.

  As shown in FIG. 7, each of the monitoring switches S0 to Su is composed of an N-channel transistor and a P-channel transistor. The switch selection signal generation circuit 110 includes a timing generator 101 that is synchronized with the CLK signal, and a row scanning circuit 102 and a column scanning circuit 104 that are driven by the timing generator 101 and include a counter circuit and a shift register. Accordingly, the timing generator 101 drives the row scanning circuit 102 and the column scanning circuit 104 of the switch selection signal generation circuit 110 in synchronization with the CLK signal, and the row scanning circuit 102 sequentially arranges the monitor switches on the row selection line 103. The column scanning circuit 104 transmits a readout pulse for sequentially selecting the monitor switch array column to the column selection line 105, and selects the monitor switch array row and column. To do. The row selection line 103 and the column selection line 105 that intersect at the position of the memory element Mhk are connected to the two input terminals of the switch selection circuit SEhk, which are connected to the AND gate 106 and the NAND gate 107 of the switch selection circuit SEhk. Connect to each of the two input terminals.

From the output terminals of the AND gate 106 and the NAND gate 107 of the switch selection circuit SEhk, an N-channel transistor signal and a P-channel transistor signal of the monitor switch are generated by inverting the high level and the low level. Each signal is input to the gate electrode of the N-channel transistor and the gate electrode of the P-channel transistor of the monitor switch. Thereby, the switch selection circuit SEhk whose arrangement position is selected by the read pulse of the row scanning circuit 102 and the column scanning circuit 104 opens the gate of the monitor switch for the memory element Mhk, and the memory element Mhk to which the voltage measurement terminal is connected. The circuit potential is transmitted to the monitor pad PAD. Thus, by transmitting the potential at the measurement point of the monitor switch to the monitor pad PAD, the potential at each measurement point of the monitor switch can be sequentially measured in synchronization with the CLK signal.

  As shown in FIG. 9, branch wirings VSS0, VSS1, VSS2,..., VSS (m−1), VSSm, VSS (m + 1), VSS (m + 2), VSS (m + 3) are included in the branch wiring of the ground node VSS. , ..., VSS (2m), VSS (2m + 1), and the like. In FIG. 9, monitoring switches S0 to Sm are installed at the end points of the left branch wiring of the main node of the ground node VSS of the memory cell array 100. Similarly, monitoring switches S (m + 1) to S (2m + 1) are installed at the end of the right branch wiring of the main trunk of the ground node VSS.

(Search for defective elements)
FIG. 10 shows a circuit diagram centered on the memory cell array 100 of the semiconductor memory device 1. Since the wiring of the ground node VSS extending in the vertical direction from the ground pad VSS-P of the semiconductor memory device 1 is the main wiring, the wiring resistance is set to be as low as possible by setting the wiring width to be large. In FIG. 10, circuits such as the row decoder 200 and the column decoder 300 are omitted in order to pay attention to the arrangement and wiring position of the monitor switch S (k) near the source terminal of the memory element Mhk of the memory cell array 100. The memory cell array 100 includes m rows × n columns of memory elements Mhk. In FIG. 10, the row h and the row h + 1 selected by the row line nodes WLh and WL (h + 1) are shown, and the column line node BIT0 is shown. , BIT (k−1), BIT (k), BIT (k + 1), BIT (n), 0th column, (k−1) th column, kth column, (k + 1) th column, nth column Showing eyes. The source terminals of the memory elements Mh0 to Mhn selected at the row line node WLh are commonly connected to the branch wiring VSSh, and the branch wiring VSSh is connected to the vertical wiring of the ground node VSS. The source terminals of the memory elements M (h + 1) 0 to M (h + 1) n selected by the row line node WL (h + 1) are commonly connected to the branch line VSS (h + 1), and the branch line VSS (h + 1) is connected to the ground node VSS. Connect to the vertical wiring. The vertical wiring of the ground node VSS is formed with a large width to obtain a large current capacity, and the resistance value is reduced.

  Here, in the switch selection signal generation circuit 110 in FIG. 8, only the column selection line 105 that connects the column scanning circuit 104 to the switch selection circuit SEh0 (h = 0 to m) at the position of the column line node BIT0 is selected. And only the row scanning circuit 102 is scanned. On the other hand, in synchronism with the operation of the timing generator 101 of the switch selection signal generation circuit 110, the column decoder 300 for selecting a column of the memory cell array 100 is operated instead of the column scanning circuit 104, and the column line node BITk (k = 0 to n) are selected sequentially.

In a normal memory read operation of a semiconductor memory device, memory elements Mhk (h = 0 to m, k = 0 to n) are read from the memory cell array 100 as follows. That is, a column selection signal is transmitted from the column decoder 300 to the column selection node COLk (k = 0 to n) of the memory cell array 100, and the column selection transistor CGk (k = 0 to 0) whose gate terminal is connected to the column selection node COLk. n), the gate of the column selection transistor CGk is opened, and the common node COM of the sense amplifier 500 is connected to the column line node BIT (k) (k = 0 to n) via the column selection transistor CGk. When a row is selected by transmitting a row selection signal to the row line node WLh (h = 0 to m), a row and a column are selected, and the memory element Mhk is selected. If the storage data of the selected memory element Mhk is “1”, the memory element Mhk is turned on, and the column selection transistor whose gate is opened and the column line node BIT (k) from the common node COM of the sense amplifier 500. , Current flows from the memory element Mhk to the ground node VSS, and current flows out from the ground pad VSS-P of the ground node VSS. If the data stored in the memory element Mhk is “0”, Mhk is turned off and no current flows. This current is detected by the sense amplifier 500 connected to the column line node BIT (k) via the column selection transistor CGk at the common node COM, and data is determined.

  Here, when one memory element Mhk is destroyed and, for example, the branch line VSSh of the column line node BIT (k) and the ground node VSS is short-circuited, the row selection signal is not transmitted to the row line node WLk. However, a current flows from the column line node BIT (k) to the branch wiring VSSh of the ground node VSS. In the case of such a failure, only one memory element Mhk is destroyed, but when the column selection node COLk is selected by the column decoder 300, the common node COM of the sense amplifier 500 becomes the column line node. When connected to BIT (k), no matter which row line node WL is selected by the row decoder 200, a current always flows through the common node COM of the sense amplifier 500. Therefore, in the conventional semiconductor memory device 1, it is difficult to specify the position of which row of the memory element Mhk is a defective memory element Mhk.

  The present embodiment solves this problem as follows. In the switch selection signal generation circuit 110 of FIG. 8, first, only the column selection line 105 connected to the switch selection circuit SEh0 (h = 0 to m) at the position of the column line node BIT0 is selected. Then, the column decoder 300 of the semiconductor memory device 1 is operated to sequentially select the column selection nodes COLk (k = 0 to n), thereby connecting the column line node BITk to the common node COMk of the sense amplifier 500. In synchronization with the operation of the column decoder 300, that is, while one column selection node COLk is selected, the timing generator 101 scans the row scanning circuit 102 and switches the selection of the row selection line 103. Thereby, the potential of each branch wiring of the ground node VSS can be measured, and the branch wiring VSSh of the ground node VSS in which the damaged memory element Mhk is short-circuited can be found.

  With reference to FIG. 11, a method for specifying a defective memory element in the memory cell array 100 of the semiconductor memory device 1 of the present embodiment will be specifically described. FIG. 11A shows a graph representing the magnitude of the potential at each position of the branch wiring VSSh of the ground node VSS along the row line node WLh. The voltage measurement point of the monitor switch Sh is connected to the position (0) at the end of the branch wiring VSSh. In FIG. 11, (k−1) represents the position of the memory element Mh (k−1), (k) represents the position of the memory element Mhk, (k + 1) represents the position of the memory element Mh (k + 1), and VSS-P is Indicates the position of the ground pad VSS-P. In FIG. 11 (a), the solid line indicates the potential at each position of the branch wiring of the ground node VSS of the memory elements Mh0 to Mhn in the h-th row in which the memory element Mhk is destroyed and an excessive current flows. The potentials at the respective positions of the branch wirings of the ground nodes VSS of the memory elements M (h + 1) 0 to M (h + 1) n in the normal (h + 1) row where no excessive current flows are shown.

The branch wiring VSSh (h = 0 to m) of the ground node VSS connected to the source terminal of the memory element arranged in the row direction selected by the row line node WLh (h = 0 to m) of the memory cell array 100 is a semiconductor. Since it is provided in the area of the memory cell array 100 in the integrated circuit chip of the memory device 1, the resistance generated by the wiring has a value that cannot be ignored because the wiring width cannot be increased so much. Therefore, when one memory element Mhk is destroyed and an excessive current flows, the branch wiring VSSh is directed from the position of the branch wiring VSSh to which the source terminal of the destroyed memory element Mhk is connected to the ground pad VSS-P. Since an excessive current flows, a steep potential gradient is generated from the position (k) of the destroyed memory element Mhk toward the ground pad VSS-P. On the other hand, since no current flows from the position (k) of the destroyed memory element Mhk to the position of the monitor switch Sh at the end (left end) of the wiring opposite to the ground pad VSS-P, the potential There is no gradient, and the potential at the position of the monitor switch Sh at the end of the branch wiring VSSh is the position (k) of the branch wiring VSSh connected to the destroyed memory element Mhk.
It becomes the same size as the potential.

  Therefore, the column scanning circuit 104 of the switch selection signal generation circuit 110 in FIG. 8 selects only the column selection line 105 connected to the switch selection circuit SEh0 (h = 0 to m) at the position of the column line node BIT0. The monitoring switches S0 to Sm in FIG. 9 connected to the selection line 105 are selected. These monitoring switches S0 to Sm are for measuring a potential by connecting a voltage measurement point to the end Sh of the branch wiring VSSh parallel to the row line node WLh. Then, the column decoder 300 and the column gate 400 are operated in synchronization with the operation of the timing generator 101 of the switch selection signal generation circuit 110 while the row scanning circuit 102 is operated to scan the row, and the column of the memory cell array 100 is operated. A voltage is sequentially applied to the line node BITk (k = 0 to n).

  When a voltage is applied to the column line node BITk to which one damaged memory element Mhk of the memory cell array 100 is connected, the voltage transmitted from the monitor switches S0 to Sm of each row selected by the row scanning circuit 102 to the monitor pad PAD Is shown in FIG. When the memory element Mhk is destroyed and an excessive current flows, when a voltage is applied to the column line node BITk of the memory cell array 100, the potential at the end of the branch wiring VSSh connected to the destroyed memory element Mhk rises. Other than that, since the potential at the end of the branch wiring connected only to the normal memory element is low, the branch wiring connected to the defective memory element can be discriminated. In this way, the use of the switch selection signal generation circuit 110 has an effect that the damaged memory element Mhk can be detected.

  If the memory cell array 100 is divided into the left and right regions of the main node of the ground node VSS as shown in FIG. 9, the column scanning circuit 104 selects the leftmost column selection line 105 in FIG. 9, the column scanning circuit 104 is made to select the column selection line 105 at the right end of FIG. 9, and the column line node BITk (k = 0 to 0) of the right side memory cell array 100 is used by using the monitor switch at the right end of the branch wiring. While the voltage is sequentially applied to n), the row scanning circuit 102 opens the gate of the monitor switch by opening the gate of the monitor switch and transmits it to the monitor pad PAD as shown in FIG. 11B. Measure the voltage at

  In this embodiment, in order to check whether or not the memory element Mhk of the memory cell array 100 is destroyed, the column decoder 300 sequentially transfers to the column selection node COLk (k = 0 to n) and the kth column (k = 0 to n). A column selection signal for selecting is transmitted. On the other hand, the selection of the h-th row of the memory element Mhk to be inspected is performed by sequentially transmitting a read pulse from the row scanning circuit 102 of the switch selection signal generating circuit 110 to the switch selection circuit SEh0 (h = 0 to m). By selecting the switch Sh and opening its gate, the branch wiring of the h-th row of the ground node VSS of the memory cell array 100 is selected, and the end of the branch wiring is connected to the monitoring pad PAD in the order of the branch wiring arrangement. Connect to. In this way, the potential of the end of the branch wiring VSSh of the ground node VSS selected in order is connected to the monitoring pad PAD with the monitoring switch Sh and the potential of the monitoring pad is measured as shown in FIG. There is an effect that the position of the damaged memory element Mhk can be easily specified.

(Modification 1)
Below, the modification 1 of 1st Embodiment is demonstrated. As shown in FIG. 3, 16-bit column line nodes BITk-0 to BITk-15 are simultaneously selected and operated for one column selection node COLk (k = 0 to n) as branch lines of the ground node VSS. In this case, even if the row number h and the column number k of the damaged memory element can be specified by the method of the first embodiment, there are 16 damaged candidate memory elements from Mhk-0 to Mhk-15. Furthermore, it is necessary to identify one damaged memory element from the 16 pieces.

  Therefore, in the first modification, the column selection node COLk of the column k of the damaged memory element specified by the method of the first embodiment is selected, and the voltage is applied to the 16 column line nodes BITk-0 to BITk-15. Add. Then, the row scanning circuit of the switch selection signal generation circuit 110 in FIG. 8 fixes and selects the h-th row of the damaged memory element specified by the method of the first embodiment. Next, column scanning is performed by the column scanning circuit 104, whereby the potentials at the voltage measurement points in the entire area of the branch wiring are drawn out by the monitor switch, and a potential distribution graph is obtained as shown in FIG. . Thereby, the position of the defective cell (damaged memory element Mhk) can be specified. Thus, according to the first modification, the voltage measurement point of the branch wiring of the ground node VSS in the h-th row of the memory element is connected to the monitoring pad PAD in the order arranged in the branch wiring, thereby measuring the potential. There is an effect that the damaged portion of the memory element in the memory cell array 100 can be easily identified.

<Second Embodiment>
In the second embodiment, as shown in FIG. 12, the reference transistor Tr9 of the column gate 400 is connected to the branch line VSSr of the ground node VSS from the end of the branch line VSSr to the main node of the ground node VSS. Until then, each monitor switch Sr (0), Sr (k−1), Sr (k), Sr (k + 1), Sr (n) having voltage measurement points connected to their respective positions is installed. 7 selects the branch wiring VSSr as the row of the branch wiring in the outer portion of the memory cell array 100, and the column scanning circuit 104 controls the monitor switch installed on the branch wiring VSSr. The switch selection circuit SE is switched to transmit the potential of the branch wiring VSSr at the position where the voltage measurement point of the monitor switch is connected to the monitor pad PAD. As described above, the potentials at the voltage measurement points of the monitor switches Sr (0), Sr (k−1), Sr (k), and Sr (k + 1) are sequentially transmitted to the monitor pad PAD, so that the branch line VSSr is transmitted. There is an effect that the potential at the position to which the reference transistor Tr9 is connected can be measured in order.

  For example, when the reference transistor Tr9 at the position where the voltage measurement point of the monitor switch Sr (k) is connected is damaged and shorted to the branch line VSSr, the potential of the branch line VSSr at that position rises. FIG. 13 shows the potential of the branch wiring VSSr. The potential of the branch line VSSr shown in FIG. 13 is the same as the potential detected by the monitor switch Sr (0) having the voltage measurement point connected to the end of the branch line VSSr, and the branch line VSSr before and after the monitor switch Sr (k). The monitor switches Sr (k−1) and Sr (k + 1) in which the voltage measurement point is connected to the position of the reference transistor Tr9 connected to, and the voltage measurement point to the position where the branch wiring VSSr is connected to the trunk of the ground node VSS The potential at the position of the monitoring switch Sr (n) and the ground pad VSS-P of the ground node VSS is shown.

  When the reference transistor Tr9 at the position of the branch line VSSr to which the monitoring switch S (k) is connected to the voltage measurement point is damaged and short-circuited to the branch line VSSr, the position from the position to the ground pad VSS-P Since an excessive current flows through the branch wiring VSSr, a steep potential gradient is generated in the branch wiring VSSr from the position of the damaged reference transistor Tr9 toward the ground pad VSS-P. Therefore, by measuring the potential at each position of the branch wiring VSSr, this steep potential gradient can be detected, and thereby the position of the reference transistor Tr9 that is damaged (becomes defective) can be specified. By connecting the voltage measurement point of the monitor switch Sr (k) (k = 0 to n) to the position of the source terminal of the reference transistor Tr9 connected to the branch line VSSr of the ground node VSS in this way, the damaged reference transistor There is an effect that the position of Tr9 can be specified.

<Third Embodiment>
As shown in FIG. 14, the third embodiment is not limited to the ground node VSS, but includes the power supply node VSS of each circuit, the output power supply node VCCO, the output ground node VSSO, the power supply power node VCCP, and the power supply ground node. Connect the voltage measurement point of the monitor switch such as Ss (k) to the position where each transistor is connected to the branch wiring of VSSP, and identify the position of the damaged transistor by detecting the potential gradient in the branch wiring can do. The row scanning circuit 102 in FIG. 7 selects the branch wiring as a row of the branch wiring other than the memory cell array 100, and the column scanning circuit 104 switches the switch selection circuit SE that controls the monitor switch installed on the branch wiring. .

  As an example, as shown in the circuit diagram of FIG. 15, with respect to the branch wiring of the ground node VSS of the sense amplifier 500, the voltage measurement point of the monitor switch Ss0 is connected to the position where the source terminal of the transistor Tr5 of the feedback bias circuit 501 is connected. The voltage measurement point of the monitor switch Ss3 is connected to the position where the source terminal of the transistor Tr11 of the reference feedback bias circuit 506 is connected, and the monitor is connected to the position where the source terminal of the transistor of the differential sense amplifier 503 is connected. The voltage specific points of the switches Ss1 and Ss2 are connected.

  Further, with respect to the branch wiring of the power supply node VCC of the sense amplifier 500, the voltage measurement point of the monitor switch Ss4 is connected to the position where the drain terminal of the transistor Tr4 of the feedback bias circuit 501 is connected, and the reference feedback bias circuit 506 The voltage measurement point of the monitor switch Ss8 is connected to the position where the drain terminal of the transistor Tr10 is connected, and the voltage measurement point of the monitor switch Ss5 is connected to the position where the drain terminal of the transistor Tr1 of the load circuit 502 is connected. The voltage measurement point of the monitor switch Ss7 is connected to the position where the drain terminal of the transistor Tr6 of the load circuit 505 is connected, and the voltage of the monitor switch Ss6 is connected to the position where the drain terminal of the transistor of the differential sense amplifier 503 is connected. To connect the measurement point.

  Since there are 16 sense amplifiers in the semiconductor memory device 1 having a 16-bit configuration, the 16 sense amplifiers branch when the currents of the respective sense amplifiers flow through one or two branch wirings of the ground node VSS. Although the potential varies depending on the position of the wiring, there is an effect that the potential can be sequentially measured with the monitor switch along the branch wiring. Similarly, the potential of each sense amplifier in the branch wiring of the power supply node VCC can be easily measured using the monitor switch. As described above, the voltage measuring points of the monitoring switches Ss0 to Ss8 are connected to the positions where the transistors are connected to the ground node VSS and the power supply node VCC, and the potential abnormality at the position where the voltage measuring points of the monitoring switches are connected is detected. Thus, the position of the damaged transistor can be easily specified. As described above, there is an effect that a defective portion can be easily identified by simple electrical measurement.

  Similarly, by connecting the voltage measurement point of the monitor switch to the position where the transistor of the power supply circuit 900 is connected to the power supply ground node VSSP and the power supply power supply node VCCP, a power supply that easily causes a voltage drop due to a large current flows. The potential at the position of each circuit element in the circuit 900 can be accurately measured. Further, by connecting the voltage measurement points of the switches to the potentials of the power supply node VCC and the ground node VSS of the control circuit 600, there is an effect that the operation stability of the control circuit 600 can be accurately monitored.

  Although the embodiments of the present invention have been described above, the semiconductor memory device 1 of the present invention is not limited to the above illustrated examples, and various modifications can be made without departing from the scope of the present invention. be able to. In other words, the semiconductor memory device 1 of the present invention is not limited to the mask ROM, and a monitor circuit can be similarly installed in the semiconductor memory device 1 including a flash memory, a semiconductor memory such as SRAM, and a sense amplifier. By measuring the voltage at the voltage measurement point at the position selected by the monitor switch for the damage of the transistor of the installed semiconductor memory device 1, the effect of easily identifying the position of the damaged transistor can be obtained.

DESCRIPTION OF SYMBOLS 1 ... Semiconductor memory device 100, 100-0, 100-15 ... Memory cell array 110 ... Switch selection signal generation circuit 101 ... Timing generator 102 ... Row scanning circuit 103 ... Row selection line 104 ... Column scanning circuit 105 ... Column selection line 106 ... AND gate 107 ... NAND gates 200, 200-0, 200-m ... Row decoder 201 ... NAND circuit 202 ... Inverters 300, 300-0, 300-n serving as buffers ... Column decoder 301 ... NAND circuit 302 ... Inverters 400 serving as buffers ... Column gates 500, 500-0, 500-15 ... Sense amplifier 501... Feedback type bias circuit 502... Load circuit 503... Differential type sense amplifier 504. Reference circuit 505 ... Reference load circuit 506 ... Reference feedback bias circuit 507 ... VREF circuit 508 ... Feedback bias circuit 509 ... Load circuit 600 ... Control circuit 700 ... Output buffer 800... Address input circuit BIT0, BIT1, BIT2, BIT3, BIT0-0, BITn-0, BIT0-15, BITn-15, BIT (k-1), BITk, BIT (k), BIT (k + 1) ), BIT (n)... Column line nodes CG0, CG1, CG2, CG3, CGk, CGn... Column selection transistors COL0, COL (k−1), COL (k), COL (k + 1), COL ( n) ... column selection nodes COM, COM0, COM15 ... common nodes Dout0, Do t1, Dout15... output terminal Icell. k-1), M (h + 1) k, M (h + 1) (k + 1), M (h + 1) n ... memory element PAD ... monitor pad REC ... reference common node REP ... reference potential Nodes RF0, RF1, RE2, RF3, RFk... Reference column selection transistors S0, S1, S2, Sh, Sm, Su, S (0), S (h-1), S (h), S (h + 1) ... Monitor switches Sr (0), Sr (k-1), Sr (k), Sr (k + 1), Sr (n)... Reference circuit monitor switches Ss0, Ss1, Ss2, Ss3, Ss4, Ss5, Ss6, Ss7, Ss8, Ss (k)... Sense amplifier monitoring switches SEhk, SE00, SEmn... Switch selection circuit T1 at the position of the memory element Mhk... Transistor T2 having the same size as the memory element, T3, T4, T5, T6, T7, T8, T9, T10 ... transistor Tr1, Tr2 ... load transistor Tr3 ... bias transistors Tr4, Tr5, Tr6, Tr7, Tr10, Tr11 ... transistor Tr8 ..Reference bias transistor Tr9 ... Reference transistor VCC ... Power supply node VCCO ... Output power supply node VCCP ... Power supply power node VCC-P ... Power supply pad VCCO-P ... Output Power supply pad VCCP-P: Power supply pad V for power supply S: ground node VSSr, VSS0, VSS1, VSS2, VSS (m-1), VSSm, VSS (m + 1), VSS (m + 2), VSS (m + 3), VSSSh: branch wiring VSSO: for output Ground node VSSP: Power supply ground node VSS-P: Ground pad VSSO-P: Output ground pad VSSP-P: Power supply ground pads WLh, WLm, WL0, WL1, WL2, WL3,. ..Row line nodes

Claims (5)

A memory cell array having memory elements arranged in a matrix in rows and columns, a ground node or have a branch wiring connected to power supply node, wherein each memory element in the row and column directions of the array of the memory cell array is a column decoder and a row decoder In the semiconductor memory device selected by
Each of the memory elements has a monitor switch in which a voltage measurement point is connected to a branch wiring connected to a power supply node or a ground node,
A switch selection signal generating circuit for sequentially opening the gates of the monitor switches by selecting a row in the row direction and the column direction in synchronization with a clock signal, and selecting a column by the column scanning circuit. Have
The column scanning circuit of the switch selection signal generating circuit selects and stops a column, causes the column decoder to select the column, operates the memory element, and the row scanning circuit selects a row and opens a gate. A semiconductor memory device characterized in that the potential of the voltage measurement point is measured through a monitor switch whose gate is opened using means . The semiconductor memory device according to claim 1,
A plurality of sense amplifiers for amplifying signals read from the memory cells of the memory cell array;
The semiconductor memory device, wherein the at least one branch wiring is a ground wiring of the sense amplifier or a branch wiring of a power supply node. The semiconductor memory device according to claim 1,
The semiconductor memory device, wherein the at least one branch wiring is a power supply ground node of a power supply circuit or a branch wiring of a power supply power supply node. The semiconductor memory device according to claim 1,
The semiconductor memory device, wherein the at least one branch wiring is a ground node of a control circuit or a branch wiring of a power supply node. The semiconductor memory device according to claim 1, wherein the potential of each part of the branch wiring is sequentially transmitted to the monitoring pad by the switch selection signal generation circuit and the monitor switch. Potential measurement method.

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