JP5484106B2 - Analog high-speed amplifier and image sensor using the same - Google Patents

Description

  The present invention relates to an analog high-speed amplifier and an image sensor using the same.

  In recent years, elements having various functions are mounted on a minute chip in a sensing device such as an image sensor. Among these elements, an analog high-speed amplifier that amplifies an analog signal at high speed is an important element that affects the performance of the entire sensing device. Analog high-speed amplifiers amplify weak signals output from photoelectric conversion elements of sensing devices, as well as various types of signal mixing, signal computation, long-distance transmission amplification to the subsequent stage, conversion from analog signals to digital signals, etc. It is used in the mode.

  The sensing device uses a large number of analog high-speed amplifiers for realizing these various functions, and the number of analog high-speed amplifiers increases as the resolution of the sensing device increases. For this reason, suppressing the power consumption of each analog high-speed amplifier is extremely important for suppressing the power consumption of the entire sensing device.

  The original purpose of the analog high-speed amplifier is to linearly amplify a pixel signal or the like read out from the photoelectric conversion element or the like in proportion to the input level. However, it is not always easy to realize this original purpose.

  In an analog high-speed amplifier for amplifying pixel signals, each pixel signal is normally amplified in synchronization with a pixel clock. Specifically, the pixel clock cycle is divided into a sampling period and a reset period, and the output of the analog high-speed amplifier is reset to a predetermined fixed potential (reset potential) during the reset period, while the pixel signal input in the sampling period is amplified. doing. The output of the analog high-speed amplifier rises from the reset potential in the first half of the sampling period and settles in the second half of the sampling period. The output value after settling becomes the output value of the pixel signal amplified by the analog high-speed amplifier.

  In such an amplification process, the following two problems have been conventionally confirmed.

  The first problem is an event that the rising speed from the reset potential becomes slow due to an insufficient slew rate of the analog high-speed amplifier, and the output may not be completely settled even at the end of the sampling period. If the difference between the value after settling and the value in the unsettling state is called settling error, the first problem is that settling error occurs due to insufficient slew rate. The settling error varies depending on the input level, and also varies depending on variations in slew rate characteristics of individual analog high-speed amplifiers. For this reason, the linearity of the analog high-speed amplifier is impaired, and when this analog high-speed amplifier is used for an image sensor, the reproducibility of the image is lowered.

  As a measure for improving the slew rate, a method of simply increasing the operating current of an analog high-speed amplifier is known. However, this method increases power consumption, and particularly an image sensor using a large number of analog high-speed amplifiers. Is not a preferable solution.

  The second problem is that the analog high-speed amplifier saturates when a pixel signal of a large level exceeding the expected range is input, and is affected by this saturation. It is a problem that even the pixels are subject to level fluctuations. Even if it is unavoidable that pixels of a large level outside the assumed range are saturated, it is not preferable that pixels up to a level that should not be saturated originally be affected by the saturated pixels and cannot output a correct level.

  The present invention has been made in view of the above circumstances, and an analog high-speed amplifier capable of improving the slew rate while suppressing an increase in power consumption while reducing the influence of saturated pixels and realizing high linearity, and An object is to provide an image sensor using the same.

In order to solve the above-described problems, an analog high-speed amplifier according to the present invention is an analog high-speed amplifier that inputs and amplifies an independent level signal at a predetermined clock cycle. The amplifier main body includes the sampling period and the reset period. A sampling means for inputting the signal to the amplifier main body during the sampling period, a reset means for resetting the output of the amplifier main body to a predetermined reset potential during the reset period, and the sampling period Among them, a predetermined period shorter than the sampling period from the start time of the sampling period is set as a current increase period, and during the current increase period, an operating current supplied to the amplifying unit main body is from a period other than the current increase period. also it increases, and the operating current controlling means, said output by monitoring the output of the amplifier body A determination unit that determines whether or not the linear operation range is exceeded, and when the linear operation range is exceeded, the reset period is set longer than when the linear operation range is not exceeded. It is characterized by.

In order to solve the above problems, an image sensor according to the present invention is connected to a photoelectric conversion element group that is two-dimensionally arranged in n rows and m columns, and an output of each row of the photoelectric conversion element group, or an output of each column. N or m analog high-speed amplifiers, and each analog high-speed amplifier is an analog high-speed amplifier that inputs and amplifies a signal of an independent level at a predetermined clock cycle, A sampling means for dividing the clock cycle into a sampling period and a reset period, and inputting the signal to the amplifier main body during the sampling period; and during the reset period, an output of the amplifier main body is set to a predetermined reset potential. Reset means for resetting to a predetermined period shorter than the sampling period from the start of the sampling period. A flow increase period, during the current increase period, the operating current supplied to the amplifier main body than the period other than the current increasing period to increase the operating current controlling means monitors the output of the amplifier body And a determination unit that determines whether or not the output exceeds a linear operation range, and when the output exceeds the linear operation range, the reset period is set longer than when the linear operation range is not exceeded. It is characterized by.

  According to the analog high-speed amplifier and the image sensor using the same according to the present invention, it is possible to improve the slew rate while suppressing an increase in power consumption, while reducing the influence of saturated pixels and realizing high linearity.

The figure which shows the structural example of the conventional analog high-speed amplifier. An explanatory view of the operation and problems of a conventional analog high-speed amplifier. The figure which shows the structure of a general source grounding type amplifier. The figure which shows an example of the operation simulation result of the conventional analog high-speed amplifier. The figure which shows the structural example of the analog high-speed amplifier which concerns on this embodiment. FIG. 6 is an operation explanatory diagram of the analog high-speed amplifier according to the present embodiment. The figure which shows the 1st structural example of an operating current control means. The figure which shows the 2nd structural example of an operating current control means. 1 is a diagram illustrating a configuration example of an image sensor according to a first embodiment. The figure which shows the structural example of the image sensor which concerns on 2nd Embodiment. The figure which shows the structural example of a cyclic AD converter. Operation | movement explanatory drawing of a cyclic | annular AD converter.

  Embodiments of an analog high-speed amplifier and an image sensor according to the present invention will be described with reference to the accompanying drawings.

(1) Conventional Problems First, in order to understand the present invention, the configuration and problems of a conventional analog high-speed amplifier will be described in a little more detail.

  FIG. 1 is a block diagram illustrating a configuration example of a conventional analog high-speed amplifier 100. The analog high-speed amplifier 100 performs, for example, amplification processing by synchronizing an analog signal (pixel signal) output from a photoelectric conversion element with a pixel clock.

  The analog high-speed amplifier 100 includes an amplifier body 10, a timing generation unit 11, a sampling switch 12, and a reset switch 13. A pixel signal is input to the amplifier body 10 via the sampling switch 12. On the other hand, the output of the amplifier body 10 is provided with a reset switch 13 connected to the common potential Vcommon. When the reset switch 13 is closed, the output of the amplifier body 10 is reset to the common potential Vcommon.

  For the pixel signal transmission, a fully differential amplifier is often used for the purpose of common noise removal or the like, but in FIG. 1, it is shown as a block diagram of a single-ended amplifier for simplicity of explanation. Yes.

  FIG. 2 is a diagram showing an output waveform and operation timing of the conventional analog high-speed amplifier 100. FIG. 2A illustrates how the two output voltage waveforms of the fully differential amplifier change around the common potential Vcommon. The solid lines above and below the output voltage waveform indicate the linear operating range of the analog high-speed amplifier 100.

  The analog high speed amplifier 100 amplifies each pixel signal in synchronization with the pixel clock (FIG. 2D).

  In the timing generator 11, the pixel clock cycle is divided into a sampling period and a reset period, and the sampling pulse SW_IN (FIG. 2B) that is turned on in the sampling period and turned off in the reset period is turned off and reset in the sampling period. A reset pulse SW_R (FIG. 2C) that is turned on during the period is generated. The sampling pulse SW_IN is applied to the sampling switch 12, and the reset pulse SW_R is applied to the reset switch 13, respectively, to control on / off of each switch.

  During the sampling period, the sampling switch 12 is closed and an input signal is input to the amplifier body 10. The amplifier body 10 amplifies and outputs the input signal. At this time, a transient response is involved, so that the output voltage changes so as to rise from the common potential Vcommon before the sampling period and settles after the sampling period. For this reason, the output of the amplifier body 10 is fetched at a position just before the end of the sampling period (data fetch point in FIG. 2A), and is subjected to processing such as AD conversion.

  During the reset period, the sampling switch 12 is opened and the input is shut off, while the reset switch 13 is closed and reset to the common potential Vcommon. For this reason, the output voltage of the amplifier body 10 changes rapidly from the set potential toward the common potential Vcommon. Thereafter, the above operation is repeated for each pixel clock.

  A waveform A on the left side of FIG. 2A shows an output waveform in a desired operation state, that is, when the signal level is within the linear operation range and the slew rate is sufficiently high.

  Waveform B is a waveform corresponding to the first problem described above, and is a case where the slew rate of the amplifier main body 10 is insufficient and the data capture timing comes before the output voltage is settled. In this case, the original correct output value (the output value after settling) is different from the actually captured signal value, and a settling error occurs between them.

  A waveform C shows an output waveform when a signal having a level exceeding the linear operation range is input, and saturation occurs.

  A waveform D is a waveform indicating the above-mentioned second problem. Under the influence of saturation, a pixel having a small input level following the saturation pixel (waveform C) has an offset error superimposed from the original level indicated by a broken line. Has changed to the specified level. Even if it is unavoidable to saturate a pixel at a large level outside the assumed range, pixels up to a level that should not originally be saturated are affected by the saturated pixel and cannot output a correct level. The cause of the offset error is that the output voltage does not completely reach the common potential Vcommon during the reset period due to the influence of saturation of the previous pixel, and the difference (offset) between the output voltage and the common potential Vcommon remains as it is in the subsequent pixel. This is probably because it is superimposed on the settling level.

  In order to solve the first problem, the slew rate may be improved and the settling time may be shortened. However, when it is found that the slew rate is insufficient after the amplifier body 10 is designed and manufactured, the circuit scale and circuit constant cannot be easily changed. For this reason, as a practical solution, a method of uniformly increasing the operating current has been conventionally used.

In the case of the common source ground type amplifier shown in FIG. 3, the unity gain frequency ωu (frequency at which the gain is 1) of the amplifier is expressed by the following equations (1) and (2).

Where ω _u is unity gain frequency, gm is transconductance, C _L is load capacitance, μ is carrier mobility, C _OX is gate oxide film capacitance, W is gate width, L is gate length, and _ID is operation Current (drain current).

As can be seen from the equations (1) and (2), by increasing the operating current _ID , the bandwidth of the amplifier (unity gain frequency ω _u ) is increased, and the settling time can be shortened.

However, increasing the operating current _ID not only increases power consumption, but also increases the effective gate voltage V _eff expressed by the following equation (3), and therefore is expressed by equation (4). This will narrow the signal amplitude range V _swing .

Also, reduced gain A _V of the formula (5) is comprised of the actual gain and the gain of the design are different, the settling accuracy decreases.

Here, V _eff is an effective gate voltage, V _swing is a signal amplitude range, ro is an output resistance, λ is a channel length modulation coefficient, and other specifications are the same as those described above.

  In this way, the method of simply increasing the operating current to shorten the settling time not only increases the power consumption but also affects the signal amplitude range and gain (settling accuracy). It is not.

  On the other hand, regarding the second problem (occurrence of offset error due to saturation), it has been found from the results of simulations and the like that the offset error can be eliminated or reduced by extending the reset period.

  FIG. 4 shows a result obtained by simulating the output when a small signal (for two pixels) within the linear operation range is input to the amplifier after inputting a large saturation signal (for two pixels) exceeding the linear operation range. It is a figure which shows an example. A standard reset period was set for the first small signal, and a longer reset period extended than this was set for the second small signal.

  As can be seen from FIG. 4, although an offset error ΔV occurs for the standard reset period, if a reset period longer than the standard reset period is set, the offset error may be negligibly small. all right.

  From this simulation result, it has been found that if the reset period is lengthened, offset errors can be eliminated or reduced even if saturation occurs, but extending all reset periods shortens all sampling periods. This time, there is a possibility of generating a settling error.

(2) Analog high-speed amplifier according to this embodiment An analog high-speed amplifier 1 according to this embodiment described below solves the problems of the conventional analog high-speed amplifier 100 described above.

  FIG. 5 is a block diagram illustrating a configuration example of the analog high-speed amplifier 1 according to the present embodiment. The analog high-speed amplifier 1 includes an operating current control unit 14, a comparator (determination unit) 15, and an OR circuit in addition to the amplifier body 10, the timing generation unit 11a, the sampling switch 12, and the reset switch 13 in the conventional analog high-speed amplifier 100. 16 is configured.

  FIG. 6 is a diagram showing an example of the output voltage waveform of the analog high-speed amplifier 1 and the operation timing according to the present embodiment.

  In the timing generation unit 11a of the analog high-speed amplifier 1, in addition to the sampling pulse SW_IN and the reset pulse SW_R, a current increase pulse SW_AC is generated and the current increase pulse SW_AC is applied to the operating current control means 14.

  As shown in FIG. 6D, the current increase pulse SW_AC is a pulse signal synchronized with the pixel clock. For example, the ON period corresponds to the operating current increase period. The operating current increase period is a predetermined period shorter than the sampling period, rises simultaneously with the start of the sampling period, and falls before the end of the sampling period.

  The operating current increase period corresponds to the transient response period of the amplifier body 10. As described above, by increasing the operating current of the amplifier body 10, the bandwidth of the amplifier body 10 can be expanded and the slew rate can be increased, and the settling time can be shortened.

  In this embodiment, by limiting the increase period of the operating current to the transient response period, while limiting the increase in power consumption compared to increasing the operating current at all times, The rate is increasing. In other words, the period during which the slew rate should be increased is the transient response period, and during other periods it is not necessary to increase the slew rate, and the increase in operating current is minimized by increasing the operating current only during the minimum necessary period. The settling time is shortened while limiting to the limit.

  As a result, a waveform B (waveform having a settling error) indicated by a broken line in the center of FIG. 6A becomes a waveform B ′ having a reduced settling time indicated by a solid line, and the settling error at the data acquisition point is eliminated or eliminated. Is reduced.

  In addition, in this embodiment, since the operating current is returned to the original standard operating current during the settling period after the transient response is completed, the signal amplitude range and gain (settling accuracy) are affected at the time of data acquisition. There is also an advantage of not giving.

  As a specific example of the operating current increasing means 14, there is a method of switching the bias reference voltage of the transistor included in the amplifier main body 10 with a switch or the like. FIG. 7 is a diagram illustrating a configuration example of a method of switching the bias reference voltage. In this configuration, the operating current control unit 14 includes a bias voltage generation unit 1 (voltage V1) and a bias voltage generation unit 2 (voltage V2: V1> V2) having different voltages, and is a switch driven by a current increase pulse SW_AC. 22 is selectively switched between the two. For example, when the high voltage V1 is selected, the operating current of the amplifier body 10 increases, and when the low voltage V2 is selected, the operating current returns to the standard state.

  Another specific example of the operating current increasing means 14 is a system in which the operating current increasing means 14 is incorporated in the amplifier body 10 and the amount of operating current is switched by switching the connection state of transistors that determine the operating current. .

  FIG. 8 is a diagram showing a circuit configuration example of the amplifier body 10 having the operating current control means 14 of this system. The amplifier body 10 includes transistors Tr1 to Tr7, and the transistor Tr5 is a transistor that mainly performs signal amplification.

On the other hand, the operating current of the signal amplifying transistor Tr5 is generated by the first transistor Tr1 and the second transistor Tr2 connected to the power source V _DD and the first transistor Tr6 and the second transistor Tr7 connected to the ground side. Generally determined.

  The first transistor Tr1 and the second transistor Tr2 operate in parallel when the switch SW1 is closed, and operate independently of the first transistor Tr1 when the switch SW1 is open. Similarly, the first transistor Tr6 and the second transistor Tr7 operate in parallel when the switch SW2 is closed, and operate independently of the first transistor Tr6 when the switch SW2 is open.

  Since the first and second transistors are connected in parallel when the switches SW1 and SW2 are closed, the operating current of the signal amplifying transistor Tr5 is increased compared to the normal time, and the first when the switches SW1 and SW2 are open. The operating current returns to the normal operating current.

  In either case, the operating current increases more than usual during the period when the current increasing pulse SW_AC is on, the settling time is shortened, and the settling error, which is the first problem, is eliminated or reduced.

On the other hand, with respect to the second problem, the reset period immediately after the saturation is set longer only when the saturation occurs, and the offset error due to the saturation is eliminated or reduced.
The method for extending the reset period is not particularly limited. For example, when the comparator (determination unit) 15 shown in FIG. 5 compares the output of the amplifier body 10 (output at the data acquisition point) with a saturation determination value, and the output of the amplifier body 10 exceeds the saturation determination value, A determination pulse that is turned on from the data acquisition point is generated. The ON period of the determination pulse is set so as to overlap with the ON period of the standard length reset pulse SW_R generated by the timing generator 11a. Then, the OR circuit 16 takes the OR of the determination pulse and the standard-length reset pulse SW_R to generate the extension reset pulse shown on the right side of FIG. 6C, and applies this extension reset pulse to the reset switch 13.

As the reset pulse becomes longer, the time for convergence from the saturated potential to the common potential Vcommon is lengthened, the offset of the conventional waveform D indicated by the dotted line is reduced, and the waveform D ′ without the offset error indicated by the solid line is obtained.
Since a standard-length reset pulse SW_R is applied to a waveform in which saturation does not occur, the sampling period also becomes a standard length, and there is no possibility of causing a settling error.

  According to the analog high-speed amplifier 1 described above, while the increase in power consumption is suppressed, the slew rate is improved and the settling error is reduced. On the other hand, the offset error due to the saturation pixel can be reduced, and the linearity is high. An analog high-speed amplifier 1 can be realized.

(3) Image Sensor FIG. 9 is a diagram illustrating a configuration example of the image sensor 30 (first embodiment) using the analog high-speed amplifier 1 described above.

  The image sensor 30 includes a photoelectric conversion element group 31 two-dimensionally arranged in n rows and m columns, and m columns of analog high-speed amplifiers 1 that amplify analog pixel signals output from the columns. . In the case of HDTV image sensors that are popular today, the number of pixels is 1920 × 1080, and the number of analog high-speed amplifiers 1 is up to 1920. In the case of such an image sensor 30, even if the increase in power consumption of each analog high-speed amplifier 1 is small, the power consumption of the image sensor 30 as a whole is greatly increased.

By using the analog high-speed amplifier 1 described above, it is possible to reduce the settling error while suppressing an increase in power consumption, so that the effect of contributing to power saving is great.
Further, since the settling error and offset error of each analog high-speed amplifier 1 are reduced and the linearity is high, an output signal that is proportional to the input pixel level can be obtained, and a high-quality image can be provided.

  FIG. 10 is a diagram illustrating a configuration example of the image sensor 30a (second embodiment). The image sensor 30a according to the second embodiment includes a photoelectric conversion element group 31 that is two-dimensionally arranged in n rows and m columns, and m columns of cyclic AD conversions that perform AD conversion on analog pixel signals output from the columns. And a container 40. Each cyclic AD converter 32 has an offset error reduction function similar to the analog high-speed amplifier 1 described above.

  FIG. 11 is a block diagram illustrating a configuration example of the cyclic AD converter 40. The cyclic AD converter 40 includes a sample hold amplifier 41, a cyclic bit sampling switch 42, a 1-bit AD conversion element ADSC 43, a DA conversion element 44, a double gain amplifier main body 45, a determination unit 46, a reset switch 47, and the like. Yes.

The cyclic AD converter 40 AD-converts the input analog signal Vsig while cycling the residual bit by bit from the MSB to the LSB. The configuration and operation of the cyclic AD converter 40 excluding the determination unit 46 and the reset switch 47 are well known, and a specific description of the cyclic AD conversion function itself is omitted.
Also in the 2 × gain amplifier main body 45 provided in the cyclic AD converter 40, a settling error due to insufficient slew rate occurs. Therefore, also in the cyclic AD converter 40 in the present embodiment, a current increasing period is provided in a part of the sampling period excluding the reset period, and the operating current is increased during the current increasing period to increase the double gain amplifier main body 45. A method of expanding the band and reducing settling errors is used.

  If a large level exceeding the linear range is input, an offset error occurs due to the influence of saturation. Therefore, in the cyclic AD converter 40 according to the present embodiment, a determination unit 46 having a determination function similar to the determination unit 15 (see FIG. 5) in the analog high-speed amplifier 1 is provided. When the determination unit 46 determines that a large level signal exceeding the linear operation range has been input, the reset pulse reset period is set to be longer than when the linear operation range is not exceeded. ing.

FIG. 12 is a diagram illustrating a specific example for setting the reset pulse reset period longer.
The data output DO shown at the bottom of FIG. 12 illustrates an output bit string sequence in the case of a 13-bit AD converter. MSB is expressed as D [12] and LSB is expressed as D [0]. Yes.

  The determination unit 46 monitors the output of the ADSC 43 that is sequentially converted from the MSB to the LSB, and data at least one bit before the LSB, for example, 12-bit digital data from D [12] to D [1] The output and the saturation judgment value (digital data) are compared and judged. As a result of the comparison determination, when the digital data output exceeds the saturation determination value, that is, when it is determined that the input signal exceeds the linear operation range, it is originally used for the conversion of LSB D [0]. Is used for extending the reset period, so that the reset period is set longer than usual. As a result, as described above, the influence of saturation can be cut off and the occurrence of offset errors can be reduced.

  However, in this case, since AD conversion processing is stopped and reset in the middle, data of bits lower than the stopped bit cannot be obtained. For example, in the example shown in FIG. 12, LSB data D [0] cannot be obtained, but this method is effective when the offset error is larger than the deterioration of AD conversion accuracy due to the shortening of the bit length.

  As described above, according to the analog high-speed amplifier 1 and the image sensors 30 and 30a according to the present embodiment, while improving the slew rate while suppressing an increase in power consumption, the influence of saturated pixels is reduced and high. Linearity can be realized.

  Note that the present invention is not limited to the above-described embodiments as they are, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. In addition, various inventions can be formed by appropriately combining a plurality of components disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, the constituent elements over different embodiments may be appropriately combined.

DESCRIPTION OF SYMBOLS 1 Analog high speed amplifier 10 Amplifier main body 11a Timing generation part 12 Sampling means (sampling switch)
13 Reset means (reset switch)
14 Operating current control means 15 Determination unit (comparator)
30 Image sensor 31 Photoelectric conversion element group 40 Cyclic AD converter

Claims (9)

In an analog high-speed amplifier that inputs and amplifies an independent level signal at a predetermined clock cycle,
Amplifying unit body;
Sampling means for dividing the clock cycle into a sampling period and a reset period, and inputting the signal to the amplifying unit main body during the sampling period;
During the reset period, reset means for resetting the output of the amplifier main body to a predetermined reset potential;
Among the sampling periods, a predetermined period shorter than the sampling period from the start time of the sampling period is defined as a current increase period, and during the current increase period, an operating current supplied to the amplifying unit main body is other than the current increase period. An operating current control means for increasing the period of time,
A determination unit that monitors the output of the amplification unit main body and determines whether the output exceeds a linear operation range; and
With
When the linear operating range is exceeded, the reset period is set longer than when the linear operating range is not exceeded.
An analog high-speed amplifier characterized by that . A pulse generator for generating a sampling pulse, a reset pulse, and a current increase pulse each having an on period corresponding to each of the sampling period, the reset period, and the current increase period;
The sampling means inputs the signal when the sampling pulse is on,
The reset means resets the output of the amplification unit body when the reset pulse is on,
The operating current control means increases the operating current when the current increase pulse is on.
The analog high-speed amplifier according to claim 1. The sampling means is composed of a switch that is turned on and off by the sampling pulse, and the reset means is composed of a switch that is turned on and off by the reset pulse.
The analog high-speed amplifier according to claim 2. The operating current control means increases the operating current by switching a voltage value of a bias voltage applied to a transistor included in the amplifier body according to an on / off state of the current increasing pulse.
The analog high-speed amplifier according to claim 2. The amplifier body includes a signal amplifying transistor and first and second transistors for generating an operating current of the signal amplifying transistor,
The operating current control means operates the first transistor only to generate the operating current when the current increasing pulse is off, and the first transistor and the first transistor when the current increasing pulse is on. Increasing the operating current by connecting two transistors in parallel;
The analog high-speed amplifier according to claim 2. The determination unit compares a predetermined saturation determination value with the output of the amplification unit main body to determine whether or not a linear operation range is exceeded, and the output of the amplification unit main body exceeds the saturation determination value It is a comparator that outputs a determination pulse that turns on the period.
The analog high-speed amplifier according to claim 1 . a photoelectric conversion element group arranged two-dimensionally in n rows and m columns;
N or m analog high-speed amplifiers respectively connected to the output of each row or the output of each column of the photoelectric conversion element group;
Comprising
Each analog high-speed amplifier is an analog high-speed amplifier that inputs and amplifies an independent level signal at a predetermined clock cycle,
Amplifying unit body;
Sampling means for dividing the clock cycle into a sampling period and a reset period, and inputting the signal to the amplifying unit main body during the sampling period;
During the reset period, reset means for resetting the output of the amplifier main body to a predetermined reset potential;
Among the sampling periods, a predetermined period shorter than the sampling period from the start time of the sampling period is defined as a current increase period, and during the current increase period, an operating current supplied to the amplifying unit main body is other than the current increase period. An operating current control means for increasing the period of time,
A determination unit that monitors the output of the amplification unit main body and determines whether the output exceeds a linear operation range; and
With
When the linear operating range is exceeded, the reset period is set longer than when the linear operating range is not exceeded.
An image sensor characterized by that . A pulse generator for generating a sampling pulse, a reset pulse, and a current increase pulse each having an on period corresponding to each of the sampling period, the reset period, and the current increase period;
The sampling means inputs the signal when the sampling pulse is on,
The reset means resets the output of the amplification unit body when the reset pulse is on,
The operating current control means increases the operating current when the current increase pulse is on.
The image sensor according to claim 7 . a photoelectric conversion element group arranged two-dimensionally in n rows and m columns;
N or m cyclic AD converters respectively connected to the output of each row or the output of each column of the photoelectric conversion element group;
Comprising
Each of the cyclic AD converters has an analog high-speed amplifier that inputs and amplifies an independent level signal at a predetermined clock cycle;
The analog high-speed amplifier is
Amplifying unit body;
Sampling means for dividing the clock cycle into a sampling period and a reset period, and inputting the signal to the amplifying unit main body during the sampling period;
During the reset period, reset means for resetting the output of the amplifier main body to a predetermined reset potential;
Among the sampling periods, a predetermined period shorter than the sampling period from the start time of the sampling period is defined as a current increase period, and during the current increase period, an operating current supplied to the amplifying unit main body is other than the current increase period. An operating current control means for increasing the period of time,
The cyclic AD converter monitors digital data that is sequentially converted from the MSB to the LSB in units of the clock period, and outputs the output of the amplifying unit main body using the digital data at least one bit before the LSB. A determination unit that determines whether or not the linear operation range has been exceeded,
With
If it is determined that the linear operating range has been exceeded, the reset period is set longer than when the linear operating range is not exceeded.
An image sensor characterized by that .

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