JP5484211B2 - Error correction decoding apparatus and method, and error correction encoding apparatus and method - Google Patents

Description

  The present invention relates to an error correction decoding apparatus and method and an error correction coding apparatus and method used in a digital transmission system.

  Conventionally, in an error correction decoding apparatus (error correction decoding method) and an error correction encoding apparatus (error correction encoding method) applied to high-speed transmission (for example, a digital transmission system for optical communication), a plurality of circuits Has been proposed that enables high-speed transmission even when a low-speed circuit is used (see, for example, Patent Document 1).

In the conventional decoding method and apparatus described in Patent Document 1, an input signal is divided into blocks by a signal distributor and is sequentially supplied to a plurality of error correction decoding circuits.
However, according to the above-described conventional configuration, when the number of parallel is large, the number of switching signals in the serial-parallel conversion is large. Therefore, for example, the number of I / O (Input / Output) such as FPGA (Field Programmable Gate Array) However, it is difficult to realize with a limited circuit.

JP-A-8-124321

  Since the conventional error correction decoding apparatus and method and the error correction encoding apparatus and method are configured as described above, the number of signal lines at the time of switching increases. There was a problem that it could not be realized due to the limitation of.

  The present invention has been made in order to solve the above-described problems. In response to a high-speed transmission request in a digital transmission system, by using a plurality of low-speed circuits without increasing the number of signal lines, for example, in an FPGA. It is an object to obtain a feasible error correction decoding apparatus and method and an error correction coding apparatus and method.

An error correction decoding apparatus according to the present invention includes a plurality of error correction decoding circuits connected in cascade on input data lines, and each of the plurality of error correction decoding circuits is configured to input common received data and control signals. to process a coded sequence having a separate specific information, based on the control signal and the unique information, write Mutotomoni from the received data takes the predetermined input data, what th codeword of the code sequence input The codeword recognized or decoded is selected and acquired from the code sequence, and error correction decoding processing is performed.

  According to the present invention, a plurality of error correction decoding circuits are connected in cascade, a specific part is selectively acquired from a code sequence inputted at high speed, and encoded or decoded. Instead, the sequence encoded or decoded in the preceding stage is used. Thus, even if an error correction decoding circuit having a low throughput capability is used, a high speed error correction decoding apparatus can be realized without increasing the number of signal lines.

It is a block diagram which shows the structural example of the error correction decoding apparatus which concerns on Embodiment 1 of this invention. It is a timing chart which shows the operation example of the error correction decoding apparatus which concerns on Embodiment 1 of this invention. It is explanatory drawing which shows typically the monitor information replacement output by Embodiment 1 of this invention. It is a block diagram which shows the structural example of the error correction decoding apparatus which concerns on Embodiment 2 of this invention. It is a timing chart which shows the operation example of the error correction decoding apparatus which concerns on Embodiment 2 of this invention. It is a block diagram which shows the structural example of the error correction coding apparatus which concerns on Embodiment 3 of this invention. It is a timing chart which shows the operation example of the error correction coding apparatus which concerns on Embodiment 3 of this invention. It is a block diagram which shows the structural example of the error correction coding apparatus which concerns on Embodiment 4 of this invention. It is a timing chart which shows the operation example of the error correction coding apparatus which concerns on Embodiment 4 of this invention.

Embodiment 1 FIG.
FIG. 1 is a block diagram showing a configuration example of an error correction decoding apparatus 1 according to Embodiment 1 of the present invention.
In FIG. 1, the error correction decoding apparatus 1 includes an input interface 4, a plurality (three) of error correction decoding circuits 5, 6, 7 connected in cascade on input data lines, and an output interface 15.

The input interface 4 receives the control signal 2 indicating the head of the code sequence and the received data 3 of a plurality of error correction code sequences, and inputs them to the error correction decoding circuit 5 in the first stage (head of the cascade connection).
The error correction decoding circuits 5, 6, and 7 have the same circuit configuration, and sequentially decode input signals.

  The error correction decoding circuit 7 at the third stage (the end of the cascade connection) outputs a control output signal 16 indicating the head of the code sequence and corrected data 17 after the error correction result via the output interface 15.

  The first stage error correction decoding circuit 5 is connected to the input RAM interface 8 and the output RAM interface 10 arranged in series on the input data line, the input RAM 9 connected to the input RAM interface 8, and the output RAM interface 10. The output RAM 11, the error correction decoding operation circuit (# 1) 12, the input RAM interface 18 inserted between the input RAM 9 and the decoding operation circuit 12, and the decoding operation circuit 12 and the output RAM 11. And an output RAM interface 19 inserted therein.

The input RAM interface 8 takes in the reception data 3 and inputs the reception data 3 to the decoding arithmetic circuit 12 via the input RAM 9 and the input RAM interface 18 and inputs the reception data 3 to the output RAM interface 10 at the subsequent stage.
The decoded signal from the decoding arithmetic circuit 12 is output from the error correction decoding circuit 5 via the output RAM interface 19, the output RAM 11, and the output RAM interface 10.

Since the second and third stage error correction decoding circuits 6 and 7 have the same configuration as the first stage error correction decoding circuit 5, the RAM interface, the input interface, and the output interface in the error correction decoding circuits 6 and 7 The sign of is omitted.
However, the decoding arithmetic circuit (# 1) 12, the decoding arithmetic circuit (# 2) 13, and the decoding arithmetic circuit (# 3) 14 in the error correction decoding circuits 5, 6, and 7 each hold different unique information. Suppose you are.

Next, the operation of the error correction decoding apparatus 1 according to the first embodiment of the present invention shown in FIG. 1 will be described with reference to the timing chart of FIG.
In FIG. 2, the control signal 2 is input to the error correction decoding apparatus 1 once for every three codewords (three pieces of received data 3), and contributes to the identification of the head of the code sequence. Numbers C1, C2,..., C9 of the received data 3 of the correction code sequence indicate codeword numbers.

  In FIG. 2, when error correction decoding circuits 5, 6, and 7 having a throughput capability lower than that of the transmission speed of the digital transmission system are connected in cascade, the transmission speed of the desired digital transmission system. Shows the actions to make it possible to achieve.

Each error correction decoding circuit 5, 6, 7 receives a head signal pulse of the control signal 2, and based on the individual information held by each decoding arithmetic circuit 12, 13, 14, a code input within the head signal pulse period Recognize what number of words to decode.
For example, each error correction decoding circuit 5, 6, 7 counts the number of inputs from the head pulse, and recognizes a predetermined code word in charge of received data 3.

In the operation example of FIG. 2, first, the error correction decoding circuit 5 takes in data corresponding to the code word C1 from the received data 3 from the input RAM interface 8 simultaneously with the head pulse of the control signal 2, and takes in the code word C1 taken in. Are stored in the input RAM 9.
In the following description, the delimiter between each received data 3 and the corrected data is abbreviated as a code word CX. Here, “X” is an integer arranged in time series, and X = 1, 2,..., 9 in FIG.

  The code word C1 stored in the input RAM 9 is input to the decoding arithmetic circuit 12 via the input RAM interface 18, and decoding processing is performed. At this time, the decoding processing time is set so that it can be completed before the next codeword C4 is input, and the decoding result is temporarily stored in the output RAM 11 via the output RAM interface 19.

The input RAM interface 8 and the input RAM interface 18 can operate in the same order or in different orders.
Therefore, by changing the input order of the input RAM interfaces 8 and 18, it is possible to apply interleaving for burst error tolerance and simplify the arithmetic processing in the decoding arithmetic circuit 12.

  In FIG. 1, the input RAM interface 8 and the input RAM interface 18 are shown as separate circuit elements. However, in terms of mounting, the input RAM interface 8 and the input RAM interface 18 have a configuration in which two input / output lines are provided in a common RAM interface circuit. Also good.

  The output RAM interface 10 in the error correction decoding circuit 5 receives the input signal from the input RAM interface 8 and the input signal from the output RAM 11, and based on the individual information in the decoding arithmetic circuit 12, the input RAM interface 8 The codewords other than the codewords C1, C4, and C7 to be captured are passed through and output to the error correction decoding circuit 6 at the next stage (second stage).

  That is, the output RAM interface 10 takes the code word C4 from the input RAM interface 8 and replaces the decoded result (corrected data) of the code word C1 previously decoded from the output RAM 11 with the next stage ( It is output to the error correction decoding circuit 6 in the second stage).

Note that the output RAM interface 19 and the output RAM interface 10 can operate in the same order or in different orders.
Therefore, by changing the input order of the output RAM interfaces 19 and 10, it is possible to perform interleaving for burst error tolerance and simplify the arithmetic processing in the decoding arithmetic circuit 12.

As the configuration of the error correction decoding circuit 5, it is preferable to perform inverse conversion of each input signal in accordance with the change of the input order between the input RAM interface 8 and the input RAM interface 18.
Further, in FIG. 1, the output RAM interface 19 and the output RAM interface 10 are shown as separate circuit elements. However, in terms of mounting, the common RAM interface circuit has two input / output lines. Also good.

The error correction decoding circuit 6 at the second stage performs the same operation as the error correction decoding circuit 5 on the code words C2, C5, and C8 in the received data 3 based on the individual information in the decoding arithmetic circuit 13. .
The error correction decoding circuit 7 at the third stage performs the same operation as the error correction decoding circuit 5 on the code words C3, C6, and C9 in the received data 3 based on the individual information in the decoding operation circuit 14. I do.

  However, in the error correction decoding circuits 5 and 6, the code word passed through the RAM output interface may be the result (corrected data) of the error correction decoding circuit up to the previous stage.

  The output signal of the error correction decoding circuit 7 at the third stage is input to the output interface 15, and the output interface 15 is controlled with one pulse every three codewords as in the case of the control signal 2 and the received data 3. While outputting the output signal 16, the corrected data 17 after the error correction result is output.

  In FIG. 1, the decoding operation circuits 12, 13, and 14 in each error correction decoding circuit 5, 6, 7 are configured to hold individual unique information, but each error correction decoding circuit 5, 6, It is also possible to realize the same operation as that of FIG. 2 by providing each of the error correction decoding circuits 5, 6, and 7 with the unique information from the outside, with 7 having completely the same configuration.

In the operation example of FIG. 2, the control signal 2 is given a pulse every three codewords to identify the codeword in which each error correction decoding circuit 5, 6, 7 operates. It is also possible to give an identification number from the outside and make each error correction decoding circuit 5, 6, 7 discriminate. In this case, it is possible to operate even with pulse input for each code word.
In short, various types of control signals 2 can be used as long as each error correction decoding circuit 5, 6 and 7 can identify the codeword in charge of processing.

  As described above, the error correction decoding apparatus 1 (error correction decoding method) according to Embodiment 1 (FIGS. 1 and 2) of the present invention includes a plurality of error correction decoding circuits 5 connected in cascade on input data lines, 6 and 7, and each of the plurality of error correction decoding circuits 5, 6, and 7 is configured to process each encoded sequence to process one encoded sequence for the input common reception data 3 and control signal 2. Arithmetic circuit 12, 13, 14 has individual unique information. Based on control signal 2 and unique information, predetermined input data is fetched from received data 3 and a specific part is selected and acquired from an input code sequence. Perform error correction decoding.

  Each of the plurality of error correction decoding circuits 5, 6, and 7 takes in predetermined input data from the received data 3, and simultaneously converts the corrected data after error correction decoding processing into an error in the next stage in place of the input signal. Output as received data to the correction decoding circuit.

  That is, the error correction decoding circuits 5, 6, and 7 connected in cascade with respect to the input data line respectively receive a plurality of code sequences from the fixed period leading signals corresponding to the plurality of code sequences input sequentially. A code sequence different from the head signal is taken in, replaced with the decoded code sequence instead of the fetched code sequence, and other code sequences are left as they are, and the code sequence is sent to the error correction decoding circuit in the next stage. Is configured to pass.

In this way, individual information is given to each of the error correction decoding circuits 5, 6, 7 using the low-speed error correction decoding circuits 5, 6, 7, and a code word is selected and input from a plurality of code word sequences. By decoding and outputting the preceding decoding result in place of the input codeword sequence, even if low-speed error correction decoding circuits 5, 6 and 7 are used, it corresponds to the error correction decoding processing of the high-speed digital transmission system can do.
In addition, since the number of connection signals can be reduced, circuit division in the FPGA can be easily realized.

The configuration of FIG. 1 can be applied to any decoding method as a decoding method of an error correction code. In particular, a turbo code, an LDPC (Low-Density Parity-Check) code, or the like can be applied to a received sequence. This is effective when iterative decoding is performed.
In this case, the number of dependent connections of the error correction decoding circuit can be easily expanded in accordance with the required processing time depending on the number of repetitions.

  The corrected data 17 is output at a data transmission rate at which the parity part of the error correction code is also output. By replacing the parity part with monitor information relating to the decoding result (such as the number of correction bits), the signal line is output. The correction status can be notified later without increasing the number.

Next, the replacement output of the monitor information will be described more specifically with reference to FIG.
FIG. 3 is an explanatory diagram schematically showing the monitor information replacement output, in which an explanation block regarding the monitor information replacement output is added to the input / output unit of the error correction decoding apparatus 1 of FIG.

In FIG. 3, a received data frame structure 50 indicates a frame structure of received data 3 to be decoded by the error correction decoding apparatus 1, and includes codewords C1, C2, and C3.
The received data frame structure 50 includes an information sequence area 51 of the code word C1, an information sequence area 52 of the code word C2, an information sequence area 53 of the code word C3, a parity sequence area 54 of the code word C1, and a code word C2. Parity sequence region 55 and a parity sequence region 56 of codeword C1.

The corrected data frame configuration 60 indicates the frame configuration of the corrected data 17 decoded by the error correction decoding apparatus 1.
The corrected data frame structure 60 has the same structure as the received data frame structure 50, and monitor information replacement areas 57, 58, and 59 are provided in a part of the parity sequence areas 54, 55, and 56, respectively.

In FIG. 3, each input signal in the received data 3 and the corrected data 17 can be configured as either a serial input or a parallel input. However, in order to simplify the description, it is assumed that the input signal is a parallel input.
In addition, although interleaving or the like can be applied, in order to simplify the description, it is assumed that output is performed in the same manner as that time series without replacing the input time series.

As described above, the information sequence region 51 and the parity sequence region 54 of the codeword C1 included in the received data frame structure 50 are taken into the first-stage error correction decoding circuit 5 and decoded.
Similarly, the information sequence region 52 and the parity sequence region 55 of the code word C2 are taken into the error correction decoding circuit 6 at the second stage and decoded, and the information sequence region 53 and the parity sequence region 56 of the code word C3 are The data is taken into the third stage error correction decoding circuit 7 and decoded.

  Normally, monitor information related to decoding results (such as the number of correction bits) by the error correction decoding circuits 5, 6 and 7 can be obtained by providing signal lines for monitor information in the error correction decoding circuits 5, 6 and 7, respectively. Although it is obtained via a signal line, if the number of error correction decoding circuits increases, the number of output signal lines from the error correction decoding apparatus 1 also needs to be increased, which is not practical.

  Therefore, in the first embodiment of the present invention, in order to suppress the number of signal lines for monitor information, as shown in FIG. 3, in the corrected data frame configuration 60, each parity sequence area 54, 55, 56 is stored. A part is replaced with monitor information related to the decoding result (such as the number of correction bits) and output.

  Of the corrected data 17, the parity sequence is not required after the information sequence is decoded and the estimated information sequence is calculated. In Embodiment 1 of the present invention, the parity sequence is used to match the data transmission rate. A sequence decoding result (or a sequence replaced with a dummy sequence) is output.

In the post-correction data frame configuration 60 shown in FIG. 3, the monitor information related to the error correction decoding circuit 5 at the first stage is embedded in the monitor information replacement area 57 and included in the post-correction data 17 and output.
Similarly, monitor information related to the second-stage error correction decoding circuit 6 is embedded in the monitor information replacement area 58, and monitor information related to the third-stage error correction decoding circuit 7 is embedded in the monitor information replacement area 59. Are included in the corrected data 17 and output.
Thereby, the correction status can be notified to the subsequent stage without increasing the number of signal lines.

Embodiment 2. FIG.
In the first embodiment (FIG. 1), the input RAM interface 8 and the output RAM interface 10 are provided on the same data bus. However, as shown in FIG. 4, they are provided individually on independent data lines. Also good.

FIG. 4 is a block diagram showing a configuration example of an error correction decoding apparatus 1A according to Embodiment 2 of the present invention. The same components as those described above (see FIG. 1) are denoted by the same reference numerals as those described above, or A detailed description will be omitted by adding “A” after the reference numeral.
4 is different from the above (FIG. 1) only in that the input RAM interface 8 and the output RAM interface 10 are not connected in cascade and are provided on independent data lines.

The operation of error correction decoding apparatus 1A according to Embodiment 2 of the present invention shown in FIG. 4 will be described below with reference to the timing chart of FIG.
Each circuit operation, each data, and each signal shown in FIG. 5 are the same as those described above (FIG. 2).

  In FIG. 5, when the error correction decoding circuits 5A, 6A, and 7A having a throughput capability slower than the above (in the case of FIG. 1) with respect to the transmission speed of the digital transmission system are connected in cascade, the desired digital The operation for enabling the transmission rate of the transmission system to be achieved is shown.

  In FIG. 5, first, the error correction decoding circuit 5A writes the code word C1 to the input RAM 9 via the input RAM interface 8 and writes the code word C1 to the decoding arithmetic circuit 12 via the input RAM interface 18 as described above. The data is input and decoded, and the error correction result (corrected data) is written to the output RAM 11 via the output RAM interface 19.

  At this time, in the configuration described above (FIGS. 1 and 2), the error correction result needs to be written to the output RAM 11 before the next code word C4 is fetched. According to the configuration of FIG. Before the error correction decoding process is started in the decoding arithmetic circuit 12 for the code word C4, the writing of the error correction result in the output RAM 11 may be completed.

Next, the RAM output interface 10 outputs the error correction result (corrected data) written in the output RAM 11.
At this time, the output start timing of the error correction result is arbitrary, and it is not necessary to synchronize with the control signal 2. However, output data from the other error correction decoding circuits 6A and 7A can also be output on the same data line. As a burst output.

  For the RAM output interface 10 in the error correction decoding circuit 5A in the first stage (no error correction decoding circuit in the previous stage), as shown in FIG. 4 and FIG. Or the like, and the error correction decoding result is replaced at a predetermined timing.

The output signal of the error correction decoding circuit 7A at the third stage (the last of the cascade connection) is output from the error correction decoding apparatus 1A as the corrected data 17 after the error correction result via the output interface 15 as described above. The
In addition, about the setting method of each specific information, and the input method of the control signal 2, it can operate | move with another control method similarly to the above-mentioned.

As described above, according to the error correction decoding apparatus 1A (error correction decoding method) according to the second embodiment (FIGS. 4 and 5) of the present invention, the error is even slower than in the case of the first embodiment. Correction decoding circuits 5A, 6A, and 7A are connected in cascade, and individual information is given to each of the error correction decoding circuits 5A, 6A, and 7A. Each of the plurality of error correction decoding circuits 5A, 6A, and 7A The later corrected data is output to a signal line different from the input data line of the reception data 3.
That is, each of the correction decoding circuits 5A, 6A, and 7A connected in cascade to the input data line selects and inputs a code word from a plurality of code word sequences, and decodes the decoding result separately from the input data line. Output to the signal line.

As a result, even if an error correction decoding circuit having a lower speed than that described above is used, the error correction decoding process of the high-speed digital transmission system can be handled.
Further, according to the configuration of FIG. 4, since the input signal before correction and the output signal of the correction result are separated, the output RAM 11 can be used to output an unnecessary parity part in the output signal of the correction result. It is also possible to output after converting the information transmission rate.

Further, the post-correction data 17 replaces and outputs monitor information related to the decoding result (correction bit number, etc.) in the parity part, as in the first embodiment (FIG. 3), without increasing the number of signal lines. The correction status can be notified later.
Further, with respect to the parity sequence areas 54, 55, and 56 in FIG. 3, it is possible to secure only the monitor information replacement areas 57, 58, and 59 and perform speed conversion without outputting other unnecessary parity sequence areas. It is.

Embodiment 3 FIG.
In Embodiments 1 and 2 (FIGS. 1 to 5), the error correction decoding apparatus and method have been described. However, as shown in FIG. 6, the error correction encoding apparatus 21 and the error correction have almost the same configuration. An encoding method can be realized.

FIG. 6 is a block diagram showing a configuration example of the error correction coding apparatus 21 according to the third embodiment of the present invention. The same components as those described above (see FIG. 1) are denoted by the same reference numerals as those described above. The description is omitted.
In FIG. 6, the error correction coding apparatus 21 includes an input interface 4, a plurality (three) of error correction coding circuits 25, 26, and 27 connected in cascade on input data lines, and an output interface 15. Yes.

The input interface 4 receives the control signal 2 indicating the head of the code sequence and a plurality of information data 23 for transmission, and inputs them to the error correction coding circuit 25 at the first stage.
The error correction encoding circuits 25, 26, and 27 each have a similar circuit configuration, and sequentially encode input signals.

  The error correction encoding circuit 27 at the third stage outputs the control output signal 16 indicating the head of the code sequence and the encoded data 37 after the error correction result via the output interface 15.

  The first-stage error correction coding circuit 25 is connected to the input RAM interface 8 and output RAM interface 10 connected in series on the transmission data line, the input RAM 9 connected to the input RAM interface 8, and the output RAM interface 10. The output RAM 11, the error correction encoding operation circuit (# 1) 32, the input RAM interface 18 inserted between the input RAM 9 and the encoding operation circuit 32, the encoding operation circuit 32, and the output RAM 11 And an output RAM interface 19 inserted between them.

  The error correction encoding device 21 of FIG. 6 includes substantially the same components as the error correction decoding device 1 described above (FIG. 1), but the point that the information data 23 is input to the input interface 4, The error correction coding circuits 25, 26, 27 are connected in cascade, and each error correction coding circuit 25, 26, 27 is composed of an encoding operation circuit (# 1) 32, an encoding operation circuit (# 2) 33, The difference is that the encoding operation circuit (# 3) 34 is provided and the encoded data 37 is output from the output interface 15.

  That is, the error correction encoding device 21 (error correction encoding method) shown in FIG. 6 replaces the received data 3 with the information data 23 and replaces the decoding arithmetic circuits 12, 13, and 14 with the encoding arithmetic circuit 32, This can be easily realized by replacing the corrected data 17 with the encoded data 37.

Next, the operation of error correction coding apparatus 21 according to Embodiment 3 of the present invention shown in FIG. 6 will be described with reference to the timing chart of FIG.
Each circuit operation, each data, and each signal shown in FIG. 7 are substantially the same as those described above (FIG. 2), but the information data 23, each error correction coding circuit 25, 26, 27, each coding operation circuit 32, The portions corresponding to 33 and 34 and the encoded data 37 are different from those described above.

  In FIG. 7, when error correction coding circuits 25, 26, and 27 having a throughput capability lower than the transmission speed of the digital transmission system are connected in cascade, the transmission speed of the desired digital transmission system is shown. The actions to make it achievable are shown.

  In FIG. 7, each error correction coding circuit 25, 26, 27 receives the head signal pulse of the control signal 2, and based on the individual information held by each coding operation circuit 32, 33, 34, the head signal pulse period. It recognizes what number of codewords to be decoded.

  Here, the handling of the control signal 2 and the information data 23, and the operations of the input RAM interface 8 and the input RAM 9 in the error correction coding circuit 25 are the same as those in the first embodiment, and the description thereof will be omitted. .

  The code word C1 stored in the input RAM 9 is input to the encoding operation circuit 32 via the input RAM interface 18, and the encoding process is performed. At this time, the encoding processing time is set so that it can be completed before the next codeword C4 is input, and the encoding result is temporarily stored in the output RAM 11 via the output RAM interface 19.

Note that the input order of the input RAM interface 8 and the input RAM interface 18 can be operated in the same order or different orders as described above.
Therefore, by changing the input order of the input RAM interfaces 8 and 18, it is possible to perform interleaving for burst error tolerance and simplify the arithmetic processing in the encoding arithmetic circuit 32. This input order may be different from the order of the error correction decoding apparatus 1 described above.

  In FIG. 6, the input RAM interface 8 and the input RAM interface 18 are shown as separate circuit elements. However, in terms of mounting, the input RAM interface 8 and the input RAM interface 18 are configured by providing two input / output lines in a common RAM interface circuit. Also good.

  The output RAM interface 10 receives the input signal from the input RAM interface 8 and the input signal from the output RAM 11, and based on the individual information in the encoding arithmetic circuit 32, the code words C1 and C4 that the input RAM interface 8 takes in , Code words other than C7 are passed through and output to the error correction encoding circuit 26 in the next stage (second stage).

  That is, the output RAM interface 10 takes the code word C4 from the input RAM interface 8 and replaces the encoded result of the code word C1 encoded earlier from the output RAM 11 with the second-stage error correction code. To the circuit 26.

As described above, the output RAM interface 19 and the output RAM interface 10 can operate in the same order or in different orders.
Therefore, by changing the output order of the output RAM interfaces 19 and 10, it is possible to perform interleaving for burst error tolerance and to simplify the arithmetic processing in the encoding arithmetic circuit 32.

  Further, as the configuration of the error correction coding circuit 25, it is preferable to perform inverse conversion of each input signal in accordance with the change of the input order between the input RAM interface 8 and the input RAM interface 18. The output order may be different from that of the error correction decoding apparatus 1 described above.

Further, in FIG. 6, the output RAM interface 19 and the output RAM interface 10 are shown as individual circuit elements. However, in terms of mounting, the common RAM interface circuit has two input / output lines. Also good.
The arithmetic operation in the second and third stage error correction encoding circuits 26 and 27 and the handling of the operation target code word are the same as those of the error correction decoding circuits 6 and 7 described above, and thus the description thereof is omitted.

  As described above, the error correction coding device 21 (error correction coding method) according to the third embodiment (FIGS. 6 and 7) of the present invention has a plurality of error correction codings connected in cascade on the input data line. Circuits 25, 26, and 27, and each of the plurality of error correction encoding circuits 25, 26, and 27 processes one encoded sequence for the input common information data 23 and control signal 2. It has individual unique information, and based on the control signal 2 and the unique information, takes predetermined input data from the information data 23, selects and acquires a specific part from the input code sequence, and performs error correction coding processing.

  Each of the plurality of error correction encoding circuits 25, 26, 27 takes in predetermined input data from the information data 23 and simultaneously converts the encoded data after error correction encoding processing into the next stage in place of the input signal. Is output as information data for the error correction coding circuit.

  That is, each of the error correction encoding circuits 25, 26, and 27 connected in cascade with respect to the input data line has a plurality of codes for a fixed-cycle head signal corresponding to a plurality of code sequences that are sequentially input. The code sequence that is different from the first signal is taken from the sequence, replaced with the code sequence after the error correction coding process instead of the imported code sequence, and the other code sequences are left as they are, and the next stage error correction coding is performed. It is configured to pass a code sequence to the circuit.

In this way, individual information is given to each of the error correction encoding circuits 25, 26, and 27 using the low-speed error correction encoding circuits 25, 26, and 27, and a code word is selectively input from a plurality of code word sequences. Thus, an error in the high-speed digital transmission system can be obtained even if the low-speed error correction encoding circuits 25, 26, and 27 are used by outputting the previous encoding result instead of the input codeword sequence. It is possible to deal with correction encoding processing.
In addition, since the number of connection signals can be reduced, circuit division in the FPGA can be easily realized.

Embodiment 4 FIG.
In the third embodiment (FIG. 6), the input RAM interface 8 and the output RAM interface 10 are provided on the same data line. However, as shown in FIG. 8, they may be provided individually on independent data lines. Good.

FIG. 8 is a block diagram showing a configuration example of the error correction coding apparatus 21A according to the fourth embodiment of the present invention. The same components as those described above (see FIG. 6) are denoted by the same reference numerals as those described above. Alternatively, “A” is appended after the reference numerals and detailed description is omitted.
8 differs from the above (FIG. 6) only in that the input RAM interface 8 and the output RAM interface 10 are not connected in cascade and are provided on independent data lines.

Next, the operation of error correction coding apparatus 21A according to Embodiment 4 of the present invention shown in FIG. 8 will be described with reference to the timing chart of FIG.
Each circuit operation, each data, and each signal shown in FIG. 9 are the same as those described above (FIG. 7).

  In FIG. 9, when error correction coding circuits 25A, 26A, and 27A having a throughput capability lower than that of the above-described third embodiment (FIG. 6) are connected in cascade with respect to the transmission speed of the digital transmission system. The operation for enabling the transmission speed of the desired digital transmission system to be achieved is shown.

  In FIG. 9, first, the error correction coding circuit 25A writes the code word C1 from the input RAM interface 8 to the input RAM 9 and codes the coding operation circuit 32 from the input RAM interface 18 as in the third embodiment. The word C1 is input to perform the encoding process, and the error correction encoding result (encoded data) is written from the output RAM interface 19 to the output RAM 11.

  At this time, in the configuration described above (FIGS. 6 and 7), it is necessary to complete writing the error correction encoding result in the output RAM 11 before the next code word C4 is fetched. Before the error correction encoding process is started in the encoding arithmetic circuit 32 for the code word C4, the writing of the error correction encoding result (encoded data) into the output RAM 11 may be completed.

Next, the RAM output interface 10 outputs the error correction encoding result (encoded data) written in the output RAM 11 to the error correction encoding circuit 26A of the next stage (second stage).
At this time, the output start timing of the error correction encoding result (encoded data) is arbitrary and does not need to be synchronized with the control signal 2, but the output data from the other error correction encoding circuits 26A and 27A is the same. Burst output so that it can be output on the data line.

  For the RAM output interface 10 in the error correction encoding circuit 25A in the first stage (no error correction encoding circuit in the previous stage), as shown in FIGS. 8 and 9, a fixed value (for example, A configuration is conceivable in which “0” or the like is input and replaced with an error correction coding result at a predetermined timing.

The output signal of the error correction encoding circuit 27A at the third stage (the last of the cascade connection) is output as an encoded data 37 after the error correction encoding result via the output interface 15 as described above. It is output from 21A.
In addition, about the setting method of each specific information, and the input method of the control signal 2, it can operate | move with another control method similarly to the above-mentioned.

  As described above, according to the error correction encoding device 21A (error correction encoding method) according to the fourth embodiment (FIGS. 8 and 9) of the present invention, a plurality of error correction encoding circuits 25A, 26A, and 27A are provided. Each outputs the encoded data after the error correction encoding process to a signal line different from the input data line of the information data 23, so that the error correction encoding is performed at a lower speed than in the case of the third embodiment. Even if the circuits 25A, 26A, and 27A are used, it is possible to cope with error correction coding processing of a high-speed digital transmission system.

Further, according to the configuration of FIG. 8, since the input signal before encoding and the output signal of the encoding result are separated, the information transmission of the information data 22 is performed before being input to the error correction encoding device 21A. It is not necessary to convert the speed in advance to the transmission speed of the encoding result.
Therefore, the output RAM 11 is used to convert the information transmission speed of the information data 22 into the transmission speed of the encoding result in accordance with the parity part included in the encoded data 37 in the output signal of the encoding result. Can also be output.

  1, 1A error correction decoding device, 2 control signal, 3 received data, 4 input interface, 5, 6, 7 error correction decoding circuit, 8, 18 input RAM interface, 9 input RAM, 10, 19 output RAM interface, 11 output RAM, 12, 13, 14, 12A, 13A, 14A Decoding operation circuit, 15 output interface, 16 control output signal, 17 corrected data, 21, 21A error correction coding device, 23 information data, 25, 26, 27, 25A, 26A, 27A Error correction coding circuit, 32, 33, 34 Coding operation circuit, 37 Encoded data, 50 Received data frame configuration, 51, 52, 53 Information sequence area, 54, 55, 56 Parity sequence area, 57, 58, 59 Monitor information replacement area, 60 Data frame configuration after correction.

Claims (14)

An error correction decoding apparatus used in a digital communication system,
A plurality of error correction decoding circuits connected in cascade on the input data line,
Each of the plurality of error correction decoding circuits includes:
In order to process one encoded sequence for input common received data and control signal, it has individual unique information,
Based on the control signal and the unique information, from said received data takes the predetermined input data write Mutotomoni, or recognizes to decode the ordinal number of the code word of the code sequence input, the said code word recognized as decodes An error correction decoding apparatus that performs error correction decoding processing by selectively acquiring from a code sequence .   Each of the plurality of error correction decoding circuits captures predetermined input data from the received data, and at the same time, receives the corrected data after the error correction decoding processing in place of an input signal to the error correction decoding circuit in the next stage. The error correction decoding apparatus according to claim 1, wherein the error correction decoding apparatus outputs the data as data.   2. The error according to claim 1, wherein each of the plurality of error correction decoding circuits outputs the corrected data after the error correction decoding processing to a signal line different from an input data line of the reception data. Correction decoding device.   Each of the plurality of error correction decoding circuits replaces a part of the parity part included in the corrected data after the error correction decoding process with monitor information relating to the decoding result after the error correction decoding process, and outputs the replaced monitor information. The error correction decoding apparatus according to claim 1. An error correction decoding method used in a digital communication system,
A plurality of error correction decoding circuits are connected in cascade,
Giving individual specific information to the plurality of error correction decoding circuits,
Input common received data and control signal to the plurality of error correction decoding circuits,
In each of the plurality of error correction decoding circuit, based on the control signal and the unique information, from said received data takes the predetermined input data write Mutotomoni, recognition or decoding the ordinal number of the code word of the code sequence input An error correction decoding method comprising: performing error correction decoding processing by selectively acquiring the codeword recognized to be decoded from the code sequence .   In each of the plurality of error correction decoding circuits, predetermined input data is captured from the received data, and at the same time, the corrected data after the error correction decoding processing is received by the next stage error correction decoding circuit in place of the input signal. 6. The error correction decoding method according to claim 5, wherein the error correction decoding method is output as data.   6. The error according to claim 5, wherein each of the plurality of error correction decoding circuits outputs the corrected data after the error correction decoding processing to a signal line different from an input data line of the received data. Correction decoding method.   Each of the plurality of error correction decoding circuits replaces a part of the parity part included in the corrected data after the error correction decoding process with monitor information relating to the decoding result after the error correction decoding process, and outputs the replaced monitor information. 6. The error correction decoding method according to claim 5, characterized in that: An error correction coding apparatus used in a digital communication system,
A plurality of error correction coding circuits connected in cascade on the input data line,
Each of the plurality of error correction encoding circuits includes:
In order to process one encoded sequence for the input common information data and control signal, it has individual unique information,
Based on the control signal and the unique information, the Captures the information data a predetermined input data Mutotomoni, or recognized to encode what th code word of the code sequence input, the code word is recognized that encodes An error correction coding apparatus characterized in that an error correction coding process is performed by selectively acquiring a signal from the code sequence .   Each of the plurality of error correction encoding circuits captures predetermined input data from the information data, and at the same time, converts the encoded data after the error correction encoding processing into an error correction encoding of the next stage in place of an input signal. The error correction coding apparatus according to claim 9, wherein the error correction coding apparatus outputs the data as information data for a circuit.   The each of the plurality of error correction encoding circuits outputs the encoded data after the error correction encoding processing to a signal line different from an input data line of the information data. Error correction coding apparatus. An error correction coding method used in a digital communication system,
A plurality of error correction coding circuits are connected in cascade,
Giving individual specific information to the plurality of error correction encoding circuits;
Input common information data and control signals to the plurality of error correction coding circuits,
In each of the plurality of error correction encoding circuit, based on the control signal and the unique information, the information data from the take predetermined input data write Mutotomoni, encodes the ordinal number of the code word of the code sequence input An error correction coding method comprising: performing error correction coding processing by selectively acquiring from the code sequence the codeword recognized to be recognized and encoded.   In each of the plurality of error correction coding circuits, predetermined input data is fetched from the information data, and at the same time, the encoded data after the error correction coding processing is replaced with an error correction coding in the next stage instead of the input signal. 13. The error correction coding method according to claim 12, wherein the error correction coding method is output as information data for a circuit.   13. The encoded data after the error correction encoding process is output to a signal line different from an input data line of the information data in each of the plurality of error correction encoding circuits. Error correction coding method.

Images