JP5486498B2 - Semiconductor device and manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

  As MISFETs (Metal Insulator Semiconductor Field Effect Transistors) are miniaturized, variations in their electrical characteristics tend to increase. There are microscopic variations in impurities implanted to give the transistor desired performance. For this reason, it is known that the random variation of the transistors increases especially when the gate size of the MISFET is reduced. Here, the gate dimension means an area given by the product of the length and width of the channel portion controlled by the gate electrode.

  Cell transistors used in SRAM (Static Random Access Memory) and DRAM (Dynamic Random Access Memory) are designed near the minimum dimension in the process. Therefore, the influence of random variation as described above is the largest. In order to improve the variation or the driving capability of the transistor, the gate width is increased. Then, since the area occupied by one memory element (hereinafter referred to as cell size) increases, the merit of scaling cannot be enjoyed.

  As described above, when the planar MISFET formed on the semiconductor substrate plane is used, it is difficult to further improve the integration degree of the SRAM and the DRAM.

  One method for dealing with such a problem is to increase the effective channel area. For example, Japanese Patent Application Laid-Open No. 2007-27502 discloses an example of the following semiconductor device. In this semiconductor device, the height of the surface of the STI (Shallow Trench Isolation) insulating film differs between the logic portion and the memory portion, and the STI insulating film surface is formed lower than the semiconductor surface in the memory portion. FIG. 9 shows a cross-sectional view of the channel region of the MISFET. FIG. 9 is a cross-sectional view of the semiconductor device 50 cut perpendicularly to the direction in which the source / drain current passes. The semiconductor device 50 includes a semiconductor element (MISFET) 50a in a logic part and a semiconductor element (MISFET) 50b in a memory part. The respective semiconductor elements 50a and 50b have substantially the same structure. The semiconductor elements 50a and 50b are respectively shallow trenches 504a and 504b, gate insulating films 502a and 502b, and gate electrodes 503a and 503b filled with insulating films (STI insulating films and element isolation insulating films) 501a and 501b on the semiconductor substrate 500. Active regions 505a and 505b and sidewalls 506a and 506b. As shown in FIG. 9, in the MISFET 50b of the memory part, the surface of the insulating film 501b is dug down lower than the surface of the semiconductor substrate 500. By extending the gate insulating film 502b and the gate electrode 503b in that region, a channel can be formed also on the side surface of the element isolation region. In this way, in addition to the original gate width W, the gate width increases by the length 2ΔW of the side region. Therefore, the effective gate width can be increased without increasing the planar area of the MISFET.

JP 2007-27502 A

  However, when the STI insulating film 501b is dug as shown in FIG. 9, unevenness is generated on the surface of the gate electrode 503b formed after the STI insulating film 501b is formed. Therefore, there is a problem that the focus margin in the lithography process following this process is reduced. Thus, when the STI insulating film surfaces have different heights in the memory portion and the logic portion, it is extremely difficult to process the gate electrodes of the memory portion and the logic portion into desired shapes by the same lithography process. difficult.

  As described above, the conventional planar MISFET has a problem that random variation increases due to scaling, and it is difficult to further improve the integration degree of SRAM and DRAM. Also, considering the use of the side surface region in the gate width direction of the MISFET as a channel, the influence of random variation is improved. However, the method of changing the height of the STI insulating film surface between the logic portion and the memory portion has a problem that the processing accuracy of lithography is deteriorated and it becomes difficult to process the gate electrode into a desired shape.

  The present invention has been made in view of such problems, and by using the side region of the active region partitioned by the element isolation insulating film as a channel without changing the height of the surface of the embedded insulating film, An object of the present invention is to provide a semiconductor device capable of increasing the effective channel width of a field emission transistor and a method for manufacturing the same.

To achieve the above object, a semiconductor device according to a first aspect of the present invention includes a semiconductor substrate having a first region and a second region, and a first formed in the first region of the semiconductor substrate. An active region of the semiconductor substrate, a second active region formed in the second region of the semiconductor substrate, a first groove formed in the first region and defining the first active region, A second groove defined in the second region and defining the second active region; a first element isolation insulating film embedded in the first groove; and embedded in the second groove A recess is formed in a portion adjacent to the second active region, and a bottom of the recess is formed in the second element isolation insulating film. , it is formed at a position lower than the portion adjacent to said first active region of said first element isolation insulating film Further, in the first region, logic circuits are formed, the second region, the memory circuit is formed, characterized in that.
In order to achieve the above object, a semiconductor device according to a second aspect of the present invention includes a semiconductor substrate having a first region and a second region, and a first region formed in the first region of the semiconductor substrate. An active region of the semiconductor substrate, a second active region formed in the second region of the semiconductor substrate, a first groove formed in the first region and defining the first active region, A second groove defined in the second region and defining the second active region; a first element isolation insulating film embedded in the first groove; and embedded in the second groove A recess is formed in a portion adjacent to the second active region, and a bottom of the recess is formed in the second element isolation insulating film. And formed at a position lower than a portion of the first element isolation insulating film adjacent to the first active region. Further, wherein the first region, logic circuits are formed, the second region, Static Random Access Memory circuits are formed, characterized in that.

In order to achieve the above object, a method of manufacturing a semiconductor device according to a third aspect of the present invention defines a step of preparing a semiconductor substrate having a first region and a second region, and a first active region. Forming a first groove portion in the first region of the semiconductor substrate and a second groove portion defining a second active region in the second region of the semiconductor substrate; and Forming a first element isolation insulating film in the groove portion and a second element isolation insulating film in the second groove portion, and forming the groove portion on the surface of the semiconductor substrate. A step of sequentially forming one insulating film and a second insulating film; and etching the first insulating film, the second insulating film, and the semiconductor substrate to form the first region on the semiconductor substrate And a groove in each of the second regions Includes a step of forming, a step of forming the element isolation insulating film, forming a mask on said semiconductor substrate, of the mask to form an opening in a portion corresponding to the first region A step of isotropically etching the second insulating film using the mask; a step of removing the mask; and the second insulation of the first region and the second region. Etching the film isotropically; forming a buried insulating film in the trench; and forming a recess in a portion of the second element isolation insulating film adjacent to the second active region ; The bottom of the recess is formed at a position lower than the portion of the first element isolation insulating film adjacent to the first active region .
To achieve the above object, a method of manufacturing a semiconductor device according to a fourth aspect of the present invention defines a step of preparing a semiconductor substrate having a first region and a second region, and a first active region. Forming a first groove portion in the first region of the semiconductor substrate and a second groove portion defining a second active region in the second region of the semiconductor substrate; and Forming a first element isolation insulating film in the groove portion and a second element isolation insulating film in the second groove portion, and forming the groove portion on the surface of the semiconductor substrate. A step of sequentially forming one insulating film and a second insulating film; and etching the first insulating film, the second insulating film, and the semiconductor substrate to form the first region on the semiconductor substrate And a groove in each of the second regions And forming the element isolation insulating film by forming a first buried insulating film on the surface of the semiconductor substrate, and further completely burying the groove by the second buried insulating film A step of planarizing the first and second buried insulating films using the second insulating film as an etching stopper, and forming a resist pattern having an opening only in the second region on the semiconductor substrate. Selectively etching a part of the first buried insulating film using the resist pattern as a mask; removing the second insulating film after removing the resist pattern; and Introducing an impurity into the semiconductor substrate using an insulating film as a sacrificial film; and removing the first buried insulating film exposed on the surface; Forming a gate oxide film on the conductor substrate; and forming a recess in a portion adjacent to the second active region of the second element isolation insulating film, and the bottom of the recess includes: The first element isolation insulating film is formed at a position lower than a portion adjacent to the first active region.
In order to achieve the above object, a method of manufacturing a semiconductor device according to a fifth aspect of the present invention defines a step of preparing a semiconductor substrate having a first region and a second region, and a first active region. Forming a first groove portion in the first region of the semiconductor substrate and a second groove portion defining a second active region in the second region of the semiconductor substrate; and After the step of forming the first element isolation insulating film in the groove portion and the second element isolation insulating film in the second groove portion, and the step of forming the element isolation insulating film, the first region is formed in the first region. Forming a logic circuit and forming a memory circuit in the second region, wherein the step of forming the element isolation insulating film is formed in the second active region of the second element isolation insulating film. Form a dent in the adjacent part Includes a step, the bottom of the recess viewed part, the first being formed at a position lower than the portion adjacent to the first active region of the element isolation insulating film, characterized in that.

  According to the present invention, the side region of the active region of the field emission transistor can be used as a channel by providing the recess in the element isolation insulating film in the region adjacent to the active region. Accordingly, it is possible to provide a semiconductor device and a method for manufacturing the same that can increase the effective channel width of the field emission transistor without changing the height of the surface of the element isolation insulating film.

It is sectional drawing which cut | disconnected the semiconductor device which concerns on 1st Embodiment in the gate width direction. It is sectional drawing which cut | disconnected the semiconductor device which concerns on 1st Embodiment in the gate length direction. 1 is a plan view schematically showing a semiconductor device according to a first embodiment. It is a figure which shows the other structural example of the semiconductor device which concerns on 1st Embodiment. It is a figure which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment. It is a figure which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment. It is a figure which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment. It is a figure which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment. It is a figure which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment. It is a figure which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment. It is a figure which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment. It is a figure which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment. It is a figure which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment. It is sectional drawing which cut | disconnected the semiconductor device which concerns on 2nd Embodiment in the gate width direction. It is sectional drawing which cut | disconnected the semiconductor device which concerns on 2nd Embodiment in the gate length direction. It is a figure which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. It is a figure which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. It is a figure which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. It is a figure which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. It is a figure which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. It is a figure which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. It is a figure which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. It is a figure which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. It is a figure which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. It is a figure which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. It is a figure which shows a comparative example.

  A semiconductor device and a semiconductor device manufacturing method according to embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
A semiconductor device and a method for manufacturing the semiconductor device according to the first embodiment will be described below. In the present embodiment, a semiconductor device in which the pullback amount is changed between a logic unit and an SRAM (Static Random Access Memory) unit will be described as an example. In the present embodiment, as will be described later, by reducing the pullback amount of the SRAM portion (memory portion) compared to the pullback amount of the logic portion, the final STI (Shallow Trench Isolation) insulating film recess shape is formed in the SRAM portion. It is possible to dig deeper.

  As shown in FIGS. 1 to 3, the semiconductor device 10 includes a logic unit that is a first region, a memory unit (SRAM unit) that is a second region, and two regions. In the logic portion, a plurality of semiconductor elements 10a are formed, and a logic circuit is formed. Here, the semiconductor element 10a is a MISFET (Metal Insulator Semiconductor Field Effect Transistor). Similarly, a plurality of semiconductor elements 10b are formed in the memory portion, and a memory circuit is formed. Here, the semiconductor element 10b is a MISFET. 1 is a cross-sectional view of the MISFET of the semiconductor device 10 cut in the gate width W direction shown in FIG. 3, and FIG. 2 is a cross-sectional view of the MISFET of the semiconductor device 10 cut in the gate length L direction shown in FIG. FIG. Further, in order to distinguish between the structures of the logic unit and the memory unit, a is added to the end of the code related to the component of the logic unit and b is added to the end of the code related to the component of the memory unit for convenience.

  As shown in FIG. 1, the semiconductor element 10a includes a semiconductor substrate (silicon substrate) 100, a trench (groove) 104a, a thermal oxide film 105a, an element isolation insulating film (buried insulating film) 107a, an active region 108a, A gate insulating film 109a, a depression (depression) 110a, a gate electrode 111a, and a sidewall 112a are provided. As shown in FIG. 2, the semiconductor element 10a includes a drain region 113a, a drain electrode 114a, a source region 115a, a source electrode 116a, a silicide layer 117a, an Extension / Halo diffusion layer 118a, and the like.

  The semiconductor substrate 100 is a silicon substrate, and includes a trench 104a, an active region 108a, a gate insulating film 109a, and a thermal oxide film 105a on the upper surface of the semiconductor substrate 100.

  As shown in FIG. 3, the trench 104a formed in the semiconductor substrate 100 partitions the semiconductor element 10a and is separated from other adjacent semiconductor elements. The trench 104a includes an element isolation insulating film 107a inside thereof.

  The thermal oxide film 105a is made of a silicon oxide film and is provided on the surface of the trench 104a.

  The element isolation insulating film (buried insulating film) 107a is made of a silicon oxide film and fills the trench 104a. A region of the element isolation insulating film 107a that is in contact with the thermal oxide film 105a has a recess (depression) 110a. The recessed portion 110a exposes the thermal oxide film 105a in a region corresponding to the opening of the trench 104a. In the semiconductor element 10a shown in FIG. 1, the case where the depression 110a is formed is described as an example. However, the semiconductor element 10a does not need to have the depression 110a as shown in FIG. . Further, as shown in FIG. 4, the semiconductor element 10a may not include the thermal oxide film 105a.

  The active region 108a is a region on the upper side of the silicon substrate 100 where impurities are diffused, and is defined by the trench 104a. The active region 108a functions as a channel region when a voltage is applied to the gate electrode 111a.

  The gate insulating film 109a is made of a silicon oxide film and is formed on the active region 108a.

  The gate electrode 111a is made of, for example, polysilicon. As shown in FIG. 1, a sidewall 112a made of an insulating material such as a silicon nitride film is formed around the gate electrode 111a.

  The semiconductor element 10b has substantially the same configuration as the semiconductor element 10a, and includes a semiconductor substrate (silicon substrate) 100, a trench (groove) 104b, a thermal oxide film 105b, an element isolation insulating film (buried insulating film) 107b, and an active element. A region 108b, a gate insulating film 109b, a depression (depression) 110b, a gate electrode 111b, and a sidewall 112b are provided. Further, as shown in FIG. 2, the semiconductor element 10b includes a drain region 113b, a drain electrode 114b, a source region 115b, a source electrode 116b, a silicide layer 117b, an Extension / Halo diffusion layer 118b, and the like.

  The difference between the semiconductor element 10a in the logic part and the semiconductor element 10b in the memory part is that the recessed part 110a formed in the element isolation insulating film 107a of the semiconductor element 10a is different from the recessed part 110b formed in the element isolation insulating film 107b. In other words, it is shallow, or the recess 110a is not formed. The element isolation insulating films 107a and 107b have substantially the same height. Thus, by forming the recessed portion 110b deeper than the recessed portion 110a of the logic portion, the amount of exposure of the side region of the trench 104b from the element isolation insulating film 107b can be increased. For this reason, the gate electrode 111b can be extended to the side surface of the active region 108b, and the effective channel width is increased. The horizontal length of the recess 110a is preferably 30 nm or less, and preferably 20 nm or less.

  In particular, in this embodiment, the recess 110a of the element isolation insulating film 107a is shallower than the recess 110b of the element isolation insulating film 107b or does not include the recess 110a. Thus, the effective channel width of the semiconductor element in the memory portion can be increased without changing the height of the element isolation insulating films 107a and 107b between the logic portion and the memory portion.

  Next, the manufacturing process of the semiconductor device according to this embodiment will be described with reference to FIGS. 5A to 5I. 5A to 5I are cross-sectional views in which the MISFET of the semiconductor device is cut in the gate width W direction. For comparison, cross-sectional views of the logic portion and the memory portion are sequentially shown.

  First, as shown in FIG. 5A, a sacrificial oxide film 101 (first insulating film) having a thickness of, for example, about 10 nm is formed on a silicon substrate 100 by a thermal oxidation method. The sacrificial oxide film 101 is made of a silicon oxide film. Further, a silicon nitride film (second insulating film) 102 is formed with a thickness of, for example, 100 nm by a low pressure CVD (Chemical Vapor Deposition) method. Note that the thickness of the silicon nitride film 102 is preferably about 50 nm to 150 nm. Subsequently, resist patterns 103 a and 103 b having openings corresponding to the trenches 104 are formed on the silicon nitride film 102.

Next, a part of the silicon nitride film 102 is removed by anisotropic plasma etching using an etching gas mainly composed of a fluorine-based gas (CHF ₃ , C ₂ F _6, etc.) using the resist patterns 103 a and 103 b as a mask. . As a result, the silicon nitride films 102a and 102b remain in accordance with the resist patterns 103a and 103b. Thereafter, the resist pattern is washed with SPM (sulfuric acid / hydrogen peroxide mixture) and APM (ammonia / hydrogen peroxide mixture). Thereby, the resist pattern is peeled off. Further, the sacrificial oxide film 101 on the silicon substrate 100 is removed by wet etching mainly using a hydrofluoric acid buffer solution.

Next, the silicon substrate 100 is etched by anisotropic plasma etching using an etching gas mainly composed of a chlorine-based gas (CCl ₄ or Cl ₂ ) (trench etching). The etching depth is preferably 200 nm to 400 nm, for example, about 300 nm. Subsequently, by performing thermal oxidation in an oxygen atmosphere, thin thermal oxide films 105a and 105b having a thickness of, for example, several nm are formed on the exposed surfaces of the trenches 104a and 104b, as shown in FIG. 5B. Further, in order to recover the crystallinity and round the corners of the trench, a high temperature annealing of, for example, 1000 ° C. or higher is additionally performed in an oxidizing atmosphere. In addition to the method of forming a thermal oxide film, after cleaning with a hydrofluoric acid-based solution, the crystallinity is restored by reconfiguration of silicon atoms by annealing at about 800 ° C. in a hydrogen atmosphere, and the corners of the trenches 104a and 104b. You can also use the method of rounding parts. In this case, the thermal oxide films 105a and 105b are not formed or become extremely thin as natural oxide films.

  Next, the oxide films 106a and 106b are preferably formed with a thickness of about 50 nm or less, for example, about 10 nm, by a low pressure CVD method. Thereafter, a resist pattern (not shown) is formed only in the memory portion by a lithography process. By etching the oxide film 106a in the logic portion by etching using dilute hydrofluoric acid, the oxide film 106b remains only in the memory portion as shown in FIG. 5C. In this etching step, dry etching that can take a selectivity with the silicon nitride film may be used. Here, since the etching rate of the oxide film 106b is extremely fast (for example, about 10 times) compared to the thermal oxide films 105a and 105b, the thermal oxide films 105a and 105b are hardly etched.

  Next, a part of the silicon nitride film 102a exposed only in the logic portion is isotropically etched by wet etching with phosphoric acid at about 160 ° C., for example (this step is referred to as a first pull back). As shown in FIG. 5D, the first pullback causes the end portion of the silicon nitride film 102a in the logic portion to recede from the corner of the trench 104a by a length W11.

  Next, the resist pattern formed in the memory portion is washed with SPM or the like and peeled off. Further, the oxide film 106b remaining in the memory portion is etched using dilute hydrofluoric acid. At this stage, the silicon nitride films 102a and 102b in the logic part and the memory part are both exposed. Therefore, for example, a part of the silicon nitride films 102a and 102b is additionally etched isotropically by wet etching with phosphoric acid at about 160 ° C. (this process is referred to as a second pull back). By the second pullback, as shown in FIG. 5E, the end portion of the silicon nitride film 102b in the memory portion recedes from the corner of the trench 104b by a length W12. Further, the end portion of the silicon nitride film 102a in the logic portion recedes from the corner of the trench 104a by a length W11 + W12.

  Next, element isolation insulating films 107a and 107b are formed with a thickness of, for example, about 450 nm so as to fill the trenches 104a and 104b by high density plasma (HDP) CVD. Subsequently, baking for modifying the element isolation insulating films 107a and 107b is performed under conditions of, for example, 800 ° C. and about 10 minutes. By baking, the properties of the element isolation insulating films 107a and 107b approach that of the thermal oxide film, and the quality is improved.

  Next, as shown in FIG. 5F, the element isolation insulating films 107a and 107b except for the trench portions are removed by CMP (Chemical Mechanical Polishing) using the silicon nitride films 102a and 102b as etching stoppers.

  Next, as shown in FIG. 5G, the silicon nitride films 102a and 102b are removed by wet etching using phosphoric acid at about 160 ° C., for example. As a result, the element isolation insulating film 107a in the logic portion extends outward from the element isolation region by W11 longer than the corner portion of the trench 104a as compared with the element isolation insulating film 107b in the memory portion.

Subsequently, impurities are implanted into the well and channel region through the sacrificial oxide film 101. The implantation conditions vary depending on the transistor design, but the well depth is controlled to be, for example, about 150 nm and the channel impurity concentration is about 1 × 10 ¹⁷ atm / cm ³ to 1 × 10 ¹⁹ atm / cm ³ . Subsequently, activation and crystal recovery are performed by lamp annealing at about 1000 ° C., for example. As a result, active regions 108a and 108b are formed.

  Thereafter, the sacrificial oxide film 101 is removed by wet etching using a buffered hydrofluoric acid solution. At this time, as shown in FIG. 5H, the element isolation insulating films 107a and 107b are also etched. Thereafter, gate insulating films (oxide films) 109a and 109b are formed by wet annealing at, eg, about 850 ° C., as shown in FIG. 5I. The gate insulating films 109 a and 109 b are formed in order from the high breakdown voltage transistor among the plurality of semiconductor elements 10 a and 10 b constituting the semiconductor device 10. The oxide film thickness of the high voltage transistor is, for example, about 7 nm at the time of 3.3V design. In the core transistor region where the gate oxide films 109a and 109b are thin, the previously formed thick gate insulating films 109a and 109b are etched once with a hydrofluoric acid solution, and then the thin gate insulating films 109a and 109b of 3 nm or less are again formed. Form. In this process, the element isolation insulating films 107a and 107b are further etched to have a final shape. Here, as described above, since the pull back amount of the silicon nitride film 102b in the memory portion is smaller than that in the silicon nitride film 102a in the logic portion, as shown in FIG. 5I, the STI insulating film in the vicinity of the active region 108b in the memory portion. The depression 110b is formed deeper than the depression 110a of the logic part.

  Thereafter, as shown in FIG. 2, gate electrodes 111a and 111b are formed by a known method, and Extension / Halo ions are implanted to form Extension / Halo diffusion layers 118a and 118b. Further, sidewalls 112a and 112b are formed. Next, ions are implanted into the source / drain regions 113a, 113b, 115a, and 115b, and activation annealing is performed to activate the implanted ions. Further, silicide layers 117a and 117b are formed, and drain electrodes 114a and 114b and source electrodes 116a and 116b are provided. The gate insulating films 109a and 109b and the gate electrodes 111a and 111b are formed to extend to the side surfaces of the active regions 108a and 108b exposed by the depressions 110a and 110b. Through these steps, the semiconductor elements 10a and 10b are formed.

  Further, a logic circuit is formed in the logic portion, and a memory circuit is formed in the memory portion. These circuits may be formed simultaneously or separately. In the case of forming separately, for example, after the memory portion is masked and the logic circuit is formed, the mask of the memory portion is removed and the logic portion is masked to form the memory circuit. Or you may form in the reverse order. These circuits can be formed by methods known to those skilled in the art. By such a process, the semiconductor device 10 is formed.

  In the method for manufacturing the semiconductor device 10 of this embodiment, the oxide film 106b is formed only in the memory portion, and the silicon nitride film 102a is etched only in the logic portion. Further, after removing the oxide film 106b in the memory portion, the silicon nitride film 102a in the logic portion and the silicon nitride film 102b in the memory portion are etched. Thereby, the recess 110a of the element isolation insulating film 107a in the logic part can be formed shallower than the recess 110b in the element isolation insulating film 107b of the memory part. Alternatively, the recess 110a can be formed only in the element isolation insulating film 107b of the memory portion without providing the recess 110a in the element isolation insulating film 107a of the logic portion. Therefore, it is possible to provide a semiconductor device in which only the element isolation region adjacent to the active region 108b of the memory portion is dug and the side region of the trench 104b can be used as a channel. In the present embodiment, by limiting the region to be dug to the vicinity of the active regions 108a and 108b, the steps on the surfaces of the gate electrodes 111a and 111b formed thereafter are reduced. Therefore, processing of the gate electrodes 111a and 111b is easy, and the gate processing accuracy can be maintained. As a result, the gate width can be increased while preventing the cell size from increasing, and the driving capability of the cell transistor can be increased accordingly. Furthermore, random variations of cell transistors can be improved.

(Second Embodiment)
A semiconductor device and a method for manufacturing the semiconductor device according to the second embodiment will be described with reference to the drawings. The semiconductor device of this embodiment is different from the semiconductor device of the first embodiment. In this embodiment, the element isolation insulating film embedded in the trench is composed of the first embedded insulating film and the second embedded insulating film. In addition, by etching a part of the first buried insulating film of the memory portion in advance after the CMP process of the element isolation region, the final recess shape of the element isolation insulating film can be deeply digged in the memory portion. There is in point to do.

  As shown in FIGS. 6 and 7, the semiconductor device 20 according to the present embodiment includes two areas, a logic section that is a first area and a memory section (SRAM section) that is a second area. A plurality of semiconductor elements 20a are formed in the logic portion. The semiconductor element 20a is a MISFET (Metal Insulator Semiconductor Field Effect Transistor). Similarly, a plurality of semiconductor elements 20b are formed in the memory portion, and the semiconductor elements 20b are MISFETs. In order to distinguish between the structure of the logic part and the memory part, a is added to the end of the code related to the component of the logic part and b is added to the end of the code related to the component of the memory part for convenience.

  As shown in FIG. 6, the semiconductor element 20a includes a semiconductor substrate (silicon substrate) 200, a trench 204a, a thermal oxide film 205a, a first element isolation insulating film (buried insulating film) 206a, and a second element isolation. An insulating film (buried insulating film) 207a, an active region 209a, a gate insulating film 210a, a depression (depression) 211a, a gate electrode 212a, and a sidewall 213a are provided. Further, as shown in FIG. 7, the semiconductor element 20a includes a drain region 214a, a drain electrode 215a, a source region 216a, a source electrode 217a, a silicide layer 218a, an extension / halo diffusion layer 219a, and the like. In the present embodiment, the element isolation insulating film includes a first element isolation insulating film (buried insulating film) 206a and a second element isolation insulating film (buried insulating film) 207a. The recess 211a is formed in the first buried insulating film 206a and / or the second buried insulating film 207a.

  The semiconductor substrate 200 is a silicon substrate, and a trench 204a, an active region 209a, and a gate insulating film 210a are formed on the upper surface of the semiconductor substrate 200.

  The trench 204a is formed in the semiconductor substrate 200, surrounds the semiconductor element 20a, and is formed so as to be separated from adjacent semiconductor elements. A first element isolation insulating film 206a and a second element isolation insulating film 207a are formed in the trench 204a.

  The thermal oxide film 205a is formed of, for example, a silicon oxide film, and is formed on the surface of the trench 204a.

  The first element isolation insulating film (buried insulating film) 206a is made of, for example, a silicon oxynitride film. Note that the first element isolation insulating film 206a may be an oxide film into which an element other than nitrogen, for example, carbon or fluorine is introduced. As shown in FIG. 6, the first element isolation insulating film 206a is formed so as to cover the surface of the thermal oxide film 205a formed on the surface of the trench 204a.

  The second element isolation insulating film (buried insulating film) 207a is formed of, for example, a silicon oxide film and fills the trench 204a. In the region where the first element isolation insulating film 206a and the second element isolation insulating film 207a are adjacent to the thermal oxide film 205a, a recess (depression) 211a is formed. The recess 211a is formed across the first element isolation insulating film 206a and the second element isolation insulating film 207a or in the first element isolation insulating film 206a. In the semiconductor element 20a shown in FIG. 6, the case where the recess 211a is formed is described as an example. However, the semiconductor element 20a may not include the recess 211a.

  The active region 209a is a region formed on the upper surface of the silicon substrate 200 and in which impurities are diffused. The active region 209a functions as a channel region when a voltage is applied to the gate electrode 210a.

  The gate insulating film 210a is made of, for example, a silicon oxide film, and is formed on the active region 209a surrounded by the trench 204a.

  The gate electrode 212a is made of, for example, polysilicon. As shown in FIG. 6, a sidewall 213a made of an insulating material such as a silicon nitride film is formed around the gate electrode 212a.

  The semiconductor element 20b has substantially the same configuration as the semiconductor element 20a, and includes a semiconductor substrate (silicon substrate) 200, a trench 204b, a thermal oxide film 205b, a first element isolation insulating film 206b, and a second element isolation insulation. A film 207b, an active region 209b, a gate insulating film 210b, a depression (depression) 211b, a gate electrode 212b, and a sidewall 213b are provided. As shown in FIG. 7, the semiconductor element 20b includes a drain region 214b, a drain electrode 215b, a source region 216b, a source electrode 217b, a silicide layer 218b, an Extension / Halo diffusion layer 219b, and the like. In the semiconductor element 20b, the recess 211b is formed across the first element isolation insulating film 206b and the second element isolation insulating film 207b.

  The difference between the semiconductor element 20a in the logic portion and the semiconductor element 20b in the memory portion is that the depth of the recessed portion 211a of the semiconductor element 20a is the recessed portion 211b formed in the second element isolation insulating film 207b of the semiconductor element 20b. This is in that the depth is less than the depth or the recess 211a is not formed. Note that the heights of the second element isolation insulating films 207a and 207b are substantially the same. Thus, by forming the recessed portion 211b of the memory portion deeper than the recessed portion 211a of the logic portion, the region near the opening of the trench 204b can be dug down. Thereby, the gate insulating film 210b can be formed in a region surrounded by the trench 204b on the semiconductor substrate 200 and a region near the opening of the trench 204b, and the effective channel width of the semiconductor element 20b is increased. Can do. Further, in this embodiment, the effective channel width of the semiconductor element in the memory unit is increased without changing the height of the insulating films of the second element isolation insulating films 207a and 207b between the logic unit and the memory unit. be able to.

  Hereinafter, a method for manufacturing the semiconductor device according to the present embodiment will be described with reference to FIGS. 8A to 8J. 8A to 8J are cross-sectional views in which the MISFET of the semiconductor device is cut in the gate width direction. For comparison, cross-sectional views of the logic portion and the memory portion are sequentially shown.

  First, as shown in FIG. 8A, a sacrificial oxide film (first insulating film) 201 having a thickness of, for example, about 10 nm is formed on a silicon substrate 200 by a thermal oxidation method. Subsequently, a silicon nitride film (second insulating film) 202 is formed on the sacrificial oxide film 201 by low pressure CVD. The thickness of the silicon nitride film 202 is preferably about 50 nm to 150 nm, and is formed to a thickness of about 100 nm, for example. Next, resist patterns 203 a and 203 b having openings corresponding to the element isolation regions are formed on the silicon nitride film 202.

Next, a part of the silicon nitride film 202 is removed by anisotropic plasma etching using an etching gas mainly containing a fluorine-based gas (CHF ₃ , C ₂ F _6, etc.) using the resist patterns 203 a and 203 _b as a mask. . Thereby, the silicon nitride films 202a and 202b remain according to the resist patterns 203a and 203b. Thereafter, the resist patterns 203a and 203b are peeled off by cleaning using SPM (sulfuric acid / hydrogen peroxide solution) and APM (ammonia / hydrogen peroxide solution). Further, the sacrificial oxide film 201 is removed by wet etching mainly using a hydrofluoric acid buffer solution.

Subsequently, the silicon substrate 200 is etched (trench etching) by anisotropic plasma etching using an etching gas mainly composed of chlorine-based gas (CCl ₄ or Cl ₂ ) to form trenches 204a and 204b. The etching depth is preferably about 200 nm to 400 nm, for example, about 300 nm. Subsequently, by performing thermal oxidation in an oxygen atmosphere, thin thermal oxide films 205a and 205b having a thickness of about several nm are formed on the exposed surfaces of the trenches 204a and 204b, as shown in FIG. 8B. Further, in order to recover the crystallinity and round the corners of the trench, a high temperature annealing at 1000 ° C. or higher is additionally performed in an oxidizing atmosphere. In addition to such a method of forming a thermal oxide film, there is a method of annealing at about 800 ° C. in a hydrogen atmosphere after washing with a hydrofluoric acid solution. According to this method, reconfiguration of silicon atoms occurs, and it is possible to obtain effects such as recovery of crystallinity and rounding of the corners of the trench. In this case, the thermal oxide films 205a and 205b are not formed, or a film extremely thin to the extent of the natural oxide film thickness is formed. The steps so far are almost the same as those in the first embodiment. In the first embodiment, the pullback process is performed after this, but in the present embodiment, the pullback process may not be performed.

  Next, as shown in FIG. 8C, the first element isolation insulating films 206a and 206b are thinly and isotropically formed to a thickness of, for example, about 10 nm by plasma CVD. Here, a silicon oxynitride film may be used as the first element isolation insulating films 206a and 206b, or an insulating film into which an element other than nitrogen, for example, carbon or fluorine is introduced may be used. Subsequently, as shown in FIG. 8D, second element isolation insulating films 207a and 207b are formed by high density plasma (HDP) CVD so as to fill the trenches 204a and 204b. The second element isolation insulating films 207a and 207b are formed to a thickness of 450 nm, for example.

  Next, baking for modifying the second element isolation insulating films 207a and 207b is performed at 800 ° C. for about 10 minutes. By baking, the properties of the second element isolation insulating films 207a and 207b are close to those of the thermal oxide film, and the quality is improved. What is important in this step is that in the next etching step, the etching rate of the first element isolation insulating films 206a and 206b is preferably at least twice that of the second element isolation insulating films 207a and 207b. Each insulating film is formed so that

  Next, as shown in FIG. 8E, the second element isolation insulating films 207a, 207a, 207a, 207a, 207a, 207a, 207a, 207a, 207a, 207a, 207a, 207a, 207a, 207a, 207b and the first element isolation insulating films 206a and 206b are removed.

  Next, as shown in FIG. 8F, a resist is applied and developed to form a resist pattern 208a having an opening corresponding to the memory portion and exposing the memory portion. Subsequently, using the resist pattern 208a as a mask, a part of the first element isolation insulating film 206b of the memory portion is selectively etched as shown in FIG. 8G. Here, the etching may be performed by wet etching using a hydrofluoric acid solution, and dry etching may be used as long as the first element isolation insulating film 206b can be selectively etched.

  Next, the resist pattern 208a is removed by cleaning using SPM and APM. Further, the silicon nitride films 202a and 202b are removed by wet etching using phosphoric acid at about 160 ° C. as shown in FIG. 8H.

Subsequently, ions are implanted into the well region and the channel region through the sacrificial oxide film 201. The implantation conditions vary depending on the transistor design. For example, the well depth is controlled to be about 150 nm and the channel impurity concentration is controlled to be about 1 × 10 ¹⁷ atm / cm ³ to 1 × 10 ¹⁹ atm / cm ³ . Subsequently, activation and crystal recovery are performed by lamp annealing at about 1000 ° C. Thereby, the active regions 209a and 209b are formed. Thereafter, the sacrificial oxide film 201 is removed by wet etching using a buffered hydrofluoric acid solution. At this time, as shown in FIG. 8I, the first element isolation insulating films 206a and 206b and the second element isolation insulating films 207a and 207b are also etched.

  Thereafter, as shown in FIG. 8J, gate insulating films (oxide films) 210a and 210b are formed. The gate insulating films 210 a and 210 b are formed in order from the high breakdown voltage transistor among the plurality of semiconductor elements 20 a and 20 b constituting the semiconductor device 20. The oxide film thickness of the high voltage transistor is, for example, about 7 nm at the time of 3.3V design. Here, in the core transistor region where the gate oxide film is thin, the previously formed thick gate insulating films 210a and 210b are once etched with a hydrofluoric acid solution, and then the thin gate insulating films 210a and 210b of 3 nm or less are formed again. To do. In this process, the first element isolation insulating films 206a and 206b and the second element isolation insulating films 207a and 207b are further etched to have a final shape. Here, the first element isolation insulating film 206b in the memory portion is etched more than the first element isolation insulating film 206a in the logic portion. For this reason, as shown in FIG. 8J, the dent part (dent part) 211b near the active region 209b in the memory part is formed deeper than the dent part (dent part) 211a of the logic part. Since the thermal oxide films 205a and 205b are thin, when the first element isolation insulating films 206a and 206b are recessed and etched, the thermal oxide films 205a and 205b are the same as the first element isolation insulating films 206a and 206b. It is simultaneously etched to a certain height.

  Thereafter, as shown in FIG. 7, gate electrodes 212a and 212b are formed by a known method, and Extension / Halo ions are implanted to form Extension / Halo diffusion layers 219a and 219b. In addition, sidewalls 213a and 213b are formed. Next, ions are implanted into the source / drain regions 214a, 214b, 216a, and 216b, and activation annealing is performed to activate the implanted ions. Further, silicide layers 218a and 218b are formed, and drain electrodes 215a and 215b and source electrodes 217a and 217b are provided. Through these steps, semiconductor elements 20a and 20b are formed as shown in FIGS.

  Further, a logic circuit is formed in the logic portion, and a memory circuit is formed in the memory portion. These circuits may be formed simultaneously or separately. In the case of forming separately, for example, after the memory portion is masked and the logic circuit is formed, the mask of the memory portion is removed and the logic portion is masked to form the memory circuit. Or you may form in the reverse order. These circuits can be formed by methods known to those skilled in the art. By such a process, the semiconductor device 20 is formed.

  In the semiconductor device manufacturing method of the present embodiment, first buried insulating films 206a and 206b and second buried insulating films 207a and 207b are formed in the trenches 204a and 204b, and the first buried insulating films 207a and 207b are formed. The upper part of the buried insulating film 206b is selectively etched. Thereby, the recess 211a of the logic part can be formed to be shallower than the recess 211b of the memory part or not to provide the recess 211a. Accordingly, it is possible to provide a semiconductor device in which only the element isolation region adjacent to the active region 209b of the memory portion is dug and the side region of the trench 204b can be used as a channel. In the present embodiment, by limiting the region to be dug to the vicinity of the active region, the step on the surface of the semiconductor element is reduced, the processing of the gate electrodes 212a and 212b is facilitated, and the gate processing accuracy can be maintained. As a result, it is possible to increase the driving capability of the cell transistor as the gate width increases while preventing an increase in cell size, and to improve random variations.

  The method for forming each part disclosed in the above embodiment exemplifies only essential parts, and an actual semiconductor device includes a part that is not explicitly shown in this embodiment. The present invention is not limited to the above-described embodiments, and various modifications and applications are possible. For example, the order of the steps disclosed in the above-described embodiments can be changed as appropriate, for example, the order can be changed. Furthermore, some or all of the configurations of the above-described embodiments may be appropriately combined with each other.

  In the step shown in FIG. 8D, a thin thermal oxide film may exist between the silicon substrate 200 and the first buried insulating films 206a and 206b.

  In the above-described embodiments, the case of the SRAM has been described as an example. However, the present invention is not limited to this, and can be applied to other memory elements such as a DRAM.

10, 20, 50 Semiconductor device 10a, 10b, 20a, 20b, 50a, 50b Semiconductor element 100, 200, 500 Semiconductor substrate (silicon substrate)
201, 101 Sacrificial oxide film (first insulating film)
102, 102a, 102b, 202, 202a, 202b Silicon nitride film (second insulating film)
103a, 103b, 203a, 203b, 208a Resist pattern 104a, 104b, 204a, 204b, 504a, 504b Trench (groove)
105a, 105b, 205a, 205b Thermal oxide film 106b Oxide film 107a, 107b, 501a, 501b Element isolation insulating film (buried insulating film)
108a, 108b, 209a, 209b, 505a, 505b Active region 109a, 109b, 210a, 210b, 502a, 502b Gate insulating film 110a, 110b, 211a, 211b Recessed portion (recessed portion)
111a, 111b, 212a, 212b, 503a, 503b Gate electrodes 112a, 112b, 213a, 213b, 506a, 506b Side walls 113a, 113b, 214a, 214b Drain regions 114a, 114b, 215a, 215b Drain electrodes 115a, 115b, 216a, 216b Source region 116a, 116b, 217a, 217b Source electrode 117a, 117b, 218a, 218b Silicide layer 118a, 118b, 219a, 219b Extension / Halo diffusion layer 206a, 206b First element isolation insulating film (first buried insulating film) )
207a, 207b Second element isolation insulating film (second buried insulating film)

Claims (12)

A semiconductor substrate having a first region and a second region;
A first active region formed in the first region of the semiconductor substrate;
A second active region formed in the second region of the semiconductor substrate;
A first groove formed in the first region and defining the first active region;
A second groove formed in the second region and defining the second active region;
A first element isolation insulating film embedded in the first groove,
A second element isolation insulating film embedded in the second trench,
Have
The second element isolation insulating film has a recess formed in a portion adjacent to the second active region,
The bottom of the recess is formed at a position lower than a portion of the first element isolation insulating film adjacent to the first active region ,
Furthermore, a logic circuit is formed in the first region, and a memory circuit is formed in the second region.
A semiconductor device. A semiconductor substrate having a first region and a second region;
A first active region formed in the first region of the semiconductor substrate;
A second active region formed in the second region of the semiconductor substrate;
A first groove formed in the first region and defining the first active region;
A second groove formed in the second region and defining the second active region;
A first element isolation insulating film embedded in the first groove,
A second element isolation insulating film embedded in the second trench,
Have
The second element isolation insulating film has a recess formed in a portion adjacent to the second active region,
The bottom of the recess is formed at a position lower than a portion of the first element isolation insulating film adjacent to the first active region ,
Further, a logic circuit is formed in the first region, and a static random access memory circuit is formed in the second region.
A semiconductor device. The first element isolation insulating film is formed with a recess that is shallower than the recess formed in the second element isolation insulating film in a portion adjacent to the first active region, or The first
The element isolation insulating film is substantially flat across a portion adjacent to the first active region.
The semiconductor device according to claim 1 or 2, characterized in that. The height of the surface of the first element isolation insulating film is substantially equal to the height of the surface of the second element isolation insulating film;
The semiconductor device according to claim 1 or 2, characterized in that. A field effect transistor formed in the first region and a field effect transistor formed in the second region;
A channel region of the field effect transistor formed in the first region is formed to extend to a side surface of the first active region exposed by the recess formed in the first element isolation insulating film. Has been
A channel region of the field effect transistor formed in the second region is formed to extend to a side surface of the second active region exposed by the recess formed in the second element isolation insulating film. Being
The semiconductor device according to claim 3 . Thermal oxide films are provided between the first active region and the first element isolation insulating film and between the second active region and the second element isolation insulating film, respectively.
The semiconductor device according to claim 3 . The thickness of the gate insulating film of the field effect transistor formed in the first region is equal to the thickness of the gate insulating film of the field effect transistor formed in the second region.
The semiconductor device according to claim 5 . Providing a semiconductor substrate having a first region and a second region;
A first groove defining a first active region is formed in the first region of the semiconductor substrate, and a second groove defining a second active region is formed in the second region of the semiconductor substrate. And steps to
Forming a first element isolation insulating film in the first groove portion and a second element isolation insulating film in the second groove portion;
With
The step of forming the groove includes
Sequentially forming a first insulating film and a second insulating film on the surface of the semiconductor substrate;
Etching the first insulating film, the second insulating film, and the semiconductor substrate to form grooves in the first region and the second region on the semiconductor substrate, respectively.
The step of forming the element isolation insulating film includes:
Forming a mask on the semiconductor substrate;
Forming an opening in a portion of the mask corresponding to the first region;
Isotropically etching the second insulating film using the mask;
Removing the mask;
A isotropic etching is performed on the second insulating film in the first region and the second region.
Tep,
Forming a buried insulating film in the groove;
Forming a recess in a portion of the second element isolation insulating film adjacent to the second active region ,
The bottom of the recess is formed at a position lower than a portion of the first element isolation insulating film adjacent to the first active region.
A method for manufacturing a semiconductor device. Providing a semiconductor substrate having a first region and a second region;
A first groove defining a first active region is formed in the first region of the semiconductor substrate, and a second groove defining a second active region is formed in the second region of the semiconductor substrate. And steps to
Forming a first element isolation insulating film in the first groove portion and a second element isolation insulating film in the second groove portion;
With
The step of forming the groove includes
Sequentially forming a first insulating film and a second insulating film on the surface of the semiconductor substrate;
Etching the first insulating film, the second insulating film, and the semiconductor substrate to form grooves in the first region and the second region on the semiconductor substrate, respectively.
The step of forming the element isolation insulating film includes:
Forming a first buried insulating film on the surface of the semiconductor substrate, and further completely filling the groove with a second buried insulating film;
Planarizing the first and second buried insulating films using the second insulating film as an etching stopper;
Forming a resist pattern having an opening only in the second region on the semiconductor substrate, and selectively etching a part of the first buried insulating film using the resist pattern as a mask;
Removing the second insulating film after removing the resist pattern;
Introducing an impurity into the semiconductor substrate using the first insulating film as a sacrificial film;
Forming a gate oxide film on the semiconductor substrate after removing the first buried insulating film exposed on the surface;
Forming a recess in a portion of the second element isolation insulating film adjacent to the second active region ,
The bottom of the recess is formed at a position lower than a portion of the first element isolation insulating film adjacent to the first active region.
A method for manufacturing a semiconductor device. Forming the first buried insulating film by depositing silicon oxide containing at least one of nitrogen, carbon, fluorine, boron, phosphorus, and arsenic;
A method for manufacturing a semiconductor device according to claim 9 . Forming the second buried insulating film by depositing silicon oxide;
A method for manufacturing a semiconductor device according to claim 9 . Providing a semiconductor substrate having a first region and a second region;
A first groove defining a first active region is formed in the first region of the semiconductor substrate, and a second groove defining a second active region is formed in the second region of the semiconductor substrate. And steps to
Forming a first element isolation insulating film in the first groove portion and a second element isolation insulating film in the second groove portion;
Forming a logic circuit in the first region and forming a memory circuit in the second region after the step of forming the element isolation insulating film; and
The step of forming the element isolation insulating film includes:
Look including the step of forming a recessed portion in a portion adjacent to the second active region of said second element isolation insulating film,
The bottom of the recess is formed at a position lower than a portion of the first element isolation insulating film adjacent to the first active region.
A method for manufacturing a semiconductor device.

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