JP5487627B2 - Semiconductor integrated circuit - Google Patents

Description

  The present application generally relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit including a plurality of circuit blocks whose power supply voltage is variably controlled and operates at different power supply voltages.

  In recent years, electronic devices such as cellular phones equipped with semiconductor integrated circuits have been reduced in size and power consumption. It is also demanded to reduce power consumption for semiconductor integrated circuits. In order to reduce power consumption, different power supply voltages may be designed for each circuit block (hereinafter referred to as “multiple power supply design”).

  The semiconductor integrated circuit 100 shown in FIG. 1 is also a semiconductor integrated circuit designed for multiple power supplies. In the semiconductor integrated circuit 100 shown in FIG. 1, the first circuit block 20 using the first power supply voltage (PD1) and the second circuit block 30 using the second power supply voltage (PD2) are mixed. . In the semiconductor integrated circuit 100, the second power supply voltage (PD2) is higher than the first power supply voltage (PD1). Here, the first power supply voltage (PD1) is a variable setting, and the second power supply voltage (PD2) is a fixed setting.

  The first circuit block 20 operating at the first power supply voltage (PD1) includes a processor core 40. The processor core 40 is a core part of the CPU that performs arithmetic processing, and includes a buffer 50 and a flip-flop circuit 1.

  The second circuit block 30 operating at the second power supply voltage (PD2) includes a PLL circuit 60 that generates a clock signal inside the semiconductor integrated circuit 100, a functional circuit 70, a phase comparison circuit 3A, and a control circuit 80. It is. The functional circuit 70 includes a buffer 55 and a flip-flop circuit 2.

  In the phase comparison circuit 3A, the first clock signal (CK1L) input to the flip-flop circuit 1 and the first delay clock signal (CK1L) delayed through the level shift circuit 6 is input to the flip-flop circuit 2. The second clock signal (CK2) is input. Here, since the second power supply voltage (PD2) is higher than the first power supply voltage (PD1), the first clock signal (CK1) in the first circuit block 20 is in the second circuit block 30. In order to input to the phase comparison circuit 6, a level shift is required to boost the voltage level of the first clock signal (CK1). The level shift circuit 6 is a circuit that boosts the voltage level of the first clock signal (CK1) from the first power supply voltage (PD1) to the second power supply voltage (PD2). The phase comparison circuit 3A compares the phase difference between both input signals and outputs a comparison result. The control circuit 80 adjusts the phase difference between the first clock signal (CK1) and the second clock signal (CK2) according to the comparison result.

  The reason why the control circuit 80 adjusts the phase difference is that data (DATA) is transferred from the flip-flop circuit 1 provided in the processor core 40 to the flip-flop circuit 2 provided in the functional circuit 70. This is because if the phase difference between the first clock signal (CK1) and the second clock signal (CK2) is not adjusted, there is a possibility that the timing is shifted at the time of data (DATA) transfer, and the transfer cannot be performed. is there.

JP2008-227397 Table WO2005 / 008777

  Adjustment of the phase difference between the first clock signal (CK1) and the second clock signal (CK2) is performed based on two clock signals input to the phase comparison circuit 3A. Here, the clock signals to be subjected to phase adjustment are the first clock signal (CK1) and the second clock signal (CK2). Therefore, it is desirable that the two clock signals input to the phase comparison circuit 3A have the same phase as the first clock signal (CK1) and the second clock signal (CK2). However, the clock signal actually input to the phase comparison circuit 3A includes the first delayed clock signal (CK1L) obtained by delaying the first clock signal (CK1) through the level shift circuit 6 and the second clock signal (CK2). ).

  Adjustment of the phase difference between the first clock signal (CK1) and the second clock signal (CK2) is performed by the control circuit 80, including the amount of delay caused by the level shift circuit 6. However, among the clock signals input to the phase comparison circuit 3A, the clock signal from the first clock signal (CK1) input to the flip-flop circuit 1 and the second clock signal (CK2) input to the flip-flop circuit 2 As long as there is a difference in the propagation delay of the clock signal with respect to the clock signal from), an error may occur in the adjustment of the phase difference. Further, depending on the error, there is a possibility that trouble such as failure in data (DATA) transfer between the processor core 40 and the functional circuit 70 may occur.

  The present invention has been proposed in view of the above problems, and among the clock signals input to the phase comparison circuit 3A, the clock signal propagated from the first clock signal (CK1) input to the flip-flop circuit 1 and A semiconductor integrated circuit that eliminates the difference in propagation delay of the clock signal from the second clock signal (CK2) input to the flip-flop circuit 2 and suppresses an error in adjusting the phase difference. The purpose is to provide.

A first semiconductor integrated circuit disclosed in the present application includes a control circuit that outputs a first clock signal and a second clock signal, a first circuit that is supplied with a first power supply voltage and operates based on the first clock signal. A second power supply voltage having a voltage value different from that of the first power supply voltage, a second circuit operating based on the second clock signal, first and second power supply voltages being supplied, and the second clock signal being A first conversion circuit for changing to a first signal whose low level is the ground voltage and high level is the first power supply voltage , and the first and second power supply voltages are supplied, the first clock signal is grounded and the low level is grounded A first level shift circuit that changes to a second signal that is a voltage and a high level is a second power supply voltage , and has the same circuit configuration as the first level shift circuit, and is supplied with the first and second power supply voltages , a first signal and a low level ground A second level shift circuit high a pressure is changed to a third signal which is a second power supply voltage, a second power supply voltage is supplied, a phase for comparing the phase of the third signal of the second signal The control circuit is supplied with the second power supply voltage , adjusts the phase difference between the first clock signal and the second clock signal according to the comparison result by the phase comparison circuit, and controls the first and second Outputs a clock signal.

The phase of the second signal corresponding to the first clock signal supplied to the first circuit supplied with the first power supply voltage and the second signal corresponding to the second clock signal supplied to the second circuit supplied with the second power supply voltage. A first level shift circuit for changing the first clock signal to a second signal whose low level is the ground voltage and whose high level is the second power supply voltage when the phase comparison circuit compares the phases of the three signals with each other; Via the second signal. The propagation path of the second clock signal, the second clock signal, a low level is a ground voltage high level through the first conversion circuit for changing the first signal is a first power supply voltage, the first signal Is provided with a second level shift circuit that changes to a third signal that transitions between the ground voltage and the second power supply voltage. Here, the second level shift circuit has the same circuit configuration as the first level shift circuit. Thereby, a delay equivalent to the second signal corresponding to the first clock signal is added to the third signal corresponding to the second clock signal.

  As a result, of the two signals input to the phase comparison circuit, the second signal corresponding to the first clock signal is passed through the first level shift circuit due to the necessity of the level shift of the voltage level. Propagation delay due to level shift circuit 1 is added to delay the phase. On the other hand, for the third signal corresponding to the second clock signal, although there is no need for the level shift of the voltage level, a propagation delay by the second level shift circuit is added through the second level shift circuit. The phase is delayed. Thereby, the phase delay added to both signals becomes equal. The error due to the adjustment of the phase difference between the two signals input to the phase comparison circuit becomes minor.

A second semiconductor integrated circuit disclosed in the present application includes a control circuit that outputs a first clock signal and a second clock signal, a first circuit that is supplied with a first power supply voltage and operates based on the first clock signal. A second power supply voltage having a voltage value different from that of the first power supply voltage, a second circuit operating based on the second clock signal, first and second power supply voltages being supplied, and the second clock signal being A first conversion circuit for changing to a first signal whose low level is the ground voltage and high level is the first power supply voltage , and the first and second power supply voltages are supplied, the first clock signal is grounded and the low level is grounded A second conversion circuit that changes to a second signal that is a voltage and a high level is a second power supply voltage , and the first and second power supply voltages are supplied, and the first clock signal is a low level that is a ground voltage and a high level. the third level is the second power supply voltage A first level shift circuit for changing the item, has the same circuit configuration as the first level shift circuit is supplied first and second power supply voltage, a first signal, a low level is a ground voltage high A second level shift circuit that changes the level to a fourth signal that is the second power supply voltage ; a third conversion circuit that is supplied with the second power supply voltage, receives the second clock signal, and outputs a fifth signal; The second power supply voltage is supplied, the first phase comparison circuit that compares the phase of the third signal and the phase of the fourth signal, the second power supply voltage is supplied, the phase of the second signal and the phase of the fifth signal A first phase comparison circuit is selected when the voltage level of the second power supply voltage is higher than the voltage level of the first power supply voltage, and the first power supply voltage is selected from the voltage level of the second power supply voltage. Select the second phase comparator when the voltage level is high And a selection circuit, control circuit, a second power supply voltage is supplied, the first or the first clock signal according to the comparison result by either of the second phase comparison circuit and the second clock signal selected in the selection circuit And the first and second clock signals are output.

When the second power supply voltage is higher than the first power supply voltage, the first phase comparison circuit is selected by the selection circuit to which the second power supply voltage is supplied . The phase of the third signal corresponding to the first clock signal supplied to the first circuit supplied with the first power supply voltage and the second signal corresponding to the second clock signal supplied to the second circuit supplied with the second power supply voltage. When the first phase comparison circuit compares the phases of the four signals, the first clock is passed through the first level shift circuit that boosts the voltage level of the first clock signal from the first power supply voltage to the second power supply voltage. A third signal corresponding to the signal is supplied. The propagation path of the second clock signal, the second clock signal, a low level is a ground voltage high level through the first conversion circuit for changing the first signal is a first power supply voltage, the first signal the high level low level is a ground voltage and a second level shift circuit for changing a fourth signal which is a second power supply voltage. As a result, a delay equivalent to the third signal corresponding to the first clock signal is added to the fourth signal corresponding to the second clock signal and input to the first phase comparison circuit. When the first power supply voltage is higher than the second power supply voltage, the selection circuit selects the second phase comparison circuit. The second phase comparison circuit compares the second signal corresponding to the first clock signal input to the first circuit and the fifth signal corresponding to the second clock signal input to the second circuit. Here, the second level shift circuit has the same circuit configuration as the first level shift circuit.

  Thus, when the second power supply voltage is higher than the first power supply voltage, the phase comparison is performed by the first phase comparison circuit, and the first power supply voltage is compared with the second power supply voltage. When the voltage is high, the phase is compared by the second phase comparison circuit.

  When the second power supply voltage is higher than the first power supply voltage, the first clock signal is transmitted through the first level shift circuit from the necessity of the level shift of the voltage level. Propagation delay due to the level shift circuit is added to delay the phase. On the other hand, the second clock signal is not required to be level-shifted at the voltage level, but is added with a propagation delay by the second level shift circuit through the first conversion circuit and the second level shift circuit. Is delayed. Thereby, the phase delay added to both signals becomes equal. The error due to the adjustment of the phase difference between the two signals input to the first phase comparison circuit becomes minor.

  When the first power supply voltage is higher than the second power supply voltage, the first clock signal and the second clock signal need not be level-shifted in voltage level, but the first clock signal Through the second conversion circuit and the second clock signal is supplied through the third conversion circuit. There is no phase difference between the two signals input to the second phase comparison circuit, and errors due to the phase difference adjustment are minor.

A third semiconductor integrated circuit disclosed in the present application includes a control circuit that outputs a first clock signal and a second clock signal, a first circuit that is supplied with a first power supply voltage and operates based on the first clock signal. A second power supply voltage having a voltage value different from that of the first power supply voltage, a second circuit operating based on the second clock signal, first and second power supply voltages being supplied, and the second clock signal being A first conversion circuit for changing to a first signal whose low level is the ground voltage and high level is the first power supply voltage , and the first and second power supply voltages are supplied, the first clock signal is grounded and the low level is grounded A second conversion circuit that changes the voltage to a second signal whose high level is the second power supply voltage; and a third conversion circuit that is supplied with the second power supply voltage, receives the second clock signal, and outputs the third signal. A conversion circuit and a first power supply voltage are supplied; A fourth conversion circuit that receives one clock signal and outputs a fourth signal; a first phase comparison circuit that is supplied with a first power supply voltage and compares the phase of the fourth signal with the phase of the first signal; A second phase comparison circuit that is supplied with the second power supply voltage and compares the phase of the second signal with the phase of the third signal; and when the voltage value of the second power supply voltage is higher than the voltage value of the first power supply voltage And a selection circuit that selects the second phase comparison circuit when the voltage value of the first power supply voltage is higher than the voltage value of the second power supply voltage. The control circuit is selected by the selection circuit. The phase difference between the first clock signal and the second clock signal is adjusted according to the comparison result by either the first or second phase comparison circuit, and the first and second clock signals are output.

  When the second power supply voltage is higher than the first power supply voltage, the selection circuit selects the first phase comparison circuit. The phase of the fourth signal corresponding to the first clock signal supplied to the first circuit supplied with the first power supply voltage and the second signal corresponding to the second clock signal supplied to the second circuit supplied with the second power supply voltage. The phase of one signal is compared by the first phase comparison circuit. In addition, when the first power supply voltage is higher than the second power supply voltage, the control circuit selects the second phase comparison circuit. The phase of the second signal corresponding to the first clock signal supplied to the first circuit supplied with the first power supply voltage and the second signal corresponding to the second clock signal supplied to the second circuit supplied with the second power supply voltage. The phase of the three signals is compared by the second phase comparison circuit.

  Accordingly, when the second power supply voltage is higher than the first power supply voltage, the first phase comparison circuit to which the first power supply voltage is supplied is selected, and the first phase comparison circuit is compared with the second power supply voltage. When the one power supply voltage is a high voltage, the second phase comparison circuit to which the second power supply voltage is supplied is selected. In both cases, the signal corresponding to the first clock signal and the second clock signal There is no need to level shift the voltage level of the signal corresponding to. There is no difference in the phase delay between the two signals input to the first or second phase comparison circuit, and the error due to the adjustment of the phase difference is slight.

  According to the present application, among the clock signals input to the phase comparison circuit, a signal corresponding to the first clock signal input to the first circuit, and a signal corresponding to the second clock signal input to the second circuit, Thus, it is possible to provide a semiconductor integrated circuit in which a difference in propagation delay can be suppressed and errors due to adjustment of the phase difference are suppressed.

  The embodiment disclosed in the present application is suitable for application to dynamic voltage and frequency scaling (DVFS). Dynamic voltage / frequency control (DVFS) is to variably control the power supply voltage at which the processor core or the like operates and the frequency of the clock signal supplied. An object of the present invention is to suppress unnecessary power supply and reduce power consumption by supplying an optimal power supply voltage and clock signal frequency according to the processing speed when the processor core performs arithmetic processing.

  In order to realize dynamic voltage / frequency control (DVFS) in a semiconductor integrated circuit having a processor core, a design having a plurality of power supply systems and capable of variably controlling at least one power supply voltage (hereinafter referred to as “power supply voltage control”). May be referred to as “multiple power supply design”). When transmitting and receiving signals between circuit blocks using different power supply voltages, it is necessary to use a level shift circuit.

  The configuration of the first embodiment will be described with reference to FIG.

  A semiconductor integrated circuit 200 shown in FIG. 2 is a semiconductor integrated circuit designed for multiple power supplies. The first and second circuit blocks 20 and 30 in the semiconductor integrated circuit 200 are supplied with the first power supply voltage (PD1) and the second power supply voltage (PD2), respectively. Here, the first power supply voltage (PD1) is variable in a voltage range lower than the second power supply voltage (PD2), and the second power supply voltage (PD2) is fixed.

  In FIG. 2, the first circuit block 20 indicates that a circuit in the block operates by being supplied with the first power supply voltage (PD1), and the second circuit block 30 indicates a circuit in the block. Indicates that the second power supply voltage (PD2) is supplied to operate.

  The original clock signal (CK00) supplied from the outside of the semiconductor integrated circuit 200 is input to the PLL circuit 60 to which the second power supply voltage (PD2) is supplied. The PLL circuit 60 outputs a clock signal (CK0). The clock signal (CK0) is input to the control circuit 80 to which the second power supply voltage (PD2) is supplied.

  The control circuit 80 outputs a first original clock signal (CK01) and a second original clock signal (CK02). The first original clock signal (CK01) is input to the buffer 50 in the processor core 40 to which the first power supply voltage (PD1) is supplied. The second original clock signal (CK02) is input to the buffer 55 in the functional circuit 70 to which the second power supply voltage (PD2) is supplied.

  The buffer 50 outputs the first clock signal (CK1). The buffer 55 outputs the second clock signal (CK2). The first clock signal (CK1) is input to the input terminals of the flip-flop circuit 1 and the step-down level shift circuit 12 in the processor core 40. The second clock signal (CK2) is input to the flip-flop circuit 2 in the functional circuit 70 and the input terminal of the step-down level shift circuit 9. The flip-flop circuit 1 transfers data (DATA) to the flip-flop circuit 2.

  The first intermediate clock signal (CK1M) is output from the output terminal of the step-down level shift circuit 12. A second intermediate clock signal (CK2M) is output from the output terminal of the step-down level shift circuit 9. The first intermediate clock signal (CK1M) is input to the input terminal of the level shift circuit 6. The second intermediate clock signal (CK2M) is input to the input terminal of the level shift circuit 7.

  The first delayed clock signal (CK1L) is output from the output terminal of the level shift circuit 6. A second delayed clock signal (CK2L) is output from the output terminal of the level shift circuit 7. The first delayed clock signal (CK1L) and the second delayed clock signal (CK2L) are input to the phase comparison circuit 3A to which the second power supply voltage (PD2) is supplied. The phase comparison circuit 3A outputs a phase comparison result signal (CKA). The phase comparison result signal (CKA) is input to the control circuit 80.

  The configuration of the step-down level shift circuit 9 is shown in FIG.

  The input terminal of the step-down level shift circuit 9 is a connection point between the gate terminal of the PMOS transistor MP1 and the gate terminal of the NMOS transistor MN1. The second power supply voltage (PD2) is input to the source terminal of the PMOS transistor MP1. The source terminal of the NMOS transistor MN1 is grounded. The drain terminal of the PMOS transistor MP1 and the drain terminal of the NMOS transistor MN1 are connected.

  The connection point between the drain terminal of the PMOS transistor MP1 and the drain terminal of the NMOS transistor MN1 is connected to the gate terminal of the PMOS transistor MP2 and the gate terminal of the NMOS transistor MN2. The first power supply voltage (PD1) is input to the source terminal of the PMOS transistor MP2. The source terminal of the NMOS transistor MN2 is grounded. The connection point between the drain terminal of the PMOS transistor MP2 and the drain terminal of the NMOS transistor MN2 is the output terminal of the step-down level shift circuit 9.

  In the step-down level shift circuit 9, when the logic state of the clock signal input to the input terminal transitions, the time until the transitioned logic state is output to the output terminal is fast, and the delay is small. The step-down level shift circuit 9 not only has a function of stepping down and outputting a voltage input to the step-down level shift circuit, but also has a function as a buffer circuit that outputs the same voltage value as the voltage value of the input voltage. .

  The step-down level shift circuit 12 has the same circuit configuration as the step-down level shift circuit 9. However, unlike the step-down level shift circuit 9, the power supply voltage input to the source terminal of the PNOS transistor MP1 is the first power supply voltage (PD1).

  The configuration of the level shift circuits 6 and 7 is shown in FIG.

  The input terminal of the level shift circuit 6 is a connection point between the gate terminal of the PMOS transistor MP3 and the gate terminal of the NMOS transistor MN3. The first power supply voltage (PD1) is input to the source terminal of the PMOS transistor MP3. The source terminal of the NMOS transistor MN3 is grounded. The drain terminal of the PMOS transistor MP3 and the drain terminal of the NMOS transistor MN3 are connected.

  The connection point between the drain terminal of the PMOS transistor MP3 and the drain terminal of the NMOS transistor MN3 is connected to the gate terminal of the PMOS transistor MP4, the gate terminal of the NMOS transistor MN4, and the gate terminal of the NMOS transistor MN6. The first power supply voltage (PD1) is input to the source terminal of the PMOS transistor MP4. The source terminal of the NMOS transistor MN4 is grounded. The drain terminal of the PMOS transistor MP4 and the drain terminal of the NMOS transistor MN4 are connected.

  A connection point between the drain terminal of the PMOS transistor MP4 and the drain terminal of the NMOS transistor MN4 is connected to the gate terminal of the NMOS transistor MN5. The source terminal of the NMOS transistor MN5 is grounded. The drain terminal of the NMOS transistor MN5 is connected to the drain terminal of the PMOS transistor MP5. The drain terminal of the NMOS transistor MN6 is connected to the drain terminal of the PMOS transistor MP6. The second power supply voltage (PD2) is input to the source terminal of the PMOS transistor MP5 and the source terminal of the PMOS transistor MP6. A connection point between the drain terminal of the PMOS transistor MP5 and the drain terminal of the NMOS transistor MN5 is connected to the gate terminal of the PMOS transistor MP6. The connection point between the drain terminal of the PMOS transistor MP6 and the drain terminal of the NMOS transistor MN6 is connected to the gate terminal of the PMOS transistor MP5. This connection point is the output terminal of the level shift circuit 6.

  The level shift circuits 6 and 7 can operate regardless of the voltage values of the first power supply voltage (PD1) and the second power supply voltage (PD2). That is, the input signal can be level shifted to the boost side or level shifted to the step-down side. The level shift circuit 6 shown in the first embodiment (FIG. 2) is a case where the level is shifted to the boost side.

  Compared with the step-down level shift circuits 9 and 12, the level shift circuit 6 has a slower time until the transitioned logic state is output to the output terminal when the logic state of the clock signal input to the input terminal transitions. . In other words, the delay is large.

  The main reason for the large delay is that in the process of transition of the logic state of the signal input to the input terminal and transition of the signal output to the output terminal, the PMOS transistor MP5 and NMOS transistor MN5, and the PMOS transistor MP6 and NMOS transistor. This is because it takes time for the MN6 to reverse the logic state held in the configuration fed back to each other.

  When the logic state is inverted, there is a period in which both the PMOS transistor MP5 and the NMOS transistor MN5 are in the on state, or both the PMOS transistor MP6 and the NMOS transistor MN6 are in the on state. During this period, the logic state does not invert until the driving capability of the transistor that inverts the logic state exceeds the driving capability of the transistor that maintains the logic state. This period takes time.

  Specifically, the NMOS transistor MN6 is turned on before the PMOS transistor MP6 is turned off in the process in which the signal inputted to the input terminal changes from high level to low level and the signal outputted to the output terminal becomes low level. To do. There is a period in which both the PMOS transistor MP6 and the NMOS transistor MN6 are on. This period continues until the voltage level of the gate terminal of the PMOS transistor MP6 rises due to the NMOS transistor MN5 being turned off in conjunction with the NMOS transistor MN6 being turned on and the PMOS transistor MP6 is turned off. Similarly, in the process in which the signal input to the input terminal changes from the low level to the high level and the signal output to the output terminal changes to the high level, the NMOS transistor MN5 is turned on before the PMOS transistor MP5 is turned off. There is a period in which both the PMOS transistor MP5 and the NMOS transistor MN5 are on. This period continues until the voltage level of the gate terminal of the PMOS transistor MP5 rises due to the NMOS transistor MN6 being turned off in conjunction with the NMOS transistor MN5 being turned on and the PMOS transistor MP5 is turned off.

  The operation of the first embodiment will be described. This action is effective when the first power supply voltage (PD1) is lower than the second power supply voltage (PD2).

  An original clock signal (CK00) from the outside is input to the PLL circuit 60. The PLL circuit 60 adjusts the phase so that the original clock signal (CK00) from the outside matches the rating of the semiconductor integrated circuit 200, and outputs the clock signal (CK0) to the control circuit 80. The control circuit 80 outputs a first original clock signal (CK01) and a second original clock signal (CK02) based on the clock signal (CK0).

  The first original clock signal (CK01) becomes the first clock signal (CK1) through the buffer 50. Further, the second original clock signal (CK02) becomes the second clock signal (CK2) through the buffer 55. The first clock signal (CK1) is input to the flip-flop circuit 1, and the second clock signal (CK2) is input to the flip-flop circuit 2. The flip-flop circuit 1 operates based on the first clock signal (CK1), and the flip-flop circuit 2 operates based on the second clock signal (CK2).

  The flip-flop circuit 1 transfers data (DATA) to the flip-flop circuit 2. At this time, if the phase difference between the first clock signal (CK1) input to the flip-flop circuit 1 and the second clock signal (CK2) input to the flip-flop circuit 2 is not adjusted, the flip-flop circuit 2 There is a possibility that data (DATA) cannot be captured.

  The first clock signal (CK1) is also input to the step-down level shift circuit 12. Through the step-down level shift circuit 12, the first clock signal (CK1) is output as the first intermediate clock signal (CK1M).

  The second clock signal (CK2) is also input to the step-down level shift circuit 9. Through the step-down level shift circuit 9, the voltage level of the second clock signal (CK1) is stepped down and output as the second intermediate clock signal (CK2M).

  The step-down level shift circuit 12 generates a delay equivalent to the delay added to the second intermediate clock signal (CK2M) by the step-down level shift circuit 9 that steps down the voltage level of the second clock signal (CK2). It is provided for adding to the signal (CK1). The step-down level shift circuit 12 has the same circuit configuration as the step-down level shift circuit 9. Thereby, the delay of the first intermediate clock signal (CK1M) with respect to the first clock signal (CK1) is made equal to the delay of the second intermediate clock signal (CK2M) with respect to the second clock signal (CK2). It is possible to balance the phase of the first intermediate clock signal (CK1M) and the phase of the second intermediate clock signal (CK2M), thereby reducing the phase difference.

  The first intermediate clock signal (CK1M) is input to the level shift circuit 6. Through the level shift circuit 6, the voltage level of the first intermediate clock signal (CK1M) is boosted from the first power supply voltage (PD1) to the second power supply voltage (PD2), and the first delayed clock signal (CK1L) is output. Is done. In this case, the delay by the level shift circuit 6 is added to the first intermediate clock signal (CK1M). On the other hand, the second intermediate clock signal (CK2M) is input to the level shift circuit 7. The voltage level of the second intermediate clock signal (CK2M) is boosted from the first power supply voltage (PD1) to the second power supply voltage (PD2), and the second delayed clock signal (CK2L) is output. In this case, the delay by the level shift circuit 7 is added to the second intermediate clock signal (CK2M). The first delay clock signal (CK1L) and the second delay clock signal (CK2L) whose voltage level is boosted to the second power supply voltage (PD2) are the phase comparison circuit 3A to which the second power supply voltage (PD2) is supplied. Is input.

  Note that the delay caused by passing through the level shift circuit 6 is equivalent to the delay caused by passing through the level shift circuit 7. This is because the level shift circuit 7 has the same circuit configuration as the level shift circuit 6.

  Thereby, the delay added to the first delayed clock signal (CK1L) and the delay added to the second delayed clock signal (CK2L) can be balanced, and the phase difference can be made small.

  The phase comparison circuit 3A compares the phase difference between the first delayed clock signal (CK1L) and the second delayed clock signal (CK2L), and outputs a phase comparison result signal (CKA) corresponding to the phase difference.

  The delay added to the first delayed clock signal (CK1L) with respect to the first clock signal (CK1) and the delay added to the second delayed clock signal (CK2L) with respect to the second clock signal (CK2). Is approximately equivalent. Therefore, the phase difference between the first delayed clock signal (CK1L) and the second delayed clock signal (CK2L) input to the phase comparison circuit 3A can be made small and a phase comparison with a slight error can be performed. Can do.

  The phase comparison result signal (CKA) is input to the control circuit 80. The control circuit 80 adjusts the phase difference between the first clock signal (CK1) and the second clock signal (CK2) based on the phase comparison result signal (CKA).

  The effect of the first embodiment will be described.

  In the semiconductor integrated circuit 200 in which the first power supply voltage (PD1) is variable in a range lower than the second power supply voltage (PD2), the first clock signal (CK1) driven by the first power supply voltage (PD1) is The delay added to the signal from the first intermediate clock signal (CK1M) to the first delayed clock signal (CK1L) and the second clock signal (CK2) driven by the second power supply voltage (PD2) The delay added to the signal from the two intermediate clock signals (CK2M) to the second delayed clock signal (CK2L) can be made equal. Thereby, the phase between the signals input to the phase comparison circuit 3A can be made equal. An error included in the phase comparison result signal (CKA) output from the phase comparison circuit 3A can be reduced. The phase difference between the first clock signal (CK1) and the second clock signal (CK2) can be adjusted with high accuracy. A malfunction that the flip-flop circuit 2 cannot take in data (DATA) can be prevented.

  In the first embodiment, the step-down level shift circuit 12 is included. However, the step-down level shift circuit 12 may be omitted. This is because the delay added by the step-down level shift 9 itself is very small. Therefore, if the step-down level shift circuit 12 is not provided, a delay due to the step-down level shift 9 is added to the second clock signal (CK2), while an equivalent delay is not added to the first clock signal (CK1). The phase difference between both signals remains in a very small range.

  A semiconductor integrated circuit according to the second embodiment will be described with reference to FIG. Reference numeral 300 denotes a semiconductor integrated circuit according to the second embodiment. The first power supply voltage (PD1) is variable in a range lower than the second power supply voltage (PD2), and the second power supply voltage (PD2) is fixed. In FIG. 5, the same components as those of FIG.

  The first clock signal (CK1) is not input to the input terminal of the step-down level shift circuit 12, but is input to the input terminal of the step-down level shift circuit 13. The second clock signal (CK2) is not input to the input terminal of the step-down level shift circuit 9, but is input to the input terminal of the step-down level shift circuit 10. The step-down level shift circuit 13 has the same configuration as the step-down level shift circuit 12, and the step-down level shift circuit 10 has the same configuration as the step-down level shift circuit 9.

  The first intermediate clock (CK1M) is output from the output terminal of the step-down level shift circuit 13. A second intermediate clock signal (CK2M) is output from the output terminal of the step-down level circuit 10. The first intermediate clock signal (CK1M) and the second intermediate clock signal (CK2M) are input to the phase comparison circuit 3B to which the first power supply voltage (PD1) is supplied.

  The phase comparison circuit 3B outputs a phase comparison result signal (CKB). The phase comparison result signal (CKB) is input to the input terminal of the level shift circuit 15 having the same configuration as the level shift circuit 6. A phase comparison result delay signal (CKBL) is output from the output terminal of the level shift circuit 15. The phase comparison result delay signal (CKBL) is input to the control circuit 80.

  The operation of the second embodiment will be described. The same parts as those in the first embodiment are omitted. The second embodiment is effective when the first power supply voltage (PD1) is lower than the second power supply voltage (PD2).

  The first clock signal (CK1) is input to the step-down level shift circuit 13. Through the step-down level shift circuit 13, the first clock signal (CK1) is output as the first intermediate clock signal (CK1M).

  The second clock signal (CK2) is input to the step-down level shift circuit 10. By passing through the step-down level shift circuit 10, the voltage level of the second clock signal (CK1) is stepped down and output as the second intermediate clock signal (CK2M).

  The step-down level shift circuit 13 generates a delay equivalent to the delay added to the second intermediate clock signal (CK2M) by the step-down level shift circuit 10 that steps down the voltage level of the second clock signal (CK2). It is provided for adding to the clock signal (CK1M). The step-down level shift circuit 13 has the same circuit configuration as that of the step-down level shift circuit 10. Thereby, the delay of the first intermediate clock signal (CK1M) with respect to the first clock signal (CK1) is made equal to the delay of the second intermediate clock signal (CK2M) with respect to the second clock signal (CK2). It is possible to balance the phase of the first intermediate clock signal (CK1M) and the phase of the second intermediate clock signal (CK2M), thereby reducing the phase difference.

  The phase comparison circuit 3B compares the phase difference between the first intermediate clock signal (CK1M) and the second intermediate clock signal (CK2M), and outputs a phase comparison result signal (CKB) corresponding to the phase difference.

  The voltage level of the phase comparison result signal (CKB) is boosted through the level shift circuit 15 and is input to the control circuit 80 as a phase comparison delay signal (CKBL).

  The control circuit 80 adjusts the phase difference between the first clock signal (CK1) and the second clock signal (CK2) based on the phase comparison result delay signal (CKBL).

  The effect of the second embodiment will be described.

  In the semiconductor integrated circuit 300 in which the first power supply voltage (PD1) is variable in a range lower than the second power supply voltage (PD2), the phase comparison circuit 3B is a first power supply voltage lower than the second power supply voltage (PD2). (PD1) is supplied. For this reason, it is not necessary to boost the voltage level when the second clock signal (CK2) driven by the second power supply voltage (PD2) is input to the phase comparison circuit 3B. There is no need to interpose a level shift circuit for boosting the voltage level in the propagation path of the second clock signal (CK2), and no propagation delay of the second clock signal (CK2) is added. Thereby, the phase between the signals input to the phase comparison circuit 3B can be made equal. An error included in the phase comparison result signal (CKB) output from the phase comparison circuit 3B can be reduced. The phase difference between the first clock signal (CK1) and the second clock signal (CK2) can be adjusted with high accuracy. A malfunction that the flip-flop circuit 2 cannot take in data (DATA) can be prevented.

  Note that the delay by the step-down level shift circuit 10 interposed in the path from the second clock signal (CK2) to the second intermediate clock signal (CK2M) causes the second clock signal (CK2) to change to the first intermediate clock signal (CK1M). It is balanced by the delay by the step-down level shift circuit 13 interposed in the route to reach. That is, the delay until the first clock signal (CK1) reaches the first intermediate clock signal (CK1M) is equivalent to the delay until the second clock signal (CK2) reaches the second intermediate clock signal (CK2M). It can be.

  Here, the step-down level shift circuit 13 may be omitted. This is because, as in the case of the step-down level shift 12 in the first embodiment, the delay added by the step-down level shift 10 itself is very small. Accordingly, if the step-down level shift circuit 13 is not provided, a delay due to the step-down level shift 10 is added to the second clock signal (CK2), while an equivalent delay is not added to the first clock signal (CK1). The phase difference between both signals remains in a very small range.

  The configuration of the third embodiment will be described with reference to FIG. In FIG. 6, the same components as those in FIG.

  The first clock signal (CK1) is further input to the input terminal of the step-down level shift circuit 11. The second clock signal (CK2) is also input to the input terminal of the step-down level shift circuit 14. The configurations of the step-down level shift circuit 11 and the step-down level shift circuit 14 are the same as those of the step-down level shift circuit 9. However, in the step-down level shift circuit 11, the power supply voltage input to the source terminal of the PMOS transistor MP1 is the first power supply voltage (PD1). The power supply voltage input to the source terminal of the PMOS transistor MP2 is the second power supply voltage (PD2). In the step-down level shift circuit 14, the power supply voltage input to the source terminals of the PMOS transistors MP1 and MP2 is the second power supply voltage (PD2).

  When the first power supply voltage (PD1) is higher than the second power supply voltage (PD2), the first intermediate clock signal (CK1D) is output from the output terminal of the step-down level shift circuit 11. A second intermediate clock signal (CK2D) is output from the output terminal of the step-down level shift circuit 14. The first intermediate clock signal (CK1D) and the second intermediate clock signal (CK2D) are input to the phase comparison circuit 5 to which the second power supply voltage (PD2) is supplied.

  The phase comparison circuit 5 outputs a phase comparison result signal (CKA2). The phase comparison result signal (CKA) and the phase comparison result signal (CKA2) are input to the selection circuit 8. When the first power supply voltage (PD1) is lower than the second power supply voltage (PD2), the selection circuit 8 selects the phase comparison result signal (CKA), and the phase comparison result signal (CKA) is sent to the control circuit 80. Communicated. When the first power supply voltage (PD1) is higher than the second power supply voltage (PD2), the selection circuit 8 selects the phase comparison result signal (CKA2), and the phase comparison result signal (CKA2) is sent to the control circuit 80. Communicated.

  The operation of the third embodiment will be described. The same parts as those in the first embodiment are omitted.

  The operation when the first power supply voltage (PD1) is lower than the second power supply voltage (PD2) will be described.

  The phase comparison result signal (CKA) is input to the control circuit 80 via the selection circuit 8. The control circuit 80 adjusts the phase difference between the first clock signal (CK1) and the second clock signal (CK2) based on the phase comparison result signal (CKA).

  The operation when the first power supply voltage (PD1) is higher than the second power supply voltage (PD2) will be described.

  The first clock signal (CK1) is input to the step-down level shift circuit 11. Through the step-down level shift circuit 11, the voltage level of the first clock signal (CK1) is stepped down and output as the first intermediate clock signal (CK1M).

  The second clock signal (CK2) is input to the step-down level shift circuit 14. Through the step-down level shift circuit 14, the second clock signal (CK2) is output as a second intermediate clock signal (CK2M).

  The step-down level shift circuit 14 generates a delay equivalent to the delay added to the first intermediate clock signal (CK1M) by the step-down level shift circuit 11 that steps down the voltage level of the first clock signal (CK1). It is provided for adding to the signal (CK2M). The step-down level shift circuit 14 has the same circuit configuration as the step-down level shift circuit 11. Thereby, the delay of the first intermediate clock signal (CK1M) with respect to the first clock signal (CK1) is made equal to the delay of the second intermediate clock signal (CK2M) with respect to the second clock signal (CK2). It is possible to balance the phase of the first intermediate clock signal (CK1M) and the phase of the second intermediate clock signal (CK2M), thereby reducing the phase difference.

  The phase comparison circuit 5 compares the phase difference between the first intermediate clock signal (CK1M) and the second intermediate clock signal (CK2M), and outputs a phase comparison result signal (CKA2) corresponding to the phase difference.

  The control circuit 80 adjusts the phase difference between the first clock signal (CK1) and the second clock signal (CK2) based on the phase comparison result delay signal (CKA2).

  The effect of the third embodiment will be described.

  When the first power supply voltage (PD1) is lower than the second power supply voltage (PD2), the selection circuit 8 selects the phase comparison result signal (CKA1) and outputs it to the control circuit 80. At this time, the phase difference between the clock signals input to the phase comparison circuit 3A is slight. This is because the level shift circuit 6 and the level shift circuit 7 have the same delay, and the step-down level shift circuit 12 and the step-down level shift circuit 9 have the same delay.

  When the first power supply voltage (PD1) is higher than the second power supply voltage (PD2), the selection circuit 8 selects the phase comparison result signal (CKA2) and outputs it to the control circuit 80. At this time, the phase difference between the clock signals input to the phase comparison circuit 5 is slight. This is because the step-down level shift circuit 11 and the step-down level shift circuit 14 have the same delay.

  The selection circuit 8 selects either the phase comparison result signal (CKA1) or the phase comparison result signal (CKA2) according to the voltage value of the first power supply voltage (PD1) and the second power supply voltage (PD2). select. As a result, it is possible to operate the circuit with a small phase difference between the clock signals regardless of the voltage value between the first power supply voltage (PD1) and the second power supply voltage (PD2).

  As described in the first embodiment, the step-down level shift circuit 12 and the step-down level shift circuit 9 are not necessary. Further, similarly to the step-down level shift circuit 12 in the first embodiment, the step-down level shift circuit 14 may be omitted. This is because the delay added by the step-down level shift 9 itself is very small. Accordingly, if the step-down level shift circuit 14 is not provided, a delay due to the step-down level shift 9 is added to the second clock signal (CK2), while an equivalent delay is not added to the first clock signal (CK1). The phase difference between both signals remains in a very small range.

  The configuration of the fourth embodiment will be described with reference to FIG. In FIG. 7, the same components as those of the second embodiment (FIG. 5) and the third embodiment (FIG. 6) are denoted by the same reference numerals, and the description thereof is omitted.

  The phase comparison result delay signal (CKBL) is input to the selection circuit 8.

  When the first power supply voltage (PD1) is lower than the second power supply voltage (PD2), the selection circuit 8 selects the phase comparison result signal (CKBL) and transmits the phase comparison result signal (CKBL) to the control circuit 80. To do. When the first power supply voltage (PD1) is higher than the second power supply voltage (PD2), the selection circuit 8 selects the phase comparison result signal (CKA2) and transmits the phase comparison result signal (CKA2) to the control circuit 80. To do.

  The operation of the fourth embodiment will be described. The same components as those in the second and third embodiments are omitted. The operation when the first power supply voltage (PD1) is higher than the second power supply voltage (PD2) is the same as that in the third embodiment, and thus the description thereof is omitted.

  The phase comparison result delay signal (CKBL) is input to the control circuit 80 via the selection circuit 8. The control circuit 80 adjusts the phase difference between the first clock signal (CK1) and the second clock signal (CK2) based on the phase comparison result delay signal (CKBL).

  The fourth embodiment has the same effects as the third embodiment.

  Here, the first power supply voltage (PD1) is an example of the first power supply voltage in the claims. The second power supply voltage (PD2) is an example of a second power supply voltage in the claims. The flip-flop circuit 1 is an example of a first circuit in the claims. The flip-flop circuit 2 is an example of a second circuit in the claims. The first clock signal (CK1) is an example of the first clock signal in the claims. The first clock signal (CK1), the first intermediate clock signal (CK1M) (CK1D), and the first delayed clock signal (CK1L) are examples of signals corresponding to the first clock signal in the claims. The second clock signal (CK2) is an example of a second clock signal in the claims. The second clock signal (CK2), the second intermediate clock signal (CK2M) (CK2D), and the second delayed clock signal (CK2L) are examples of signals corresponding to the second clock signal in the claims. The phase comparison circuits 3A and 3B are examples of the phase comparison circuit of the claims or the first phase comparison circuit. The phase comparison circuit 5 is an example of a second phase comparison circuit. The level shift circuit 6 is an example of a first level shift circuit. The level shift circuit 7 is an example of a second level shift circuit. The phase comparison result signals (CKA), (CKA2), (CKB) and the phase comparison result delay signal (CKBL) are examples of comparison results in claims. The selection circuit 8 is an example of a selection circuit in the claims. The step-down level shift circuit 9 is an example of a first step-down level shift circuit. The step-down level shift circuit 10 is an example of a second step-down level shift circuit. The step-down level shift circuit 11 is an example of a third step-down level shift circuit. The step-down level shift circuit 12 is an example of a fifth step-down level shift circuit. The step-down level shift circuit 13 is an example of a sixth step-down level shift circuit. The step-down level shift circuit 14 is an example of a seventh step-down level shift circuit.

  The present invention is not limited to the above-described embodiment, and it goes without saying that various improvements and modifications can be made without departing from the spirit of the present invention. For example, the first power supply voltage (PD1) is variable and the second power supply voltage (PD2) is fixed. However, the present invention is not limited to this. The present invention can be implemented whether both are variable or fixed. What is necessary is just to design in consideration of the voltage relationship between the first power supply voltage (PD1) and the second power supply voltage.

  Moreover, although 1st power supply voltage (PD1) demonstrated about 1st Embodiment and 2nd Embodiment as a voltage lower than 2nd power supply voltage (PD2), it is not limited to this. Even when the first power supply voltage (PD1) is higher than the second power supply voltage (PD2), the level shift circuits 6 and 7 operate as they are. Regarding the step-down level shift circuits 9 and 10, there is no problem in operation if the power supply voltage to be supplied is the second power supply voltage (PD2). Therefore, if the step-down level shifts 9, 10, 12, and 13 are not provided, the first and second embodiments have a voltage value between the first power supply voltage (PD1) and the second power supply voltage (PD2). It works regardless of the height of the.

  According to the embodiment described above, the delay added until the first clock signal (CK1) driven by the first power supply voltage (PD1) is input to the phase comparison circuits 3A, 3B, and 5; The delay added until the second clock signal (CK2) driven by the second power supply voltage (PD2) is input to the phase comparison circuits 3A, 3B, and 5 can be made equal. Thereby, the phase between the signals input to the phase comparison circuits 3A, 3B, and 5 can be made equal. Errors included in the phase comparison result signals (CKA), (CKB), and (CKA2) output from the phase comparison circuits 3A, 3B, and 5 can be minimized. The phase difference between the first clock signal (CK1) and the second clock signal (CK2) can be adjusted with high accuracy. A malfunction that the flip-flop circuit 2 cannot take in data (DATA) can be prevented.

  Hereinafter, various aspects of the present invention will be summarized as additional notes.

(Appendix 1)
A first circuit supplied with a first power supply voltage and operating based on a first clock signal;
A second circuit supplied with a second power supply voltage and operating based on a second clock signal;
A phase comparison circuit that is supplied with the second power supply voltage and compares the phase of the signal corresponding to the first clock signal with the phase of the signal corresponding to the second clock signal;
A first level shift circuit that intervenes in a path leading to the phase comparison circuit, and changes a voltage level of the first clock signal;
A second level shift circuit interposed in a path leading to the phase comparison circuit and having the same circuit configuration as the first level shift circuit;
A semiconductor integrated circuit, wherein a phase difference between the first clock signal and the second clock signal is adjusted in accordance with a comparison result by the phase comparison circuit.
(Appendix 2)
When the second power supply voltage is higher than the first power supply voltage, the second clock signal is interposed in the path to the second level shift circuit, and the voltage level of the second clock signal is set. The semiconductor integrated circuit according to appendix 1, further comprising a first step-down level shift circuit that steps down the voltage.
(Appendix 3)
A first circuit supplied with a first power supply voltage and operating based on a first clock signal;
A second circuit supplied with a second power supply voltage and operating based on a second clock signal;
First and second phase comparison circuits that are supplied with the second power supply voltage and compare the phase of the signal corresponding to the first clock signal with the phase of the signal corresponding to the second clock signal;
A first level shift circuit interposed in a path leading to the first phase comparison circuit and boosting a voltage level of the first clock signal;
A second level shift circuit having the same circuit configuration as the first level shift circuit, the second clock signal interposed in a path to the first phase comparison circuit;
The first phase comparison circuit is selected when the second power supply voltage is higher than the first power supply voltage, and the first power supply voltage is higher than the second power supply voltage. A selection circuit for selecting the second phase comparison circuit in a case,
A semiconductor integrated circuit characterized by adjusting a phase difference between the first clock signal and the second clock signal in accordance with a comparison result by either the first or second phase comparison circuit selected by the selection circuit. .
(Appendix 4)
The supplementary note 3, wherein the second clock signal includes a first step-down level shift circuit that is interposed in a path to the second level shift circuit and steps down a voltage level of the second clock signal. Semiconductor integrated circuit.
(Appendix 5)
A first circuit supplied with a first power supply voltage and operating based on a first clock signal;
A second circuit supplied with a second power supply voltage and operating based on a second clock signal;
A first phase comparison circuit which is supplied with a first power supply voltage and compares the phase of the signal corresponding to the first clock signal with the phase of the signal corresponding to the second clock signal;
A second phase comparison circuit which is supplied with a second power supply voltage and compares the phase of the first clock signal with the phase of the second clock signal;
The first phase comparison circuit is selected when the second power supply voltage is higher than the first power supply voltage, and the first power supply voltage is higher than the second power supply voltage. A selection circuit for selecting the second phase comparison circuit in a case,
A semiconductor integrated circuit characterized by adjusting a phase difference between the first clock signal and the second clock signal in accordance with a comparison result by either the first or second phase comparison circuit selected by the selection circuit. .
(Appendix 6)
6. The semiconductor according to claim 5, further comprising a second step-down level shift circuit that intervenes in a path leading to the first phase comparison circuit, and that steps down the voltage level of the second clock signal. Integrated circuit.
(Appendix 7)
At least one of Supplementary notes 3 to 6, further comprising a third step-down level shift circuit that intervenes in a path leading to the second phase comparison circuit, and that steps down the voltage level of the first clock signal. The semiconductor integrated circuit according to any one of the above.
(Appendix 8)
A supplementary note comprising a fifth step-down level shift circuit having the same circuit configuration as that of the first step-down level shift circuit and having the first clock signal interposed in a path leading to the first level shift circuit. 5. The semiconductor integrated circuit according to 2 or 4.
(Appendix 9)
Supplementary note 6 comprising a sixth step-down level shift circuit having the same circuit configuration as that of the second step-down level shift circuit and having the first clock signal interposed in a path leading to the first phase comparison circuit. A semiconductor integrated circuit according to 1.
(Appendix 10)
Appendix 7 characterized by comprising a seventh step-down level shift circuit having the same circuit configuration as that of the third step-down level shift circuit and having the second clock signal interposed in the path to the second phase comparison circuit. A semiconductor integrated circuit according to 1.

Background Art Semiconductor Integrated Circuit Semiconductor integrated circuit according to the first embodiment Step-down level shift circuit Level shift circuit Semiconductor integrated circuit according to the second embodiment Semiconductor integrated circuit according to the third embodiment Semiconductor integrated circuit according to the fourth embodiment

DESCRIPTION OF SYMBOLS 1, 2 Flip-flop circuit 3A, 3B, 5 Phase comparison circuit 6, 7, 15 Level shift circuit 8 Selection circuit 9, 10, 11, 12, 13, 14 Step-down level shift circuit 100 Semiconductor integrated circuit of background art 200 1st Semiconductor integrated circuit of embodiment 300 Semiconductor integrated circuit of second embodiment 400 Semiconductor integrated circuit of third embodiment (CKA), (CKA2), (CKB), phase comparison result signal (CKBL), phase comparison result delay signal ( CK1) First clock signal (CK1D), (CK1M) First intermediate clock signal (CK1L) First delayed clock signal (CK2) Second clock signal (CK2D), (CK2M) Second intermediate clock signal (CK2L) Second Delayed clock signal (PD1) First power supply voltage (PD2) Second power supply voltage

Claims (7)

A control circuit for outputting a first clock signal and a second clock signal;
A first circuit supplied with a first power supply voltage and operating based on the first clock signal;
A second circuit that is supplied with a second power supply voltage having a voltage value different from that of the first power supply voltage and operates based on the second clock signal;
Said first and second power supply voltage is supplied, the second clock signal, a first conversion circuit low level to modify the first signal is at a high level at the ground voltage is the first power supply voltage,
Said first and second power supply voltages are supplied, the first clock signal, a first level shift circuit low is that the ground the voltage high level is changed to the second signal is the second power supply voltage ,
The first level shift circuit has the same circuit configuration, the first and second power supply voltages are supplied, and the first signal is supplied with a low level as the ground voltage and a high level as the second power supply voltage . A second level shift circuit for changing to a third signal;
A phase comparison circuit that is supplied with the second power supply voltage and compares the phase of the second signal with the phase of the third signal;
The control circuit is supplied with the second power supply voltage, and adjusts a phase difference between the first clock signal and the second clock signal according to a comparison result by the phase comparison circuit, so that the first and second clock signals are adjusted. A semiconductor integrated circuit which outputs a clock signal.   The semiconductor integrated circuit according to claim 1, wherein the second power supply voltage has a voltage value higher than that of the first power supply voltage. A control circuit for outputting a first clock signal and a second clock signal;
A first circuit supplied with a first power supply voltage and operating based on the first clock signal;
A second circuit that is supplied with a second power supply voltage having a voltage value different from that of the first power supply voltage and operates based on the second clock signal;
Said first and second power supply voltage is supplied, the second clock signal, a first conversion circuit low level to modify the first signal is at a high level at the ground voltage is the first power supply voltage,
Said first and second power supply voltage is supplied, the first clock signal, a second conversion circuit low level to modify the second signal is high level at the ground voltage is the second power supply voltage,
It said first and second power supply voltage is supplied, the first clock signal, a first level shift circuit low level is said ground voltage high level is changed to a third signal which is the second power supply voltage ,
The first level shift circuit has the same circuit configuration, the first and second power supply voltages are supplied, and the first signal is supplied with a low level as the ground voltage and a high level as the second power supply voltage . A second level shift circuit for changing to a fourth signal;
A third conversion circuit for supplying the second power supply voltage, receiving the second clock signal, and outputting a fifth signal;
A first phase comparison circuit that is supplied with the second power supply voltage and compares the phase of the third signal with the phase of the fourth signal;
A second phase comparison circuit that is supplied with the second power supply voltage and compares the phase of the second signal with the phase of the fifth signal;
The first phase comparison circuit is selected when the voltage level of the second power supply voltage is higher than the voltage level of the first power supply voltage, and the voltage level of the first power supply voltage is higher than the voltage level of the second power supply voltage. A selection circuit for selecting the second phase comparison circuit in a case,
The control circuit is supplied with the second power supply voltage, and the first clock signal and the second clock signal according to a comparison result by either the first or second phase comparison circuit selected by the selection circuit. And outputting the first and second clock signals by adjusting the phase difference between the first and second clock signals.   The first conversion circuit steps down the second clock signal to the first signal when the voltage value of the second power supply voltage is higher than the voltage value of the first power supply voltage. 4. The semiconductor integrated circuit according to 3. A control circuit for outputting a first clock signal and a second clock signal;
A first circuit supplied with a first power supply voltage and operating based on the first clock signal;
A second circuit that is supplied with a second power supply voltage having a voltage value different from that of the first power supply voltage and operates based on the second clock signal;
Said first and second power supply voltage is supplied, the second clock signal, a first conversion circuit low level to modify the first signal is at a high level at the ground voltage is the first power supply voltage,
Said first and second power supply voltage is supplied, the first clock signal, a second conversion circuit low level is said ground voltage high level is changed to the second signal is the second power supply voltage,
A third conversion circuit for supplying the second power supply voltage, receiving the second clock signal, and outputting a third signal;
A fourth conversion circuit which is supplied with the first power supply voltage, receives the first clock signal, and outputs a fourth signal;
A first phase comparison circuit which is supplied with the first power supply voltage and compares the phase of the fourth signal with the phase of the first signal;
A second phase comparison circuit that is supplied with the second power supply voltage and compares the phase of the second signal with the phase of the third signal;
The first phase comparison circuit is selected when the voltage value of the second power supply voltage is higher than the voltage value of the first power supply voltage, and the voltage value of the first power supply voltage is higher than the voltage value of the second power supply voltage. A selection circuit for selecting the second phase comparison circuit in a case,
The control circuit adjusts a phase difference between the first clock signal and the second clock signal according to a comparison result by either the first or second phase comparison circuit selected by the selection circuit, A semiconductor integrated circuit that outputs the first and second clock signals.   The first conversion circuit steps down the second clock signal to the first signal when the voltage value of the second power supply voltage is higher than the voltage value of the first power supply voltage. 5. The semiconductor integrated circuit according to 5.   The second conversion circuit steps down the first clock signal to the second signal when the voltage value of the first power supply voltage is higher than the voltage value of the second power supply voltage. The semiconductor integrated circuit according to at least one of 3 to 6.

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