JP5487640B2 - Semiconductor device, semiconductor device abnormality confirmation method, and electronic device - Google Patents

Description

  The present invention relates to a semiconductor device, an abnormality confirmation method for a semiconductor device, and a base station.

When evaluating an electronic device (for example, a base station) or in a pre-shipment inspection at the time of mass production, there is a possibility that the semiconductor device in the electronic device does not operate or starts up.
For this reason, Patent Documents 1 and 2 disclose a technique for making it possible to visually recognize whether a power supply voltage supplied to a semiconductor device is normal or not by a light emitting diode (LED) or a display.
Patent Document 3 discloses a technique for providing a monitor point for monitoring a signal of a semiconductor device.

By the way, Patent Document 4 monitors whether the voltage, sequence, and clock signal of a power source supplied to an organic EL (Electroluminescence) panel are normal, and if any one abnormality is confirmed, is supplied to the organic EL panel. A technique for shutting off a power source is disclosed.
Patent Document 5 discloses a technique for monitoring whether or not a clock signal is normal and switching to a standby circuit when an abnormality is confirmed.

JP 2006-349626 A JP 2008-268077 A Japanese Patent Laid-Open No. 5-29414 JP 2006-113471 A JP 2007-293682 A

If the cause of the failure of the semiconductor device cannot be specified, it takes a long time to debug and delays the entire shipping test. In addition, it is not efficient because the inspection man-hours due to defects are generated.
In addition, when there is a problem with the power supply or the clock signal, it may take time to confirm which is the cause.

With the techniques of Patent Documents 1 and 2, it is possible to visually recognize whether or not the voltage of the power supplied to the semiconductor device is normal using an LED or a display. Therefore, it is possible to quickly confirm that an abnormality has occurred in the voltage of the power source supplied to the semiconductor device. However, other problems with the semiconductor device may be a power supply sequence or a clock signal. In such a case, it is not possible to confirm in which case the problem has occurred.
The technique of Patent Document 3 cannot confirm a problem unless the monitor point is connected to a probe such as an oscilloscope. Moreover, it does not have a function for visualizing defects.
The techniques of Patent Documents 4 and 5 also do not have a function that can visualize defects.

  The objective of this invention is providing the semiconductor device which solves the subject mentioned above, the abnormality confirmation method of a semiconductor device, and a base station.

  A semiconductor device according to the present invention monitors a main body circuit unit and a power supply monitoring unit that monitors whether a voltage of a power source supplied to the main body circuit unit is a preset voltage and notifies the monitoring result as visualized information A sequence monitoring unit that monitors whether the sequence of power supplied to the main body circuit unit is a preset sequence and notifies the monitoring result as visualized information; and a clock supplied to the main body circuit unit A clock monitoring unit that monitors whether the signal is a preset clock signal and notifies the monitoring result as visualized information.

  A base station according to the present invention includes the above-described semiconductor device.

  The semiconductor device abnormality check method according to the present invention monitors whether or not the voltage of the power source supplied to the main body circuit unit is a preset voltage, notifies the main body circuit unit of the monitoring result as visualization information. Monitors whether the sequence of the power to be supplied is a preset sequence, notifies the monitoring result as visualized information, and determines whether the clock signal supplied to the main body circuit unit is a preset clock signal. Monitor and notify the monitoring result as visualized information.

  According to the present invention, it is possible to provide a semiconductor device, a semiconductor abnormality confirmation method, and a base station that are easy to identify a defect and that are efficient.

1 is a block diagram schematically showing a semiconductor device according to a first embodiment of the present invention. FIG. 2 is a circuit configuration diagram schematically showing a power supply monitoring unit in the semiconductor device according to the first embodiment of the present invention. 1 is a plan view schematically showing a semiconductor device according to a first embodiment of the present invention. FIG. 3 is a circuit configuration diagram schematically showing a sequence monitoring unit in the semiconductor device according to the first embodiment of the present invention. FIG. 3 is a circuit configuration diagram schematically showing a clock monitoring unit in the semiconductor device according to the first embodiment of the present invention. It is a top view which shows roughly the semiconductor device of Embodiment 2 of this invention. It is a circuit block diagram which shows the structure for performing the abnormality confirmation method of the semiconductor device of Embodiment 2 of this invention from a monitor point.

  Embodiments of a semiconductor device, a semiconductor device abnormality confirmation method, and a base station according to the present invention will be described. However, the present invention is not limited to the following embodiment. In addition, for clarity of explanation, the following description and drawings are simplified as appropriate.

<Embodiment 1>
Embodiment 1 of the present invention will be described.
As shown in FIG. 1, the semiconductor device 1 according to the present embodiment includes a main body circuit unit 2, a power supply monitoring unit 3, a sequence monitoring unit 4, and a clock monitoring unit 5.

  The main body circuit unit 2 is a drive circuit that controls the driving of the semiconductor device 1. The power monitoring unit 3 monitors whether or not the voltage of the power supplied to the main body circuit unit 2 is a preset voltage, and notifies the monitoring result as visualized information. The sequence monitoring unit 4 monitors whether or not the sequence of the power supplied to the main body circuit unit 2 is a preset sequence and notifies the monitoring result as visualized information. The clock monitoring unit 5 monitors whether or not the clock signal supplied to the main body circuit unit 2 is a preset clock signal, and notifies the monitoring result as visualized information.

  Such a semiconductor device and an abnormality confirmation method of the semiconductor device, when a failure occurs in the semiconductor device 1, the failure originates from the voltage of the power supply to which the failure is supplied, originates from the sequence, or originates from the clock signal. You can visually check what you are doing. For this reason, it is easy and efficient to identify a defect in the semiconductor device 1. That is, the malfunction of the semiconductor device 1 can be specified in a short time, and the cost can be reduced.

Next, preferred embodiments of the semiconductor device and the semiconductor device abnormality confirmation method will be described.
As shown in FIG. 2, the power supply monitoring unit 3 preferably includes a voltage dividing circuit 31 (31a, 31b), a power supply monitoring circuit 32, and a visualization unit 33 (33a, 33b). Incidentally, the power supply monitoring unit 3 of the present embodiment is supplied with the first power supply and the second power supply.

  The voltage dividing circuit 31a divides the voltage of the first power supply to such an extent that the power supply monitoring unit 3 can monitor the voltage. In the voltage dividing circuit 31a, a first resistor 311 and a second resistor 312 are connected in series. The voltage dividing circuit 31 a is connected to the power supply monitoring circuit 32 between the first resistor 311 and the second resistor 312.

  The voltage dividing circuit 31b divides the voltage of the second power supply to such an extent that the power supply monitoring unit 3 can monitor the voltage. In the voltage dividing circuit 31b, a third resistor 313 and a fourth resistor 314 are connected in series. The voltage dividing circuit 31b is connected to the power supply monitoring circuit 32 between the third resistor 313 and the fourth resistor 314.

The power monitoring circuit 32 monitors whether the divided voltage of the first power supply and the voltage of the second power supply are preset voltages, and controls the visualization unit 33 based on the monitoring result.
In other words, the divided voltage of the first power supply is supplied to the power supply monitoring circuit 32. In the power supply monitoring circuit 32, a normal voltage when the voltage of the first power supply is divided is set in advance. The power supply monitoring circuit 32 compares the set voltage with the actually divided voltage of the first power supply. At this time, when the comparison results are equal, the power supply monitoring circuit 32 outputs a signal of a high level (for example, + 3.3V) to the visualization unit 33a, and turns on the visualization unit 33a. On the other hand, when the comparison results are different, the power monitoring circuit 32 outputs a low level (for example, 0 V) signal to the visualization unit 33a and does not turn on the visualization unit 33a.

  The power supply monitoring circuit 32 is supplied with the divided voltage of the second power supply. The power monitoring circuit 32 is set in advance with a normal voltage when the voltage of the second power source is divided. The power supply monitoring circuit 32 compares the set voltage with the actually divided voltage of the second power supply. At this time, when the comparison results are equal, the power supply monitoring circuit 32 outputs a signal of a high level (for example, + 3.3V) to the visualization unit 33b, and turns on the visualization unit 33b. On the other hand, when the comparison results are different, the power monitoring circuit 32 outputs a low level (for example, 0 V) signal to the visualization unit 33b and does not turn on the visualization unit 33b.

  The visualization unit 33 (33a, 33b) is preferably an LED. The visualization unit 33 (33a, 33b) is disposed so as to be exposed from the upper surface of the semiconductor device 1. Incidentally, it is preferable that the visualization unit 33 (33a, 33b) is disposed at a corner (corner) of the semiconductor device 1 as viewed in a plan view, as shown in FIG. A relatively vacant space of the semiconductor device 1 can be used effectively.

  The anode of the visualization unit 33 a is connected to the power supply monitoring circuit 32. The cathode of the visualization unit 33a is connected to the ground terminal. The visualization unit 33a is controlled by the power supply monitoring circuit 32 based on the monitoring result of the voltage of the first power supply. That is, when the power supply monitoring circuit 32 determines that the voltage of the supplied first power supply is normal and a high level signal is input from the power supply monitoring circuit 32 to the visualization unit 33a, the visualization unit 33a is turned on. .

  The anode of the visualization unit 33 b is connected to the power supply monitoring circuit 32. The cathode of the visualization unit 33b is connected to the ground terminal. The visualization unit 33b is controlled by the power supply monitoring circuit 32 based on the monitoring result of the voltage of the second power supply. That is, when the power supply monitoring circuit 32 determines that the voltage of the supplied second power supply is normal and a high level signal is input from the power supply monitoring circuit 32 to the visualization unit 33b, the visualization unit 33b is turned on. .

  In short, the power supply monitoring unit 3 does not have a voltage set in advance by the voltage dividing circuit 31 when a voltage not used by the main body circuit unit 2 is supplied. It is determined whether or not it has been supplied.

  As shown in FIG. 4, the sequence monitoring unit 4 preferably includes a time constant circuit 41, a sequence monitoring circuit 42, and a visualization unit 43. Incidentally, the first power source and the second power source are also supplied to the sequence monitoring unit 4 of the present embodiment. At this time, the sequence monitoring unit 4 is sequentially supplied with a first power source and a second power source, which are provided with a time difference in order to perform sequence control of the main body circuit unit 2.

  The time constant circuit 41 includes a resistor 411 and a capacitor 412. The resistor 411 is provided on the wiring 44 that supplies the first power source to the sequence monitoring circuit 42. One terminal of the capacitor 412 is connected to a portion of the wiring 44 between the resistor 411 and the sequence monitoring circuit 42. The other terminal of the capacitor 412 is connected to the ground terminal. The time constant circuit 41 delays the previously supplied first power supply for a predetermined time and supplies it to the sequence monitoring circuit 42. At this time, the time for delaying the first power supply is the time difference between the first power supply and the second power supply provided for sequence control of the main body circuit unit 2 as described above.

The sequence monitoring circuit 42 monitors whether or not the first power supply and the second power supply are simultaneously supplied, and controls the visualization unit 43 based on the monitoring result.
That is, the first power source delayed by the time constant circuit 41 is supplied to the sequence monitoring circuit 42. In other words, in order to control the main body circuit unit 2 in advance, a time difference is provided with respect to the second power source, and the first power source supplied to the main body circuit unit 2 is delayed by a predetermined time by the time constant circuit 41 and sequence monitoring is performed. This is supplied to the circuit 42. Therefore, if the time difference provided in advance for the second power supply is normal, the time difference should be offset. As described above, the sequence monitoring circuit 42 is supplied with the second power source delayed in advance with a time difference from the first power source. That is, the sequence monitoring circuit 42 is provided to perform sequence control of the main body circuit unit 2 when the first power source and the second power source are simultaneously supplied to the sequence monitoring circuit 42. Therefore, it can be determined that they have a normal time difference and are supplied in the correct order. Therefore, the sequence control circuit 42 compares the supply timing of the first power supply with the supply timing of the second power supply. At this time, when the comparison results are equal, the sequence monitoring circuit 42 outputs a high level (for example, +3.3 V) signal to the visualization unit 43 and turns on the visualization unit 43. On the other hand, when the comparison results are different, the sequence monitoring circuit 42 outputs a low level (for example, 0 V) signal to the visualization unit 43 and does not turn on the visualization unit 43.

  The visualization unit 43 is preferably an LED. The visualization unit 43 is disposed so as to be exposed from the upper surface of the semiconductor device 1. Incidentally, it is preferable that the visualization part 43 is arrange | positioned at the corner part of the semiconductor device 1, as shown in FIG. A relatively vacant space of the semiconductor device 1 can be used effectively.

  The anode of the visualization unit 43 is connected to the sequence monitoring circuit 42. The cathode of the visualization unit 43 is connected to the ground terminal. The visualization unit 43 is controlled by the sequence monitoring circuit 42 based on the monitoring result of the power supply sequence. That is, when the sequence monitoring circuit 42 determines that the sequence of the supplied power is normal and a high level signal is input from the sequence monitoring circuit 42 to the visualization unit 43, the visualization unit 43 is turned on.

As illustrated in FIG. 5, the clock monitoring unit 5 includes a clock monitoring circuit 51 and a visualization unit 52.
The clock monitoring circuit 51 monitors whether or not the clock signal supplied to the main body circuit unit 2 is a preset clock signal, and controls the visualization unit 52 based on the monitoring result. That is, the clock monitoring circuit 51 is supplied with the clock signal supplied to the main body circuit unit 2. Here, if the clock signal supplied to the clock monitoring circuit 51 is normal, the clock signal changes (High to Low, or Low to High). If the clock signal is abnormal, the clock signal should not change. is there. Therefore, the clock monitoring circuit 51 determines whether or not there is a change in the clock signal within a certain time. At this time, when the comparison result is “changed”, the clock monitoring circuit 51 outputs a low level (for example, 0 V) signal to the visualization unit 52 to light the visualization unit 52. On the other hand, when the comparison result is “no change”, the clock monitoring circuit 51 outputs a high level signal (for example, about +2.7 V) to the visualization unit 52 and does not light the visualization unit 52.

  The visualization unit 52 is preferably an LED. The visualization unit 52 is disposed so as to be exposed from the upper surface of the semiconductor device 1. Incidentally, it is preferable that the visualization part 52 is arrange | positioned at the corner part of the semiconductor device 1, as shown in FIG. A relatively vacant space of the semiconductor device 1 can be used effectively.

  The anode of the visualization unit 52 is connected to the power supply side. The cathode of the visualization unit 52 is connected to the clock monitoring circuit 51. The visualization unit 52 is controlled by the clock monitoring circuit 51 based on the monitoring result of the clock signal. That is, when the clock monitoring circuit 51 determines that the supplied clock signal is normal and a low level signal is input from the clock monitoring circuit 51 to the visualization unit 52, the visualization unit 52 is turned on. On the other hand, when the clock monitoring circuit 51 determines that an abnormality occurs in the supplied clock signal and a high level signal is input from the clock monitoring circuit 51 to the visualization unit 52, the visualization unit 52 is turned off.

  In such a semiconductor device and a semiconductor abnormality confirmation method, when a failure occurs in the semiconductor device 1, the failure is caused by a voltage of a power supply to which the failure is supplied, a sequence, or a clock signal. It can be visually confirmed by each visualization part whether it is what to do. For this reason, it is easy and efficient to identify a defect in the semiconductor device 1. That is, the malfunction of the semiconductor device 1 can be identified in a short time, and as a result, the number of personnel for identifying the malfunction can be reduced. In addition, the semiconductor device abnormality check method can be automatically performed without using a tester or an oscilloscope. Therefore, it can also contribute to cost reduction.

<Embodiment 2>
A second embodiment of the present invention will be described.
The semiconductor device 100 according to the second embodiment has substantially the same configuration as that of the semiconductor device 1 according to the first embodiment. However, it is possible to separately confirm the abnormality of the semiconductor using a tester, an oscilloscope, or the like. It is configured.

  That is, as shown in FIG. 6, the semiconductor device 100 has a monitor point 101 that detects the voltage of the first power source supplied to the main body circuit unit 2 so as to be exposed from the surface of the semiconductor device 100. The semiconductor device 100 also has a monitor point 102 that detects the voltage of the second power source supplied to the main body circuit unit 2 so as to be exposed from the surface of the semiconductor device 100. Furthermore, the semiconductor device 100 includes a monitor point 103 that detects a clock signal supplied to the main body circuit unit 2 so as to be exposed from the surface of the semiconductor device 100.

  Specifically, as shown in FIG. 7, the semiconductor device 100 includes a monitor circuit 104 which is an internal wiring so that a first power supply, a second power supply, and a clock signal can be extracted. The circuit 104 and the respective monitor points 101, 102, 103 are connected.

With such a semiconductor device 100, in addition to the above-described functions and effects, it is possible to easily check the abnormality of the semiconductor even in an emergency such as when the visualization unit is damaged.
In this embodiment, the monitor points 101 and 102 for detecting the voltage and the monitor point 103 for detecting the clock signal are provided, but either one may be used.

<Embodiment 3>
The semiconductor device 1 (100) having the above-described configuration can be suitably used when configuring a base station.
That is, the base station includes a transmission device, a reception device, a signal demultiplexing device, and the like, and the semiconductor device having the above-described configuration may be used as a semiconductor device used in these devices. Such a base station can visually confirm in which device the malfunction occurs when a malfunction occurs. In addition, it is possible to visually confirm in which semiconductor device the defect has occurred. Further, in the semiconductor device, it is possible to visually confirm whether there is a problem with the voltage, a problem with the sequence, or a problem with the clock signal. For this reason, it is possible to quickly and easily confirm the abnormality of a large-scale base station.

  The present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention. For example, in the above-described embodiment, the first power source and the second power source are supplied to the main body circuit unit, but the number of supplied power sources is not particularly limited. In this case, for example, all the power is supplied to the power monitoring unit. Further, the power supplied with a time difference is supplied to the sequence monitoring circuit with each power source delayed by a time constant circuit with reference to the power source supplied with the most delay.

  In the above embodiment, the power supply voltage is divided by the voltage dividing circuit and then supplied to the power supply monitoring circuit, but this is not restrictive. Means for lowering the voltage to such an extent that the power supply monitoring circuit can monitor the voltage is not particularly limited.

  In the above embodiment, the first power supply is delayed by the time constant circuit and supplied to the sequence monitoring circuit, but this is not restrictive. For example, the time difference between the first power source and the second power source may be measured in the sequence monitoring circuit, and it may be determined whether or not the sequence is normal based on the measurement result.

  In the above-described embodiment, the visualization unit is arranged at the corner of the semiconductor device when viewed from above, but the arrangement is not particularly limited. In short, it should just be arrange | positioned in the position which can visually recognize a visualization part from the outside. Moreover, a visualization part is not limited to LED. The visualization unit may be any means that can be visually recognized from the outside.

DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Main body circuit part 3 Power supply monitoring part, 31 (31a, 31b) Voltage dividing circuit, 32 Power supply monitoring circuit, 33 (33a, 33b) Visualization part 4 Sequence monitoring part, 41 Time constant circuit, 42 Sequence monitoring circuit, 43 Visualization unit, 44 Wiring 5 Clock monitoring unit, 51 Clock monitoring circuit, 52 Visualization unit 100 Semiconductor devices 101, 102, 103 Monitor point 104 Monitor circuit

Claims (12)

Main circuit section,
A power monitoring unit that monitors whether the voltage of the power supplied to the main body circuit unit is a preset voltage, and notifies the monitoring result as visualized information;
A sequence monitoring unit that monitors whether the sequence of power supplied to the main body circuit unit is a preset sequence and notifies the monitoring result as visualized information;
A clock monitoring unit that monitors whether the clock signal supplied to the main body circuit unit is a preset clock signal and notifies the monitoring result as visualized information;
Equipped with a,
The sequence monitoring unit includes a sequence monitoring circuit, a visualization unit, and a time constant circuit,
The sequence monitoring unit is supplied with a first power source and a second power source in order at a time difference,
The time constant circuit delays the first power supply for a predetermined time and supplies the first power supply to the sequence monitoring circuit.
Said sequence monitoring circuit, the first power supply and said second power supply monitors whether or not simultaneously supplied, based on the monitoring result, the semiconductor device that controls the visualization unit. The power monitoring unit includes a power monitoring circuit and a visualization unit,
The power supply monitoring circuit monitors whether or not a voltage of a power supply supplied to the main body circuit unit is a preset voltage, and controls the visualization unit based on the monitoring result. 2. The semiconductor device according to 1. The clock monitoring unit includes a clock monitoring circuit and a visualization unit,
The clock monitoring circuit monitors whether or not a clock signal supplied to the main body circuit unit is a preset clock signal, and controls the visualization unit based on the monitoring result. 2. The semiconductor device according to 1. The power monitoring unit further includes a voltage dividing circuit,
The semiconductor device according to claim 2, wherein the voltage dividing circuit divides a voltage of a power source supplied to the main body circuit unit and supplies the divided voltage to the power source monitoring circuit. The semiconductor device according to any one of claims 1 to 4, characterized in that it has a monitoring point for detecting the voltage of the power supplied to the main circuit portion. 6. The semiconductor device according to claim 5 , comprising a plurality of monitor points for detecting the voltage. The semiconductor device according to any one of claims 1 to 6, characterized in that it has a monitoring point for detecting a clock signal supplied to the main circuit portion. Wherein the visualization unit is a semiconductor device according to any one of claims 1 to 3, characterized in that a light emitting diode. The semiconductor device according to claim 8 , wherein the light emitting diode is disposed at a corner of the semiconductor device. An electronic device having a semiconductor device according to any one of claims 1 to 9. Monitor whether the power supply voltage supplied to the main circuit section is a preset voltage, and notify the monitoring result as visualized information,
Monitors whether the sequence of power supplied to the main circuit section is a preset sequence, and notifies the monitoring result as visualized information,
A method for checking an abnormality of a semiconductor device for monitoring whether a clock signal supplied to a main body circuit unit is a preset clock signal and notifying the monitoring result as visualized information ,
When monitoring whether or not the sequence of power supplied to the main body circuit unit is a preset sequence, a time difference is provided in advance with respect to the second power source, and the first first supplied to the main body circuit unit. A method for confirming an abnormality in a semiconductor device, wherein a power supply is delayed for a predetermined time and whether or not the first power supply and the second power supply are simultaneously supplied is monitored . When monitoring whether the voltage of the power source supplied to the main body circuit unit is a preset voltage, the voltage of the power source supplied to the main body circuit unit is divided, and the divided voltage is preset. 12. The semiconductor device abnormality confirmation method according to claim 11 , wherein the voltage is monitored.

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